148489980SSeiya Wang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 248489980SSeiya Wang/* 348489980SSeiya Wang * Copyright (C) 2020 MediaTek Inc. 448489980SSeiya Wang * Author: Seiya Wang <seiya.wang@mediatek.com> 548489980SSeiya Wang */ 648489980SSeiya Wang 748489980SSeiya Wang/dts-v1/; 85d2b897bSChun-Jie Chen#include <dt-bindings/clock/mt8192-clk.h> 9b4b75bacSAllen-KH Cheng#include <dt-bindings/gce/mt8192-gce.h> 1048489980SSeiya Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 1148489980SSeiya Wang#include <dt-bindings/interrupt-controller/irq.h> 124a65b0f1SAllen-KH Cheng#include <dt-bindings/memory/mt8192-larb-port.h> 1348489980SSeiya Wang#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14e5aac225SAllen-KH Cheng#include <dt-bindings/phy/phy.h> 15994a71a3SChun-Jie Chen#include <dt-bindings/power/mt8192-power.h> 167d355378SAllen-KH Cheng#include <dt-bindings/reset/mt8192-resets.h> 1748489980SSeiya Wang 1848489980SSeiya Wang/ { 1948489980SSeiya Wang compatible = "mediatek,mt8192"; 2048489980SSeiya Wang interrupt-parent = <&gic>; 2148489980SSeiya Wang #address-cells = <2>; 2248489980SSeiya Wang #size-cells = <2>; 2348489980SSeiya Wang 24b4b75bacSAllen-KH Cheng aliases { 25b4b75bacSAllen-KH Cheng ovl0 = &ovl0; 26b4b75bacSAllen-KH Cheng ovl-2l0 = &ovl_2l0; 27b4b75bacSAllen-KH Cheng ovl-2l2 = &ovl_2l2; 28b4b75bacSAllen-KH Cheng rdma0 = &rdma0; 29b4b75bacSAllen-KH Cheng rdma4 = &rdma4; 30b4b75bacSAllen-KH Cheng }; 31b4b75bacSAllen-KH Cheng 32f19f68e5SChen-Yu Tsai clk13m: fixed-factor-clock-13m { 33f19f68e5SChen-Yu Tsai compatible = "fixed-factor-clock"; 34f19f68e5SChen-Yu Tsai #clock-cells = <0>; 35f19f68e5SChen-Yu Tsai clocks = <&clk26m>; 36f19f68e5SChen-Yu Tsai clock-div = <2>; 37f19f68e5SChen-Yu Tsai clock-mult = <1>; 38f19f68e5SChen-Yu Tsai clock-output-names = "clk13m"; 39f19f68e5SChen-Yu Tsai }; 40f19f68e5SChen-Yu Tsai 4148489980SSeiya Wang clk26m: oscillator0 { 4248489980SSeiya Wang compatible = "fixed-clock"; 4348489980SSeiya Wang #clock-cells = <0>; 4448489980SSeiya Wang clock-frequency = <26000000>; 4548489980SSeiya Wang clock-output-names = "clk26m"; 4648489980SSeiya Wang }; 4748489980SSeiya Wang 4848489980SSeiya Wang clk32k: oscillator1 { 4948489980SSeiya Wang compatible = "fixed-clock"; 5048489980SSeiya Wang #clock-cells = <0>; 5148489980SSeiya Wang clock-frequency = <32768>; 5248489980SSeiya Wang clock-output-names = "clk32k"; 5348489980SSeiya Wang }; 5448489980SSeiya Wang 5548489980SSeiya Wang cpus { 5648489980SSeiya Wang #address-cells = <1>; 5748489980SSeiya Wang #size-cells = <0>; 5848489980SSeiya Wang 5948489980SSeiya Wang cpu0: cpu@0 { 6048489980SSeiya Wang device_type = "cpu"; 6148489980SSeiya Wang compatible = "arm,cortex-a55"; 6248489980SSeiya Wang reg = <0x000>; 6348489980SSeiya Wang enable-method = "psci"; 6448489980SSeiya Wang clock-frequency = <1701000000>; 65090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 6629288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 6729288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 6829288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 6929288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 7029288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 7129288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 7248489980SSeiya Wang next-level-cache = <&l2_0>; 739d498cceSAllen-KH Cheng performance-domains = <&performance 0>; 74a4366b56SNícolas F. R. A. Prado capacity-dmips-mhz = <427>; 7548489980SSeiya Wang }; 7648489980SSeiya Wang 7748489980SSeiya Wang cpu1: cpu@100 { 7848489980SSeiya Wang device_type = "cpu"; 7948489980SSeiya Wang compatible = "arm,cortex-a55"; 8048489980SSeiya Wang reg = <0x100>; 8148489980SSeiya Wang enable-method = "psci"; 8248489980SSeiya Wang clock-frequency = <1701000000>; 83090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 8429288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 8529288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 8629288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 8729288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 8829288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 8929288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 9048489980SSeiya Wang next-level-cache = <&l2_0>; 919d498cceSAllen-KH Cheng performance-domains = <&performance 0>; 92a4366b56SNícolas F. R. A. Prado capacity-dmips-mhz = <427>; 9348489980SSeiya Wang }; 9448489980SSeiya Wang 9548489980SSeiya Wang cpu2: cpu@200 { 9648489980SSeiya Wang device_type = "cpu"; 9748489980SSeiya Wang compatible = "arm,cortex-a55"; 9848489980SSeiya Wang reg = <0x200>; 9948489980SSeiya Wang enable-method = "psci"; 10048489980SSeiya Wang clock-frequency = <1701000000>; 101090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 10229288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 10329288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 10429288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 10529288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 10629288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 10729288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 10848489980SSeiya Wang next-level-cache = <&l2_0>; 1099d498cceSAllen-KH Cheng performance-domains = <&performance 0>; 110a4366b56SNícolas F. R. A. Prado capacity-dmips-mhz = <427>; 11148489980SSeiya Wang }; 11248489980SSeiya Wang 11348489980SSeiya Wang cpu3: cpu@300 { 11448489980SSeiya Wang device_type = "cpu"; 11548489980SSeiya Wang compatible = "arm,cortex-a55"; 11648489980SSeiya Wang reg = <0x300>; 11748489980SSeiya Wang enable-method = "psci"; 11848489980SSeiya Wang clock-frequency = <1701000000>; 119090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 12029288babSAngeloGioacchino Del Regno i-cache-size = <32768>; 12129288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 12229288babSAngeloGioacchino Del Regno i-cache-sets = <128>; 12329288babSAngeloGioacchino Del Regno d-cache-size = <32768>; 12429288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 12529288babSAngeloGioacchino Del Regno d-cache-sets = <128>; 12648489980SSeiya Wang next-level-cache = <&l2_0>; 1279d498cceSAllen-KH Cheng performance-domains = <&performance 0>; 128a4366b56SNícolas F. R. A. Prado capacity-dmips-mhz = <427>; 12948489980SSeiya Wang }; 13048489980SSeiya Wang 13148489980SSeiya Wang cpu4: cpu@400 { 13248489980SSeiya Wang device_type = "cpu"; 13348489980SSeiya Wang compatible = "arm,cortex-a76"; 13448489980SSeiya Wang reg = <0x400>; 13548489980SSeiya Wang enable-method = "psci"; 13648489980SSeiya Wang clock-frequency = <2171000000>; 137090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 13829288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 13929288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 14029288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 14129288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 14229288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 14329288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 14448489980SSeiya Wang next-level-cache = <&l2_1>; 1459d498cceSAllen-KH Cheng performance-domains = <&performance 1>; 14648489980SSeiya Wang capacity-dmips-mhz = <1024>; 14748489980SSeiya Wang }; 14848489980SSeiya Wang 14948489980SSeiya Wang cpu5: cpu@500 { 15048489980SSeiya Wang device_type = "cpu"; 15148489980SSeiya Wang compatible = "arm,cortex-a76"; 15248489980SSeiya Wang reg = <0x500>; 15348489980SSeiya Wang enable-method = "psci"; 15448489980SSeiya Wang clock-frequency = <2171000000>; 155090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 15629288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 15729288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 15829288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 15929288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 16029288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 16129288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 16248489980SSeiya Wang next-level-cache = <&l2_1>; 1639d498cceSAllen-KH Cheng performance-domains = <&performance 1>; 16448489980SSeiya Wang capacity-dmips-mhz = <1024>; 16548489980SSeiya Wang }; 16648489980SSeiya Wang 16748489980SSeiya Wang cpu6: cpu@600 { 16848489980SSeiya Wang device_type = "cpu"; 16948489980SSeiya Wang compatible = "arm,cortex-a76"; 17048489980SSeiya Wang reg = <0x600>; 17148489980SSeiya Wang enable-method = "psci"; 17248489980SSeiya Wang clock-frequency = <2171000000>; 173090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 17429288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 17529288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 17629288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 17729288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 17829288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 17929288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 18048489980SSeiya Wang next-level-cache = <&l2_1>; 1819d498cceSAllen-KH Cheng performance-domains = <&performance 1>; 18248489980SSeiya Wang capacity-dmips-mhz = <1024>; 18348489980SSeiya Wang }; 18448489980SSeiya Wang 18548489980SSeiya Wang cpu7: cpu@700 { 18648489980SSeiya Wang device_type = "cpu"; 18748489980SSeiya Wang compatible = "arm,cortex-a76"; 18848489980SSeiya Wang reg = <0x700>; 18948489980SSeiya Wang enable-method = "psci"; 19048489980SSeiya Wang clock-frequency = <2171000000>; 191090bd20cSAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 19229288babSAngeloGioacchino Del Regno i-cache-size = <65536>; 19329288babSAngeloGioacchino Del Regno i-cache-line-size = <64>; 19429288babSAngeloGioacchino Del Regno i-cache-sets = <256>; 19529288babSAngeloGioacchino Del Regno d-cache-size = <65536>; 19629288babSAngeloGioacchino Del Regno d-cache-line-size = <64>; 19729288babSAngeloGioacchino Del Regno d-cache-sets = <256>; 19848489980SSeiya Wang next-level-cache = <&l2_1>; 1999d498cceSAllen-KH Cheng performance-domains = <&performance 1>; 20048489980SSeiya Wang capacity-dmips-mhz = <1024>; 20148489980SSeiya Wang }; 20248489980SSeiya Wang 20348489980SSeiya Wang cpu-map { 20448489980SSeiya Wang cluster0 { 20548489980SSeiya Wang core0 { 20648489980SSeiya Wang cpu = <&cpu0>; 20748489980SSeiya Wang }; 20848489980SSeiya Wang core1 { 20948489980SSeiya Wang cpu = <&cpu1>; 21048489980SSeiya Wang }; 21148489980SSeiya Wang core2 { 21248489980SSeiya Wang cpu = <&cpu2>; 21348489980SSeiya Wang }; 21448489980SSeiya Wang core3 { 21548489980SSeiya Wang cpu = <&cpu3>; 21648489980SSeiya Wang }; 217160ce54dSAngeloGioacchino Del Regno core4 { 21848489980SSeiya Wang cpu = <&cpu4>; 21948489980SSeiya Wang }; 220160ce54dSAngeloGioacchino Del Regno core5 { 22148489980SSeiya Wang cpu = <&cpu5>; 22248489980SSeiya Wang }; 223160ce54dSAngeloGioacchino Del Regno core6 { 22448489980SSeiya Wang cpu = <&cpu6>; 22548489980SSeiya Wang }; 226160ce54dSAngeloGioacchino Del Regno core7 { 22748489980SSeiya Wang cpu = <&cpu7>; 22848489980SSeiya Wang }; 22948489980SSeiya Wang }; 23048489980SSeiya Wang }; 23148489980SSeiya Wang 23248489980SSeiya Wang l2_0: l2-cache0 { 23348489980SSeiya Wang compatible = "cache"; 234ce459b1dSPierre Gondois cache-level = <2>; 23529288babSAngeloGioacchino Del Regno cache-size = <131072>; 23629288babSAngeloGioacchino Del Regno cache-line-size = <64>; 23729288babSAngeloGioacchino Del Regno cache-sets = <512>; 23848489980SSeiya Wang next-level-cache = <&l3_0>; 239492061bfSKrzysztof Kozlowski cache-unified; 24048489980SSeiya Wang }; 24148489980SSeiya Wang 24248489980SSeiya Wang l2_1: l2-cache1 { 24348489980SSeiya Wang compatible = "cache"; 244ce459b1dSPierre Gondois cache-level = <2>; 24529288babSAngeloGioacchino Del Regno cache-size = <262144>; 24629288babSAngeloGioacchino Del Regno cache-line-size = <64>; 24729288babSAngeloGioacchino Del Regno cache-sets = <512>; 24848489980SSeiya Wang next-level-cache = <&l3_0>; 249492061bfSKrzysztof Kozlowski cache-unified; 25048489980SSeiya Wang }; 25148489980SSeiya Wang 25248489980SSeiya Wang l3_0: l3-cache { 25348489980SSeiya Wang compatible = "cache"; 254ce459b1dSPierre Gondois cache-level = <3>; 25529288babSAngeloGioacchino Del Regno cache-size = <2097152>; 25629288babSAngeloGioacchino Del Regno cache-line-size = <64>; 25729288babSAngeloGioacchino Del Regno cache-sets = <2048>; 25829288babSAngeloGioacchino Del Regno cache-unified; 25948489980SSeiya Wang }; 2609260918dSJames Liao 2619260918dSJames Liao idle-states { 2622e599740SNícolas F. R. A. Prado entry-method = "psci"; 263090bd20cSAngeloGioacchino Del Regno cpu_ret_l: cpu-retention-l { 2649260918dSJames Liao compatible = "arm,idle-state"; 2659260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2669260918dSJames Liao local-timer-stop; 2679260918dSJames Liao entry-latency-us = <55>; 2689260918dSJames Liao exit-latency-us = <140>; 2699260918dSJames Liao min-residency-us = <780>; 2709260918dSJames Liao }; 271090bd20cSAngeloGioacchino Del Regno cpu_ret_b: cpu-retention-b { 2729260918dSJames Liao compatible = "arm,idle-state"; 2739260918dSJames Liao arm,psci-suspend-param = <0x00010001>; 2749260918dSJames Liao local-timer-stop; 2759260918dSJames Liao entry-latency-us = <35>; 2769260918dSJames Liao exit-latency-us = <145>; 2779260918dSJames Liao min-residency-us = <720>; 2789260918dSJames Liao }; 279090bd20cSAngeloGioacchino Del Regno cpu_off_l: cpu-off-l { 2809260918dSJames Liao compatible = "arm,idle-state"; 2819260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2829260918dSJames Liao local-timer-stop; 2839260918dSJames Liao entry-latency-us = <60>; 2849260918dSJames Liao exit-latency-us = <155>; 2859260918dSJames Liao min-residency-us = <860>; 2869260918dSJames Liao }; 287090bd20cSAngeloGioacchino Del Regno cpu_off_b: cpu-off-b { 2889260918dSJames Liao compatible = "arm,idle-state"; 2899260918dSJames Liao arm,psci-suspend-param = <0x01010002>; 2909260918dSJames Liao local-timer-stop; 2919260918dSJames Liao entry-latency-us = <40>; 2929260918dSJames Liao exit-latency-us = <155>; 2939260918dSJames Liao min-residency-us = <780>; 2949260918dSJames Liao }; 2959260918dSJames Liao }; 29648489980SSeiya Wang }; 29748489980SSeiya Wang 29848489980SSeiya Wang pmu-a55 { 29948489980SSeiya Wang compatible = "arm,cortex-a55-pmu"; 30048489980SSeiya Wang interrupt-parent = <&gic>; 30148489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 30248489980SSeiya Wang }; 30348489980SSeiya Wang 30448489980SSeiya Wang pmu-a76 { 30548489980SSeiya Wang compatible = "arm,cortex-a76-pmu"; 30648489980SSeiya Wang interrupt-parent = <&gic>; 30748489980SSeiya Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 30848489980SSeiya Wang }; 30948489980SSeiya Wang 31048489980SSeiya Wang psci { 31148489980SSeiya Wang compatible = "arm,psci-1.0"; 31248489980SSeiya Wang method = "smc"; 31348489980SSeiya Wang }; 31448489980SSeiya Wang 31548489980SSeiya Wang timer: timer { 31648489980SSeiya Wang compatible = "arm,armv8-timer"; 31748489980SSeiya Wang interrupt-parent = <&gic>; 31848489980SSeiya Wang interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 31948489980SSeiya Wang <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 32048489980SSeiya Wang <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 32148489980SSeiya Wang <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 32248489980SSeiya Wang clock-frequency = <13000000>; 32348489980SSeiya Wang }; 32448489980SSeiya Wang 325e1233345SAlyssa Rosenzweig gpu_opp_table: opp-table-0 { 326e1233345SAlyssa Rosenzweig compatible = "operating-points-v2"; 327e1233345SAlyssa Rosenzweig opp-shared; 328e1233345SAlyssa Rosenzweig 329e1233345SAlyssa Rosenzweig opp-358000000 { 330e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <358000000>; 331e1233345SAlyssa Rosenzweig opp-microvolt = <606250>; 332e1233345SAlyssa Rosenzweig }; 333e1233345SAlyssa Rosenzweig 334e1233345SAlyssa Rosenzweig opp-399000000 { 335e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <399000000>; 336e1233345SAlyssa Rosenzweig opp-microvolt = <618750>; 337e1233345SAlyssa Rosenzweig }; 338e1233345SAlyssa Rosenzweig 339e1233345SAlyssa Rosenzweig opp-440000000 { 340e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <440000000>; 341e1233345SAlyssa Rosenzweig opp-microvolt = <631250>; 342e1233345SAlyssa Rosenzweig }; 343e1233345SAlyssa Rosenzweig 344e1233345SAlyssa Rosenzweig opp-482000000 { 345e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <482000000>; 346e1233345SAlyssa Rosenzweig opp-microvolt = <643750>; 347e1233345SAlyssa Rosenzweig }; 348e1233345SAlyssa Rosenzweig 349e1233345SAlyssa Rosenzweig opp-523000000 { 350e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <523000000>; 351e1233345SAlyssa Rosenzweig opp-microvolt = <656250>; 352e1233345SAlyssa Rosenzweig }; 353e1233345SAlyssa Rosenzweig 354e1233345SAlyssa Rosenzweig opp-564000000 { 355e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <564000000>; 356e1233345SAlyssa Rosenzweig opp-microvolt = <668750>; 357e1233345SAlyssa Rosenzweig }; 358e1233345SAlyssa Rosenzweig 359e1233345SAlyssa Rosenzweig opp-605000000 { 360e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <605000000>; 361e1233345SAlyssa Rosenzweig opp-microvolt = <681250>; 362e1233345SAlyssa Rosenzweig }; 363e1233345SAlyssa Rosenzweig 364e1233345SAlyssa Rosenzweig opp-647000000 { 365e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <647000000>; 366e1233345SAlyssa Rosenzweig opp-microvolt = <693750>; 367e1233345SAlyssa Rosenzweig }; 368e1233345SAlyssa Rosenzweig 369e1233345SAlyssa Rosenzweig opp-688000000 { 370e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <688000000>; 371e1233345SAlyssa Rosenzweig opp-microvolt = <706250>; 372e1233345SAlyssa Rosenzweig }; 373e1233345SAlyssa Rosenzweig 374e1233345SAlyssa Rosenzweig opp-724000000 { 375e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <724000000>; 376e1233345SAlyssa Rosenzweig opp-microvolt = <725000>; 377e1233345SAlyssa Rosenzweig }; 378e1233345SAlyssa Rosenzweig 379e1233345SAlyssa Rosenzweig opp-748000000 { 380e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <748000000>; 381e1233345SAlyssa Rosenzweig opp-microvolt = <737500>; 382e1233345SAlyssa Rosenzweig }; 383e1233345SAlyssa Rosenzweig 384e1233345SAlyssa Rosenzweig opp-772000000 { 385e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <772000000>; 386e1233345SAlyssa Rosenzweig opp-microvolt = <750000>; 387e1233345SAlyssa Rosenzweig }; 388e1233345SAlyssa Rosenzweig 389e1233345SAlyssa Rosenzweig opp-795000000 { 390e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <795000000>; 391e1233345SAlyssa Rosenzweig opp-microvolt = <762500>; 392e1233345SAlyssa Rosenzweig }; 393e1233345SAlyssa Rosenzweig 394e1233345SAlyssa Rosenzweig opp-819000000 { 395e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <819000000>; 396e1233345SAlyssa Rosenzweig opp-microvolt = <775000>; 397e1233345SAlyssa Rosenzweig }; 398e1233345SAlyssa Rosenzweig 399e1233345SAlyssa Rosenzweig opp-843000000 { 400e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <843000000>; 401e1233345SAlyssa Rosenzweig opp-microvolt = <787500>; 402e1233345SAlyssa Rosenzweig }; 403e1233345SAlyssa Rosenzweig 404e1233345SAlyssa Rosenzweig opp-866000000 { 405e1233345SAlyssa Rosenzweig opp-hz = /bits/ 64 <866000000>; 406e1233345SAlyssa Rosenzweig opp-microvolt = <800000>; 407e1233345SAlyssa Rosenzweig }; 408e1233345SAlyssa Rosenzweig }; 409e1233345SAlyssa Rosenzweig 41048489980SSeiya Wang soc { 41148489980SSeiya Wang #address-cells = <2>; 41248489980SSeiya Wang #size-cells = <2>; 41348489980SSeiya Wang compatible = "simple-bus"; 4146970cadbSNícolas F. R. A. Prado dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 41548489980SSeiya Wang ranges; 41648489980SSeiya Wang 4179d498cceSAllen-KH Cheng performance: performance-controller@11bc10 { 4189d498cceSAllen-KH Cheng compatible = "mediatek,cpufreq-hw"; 4199d498cceSAllen-KH Cheng reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 4209d498cceSAllen-KH Cheng #performance-domain-cells = <1>; 4219d498cceSAllen-KH Cheng }; 4229d498cceSAllen-KH Cheng 42348489980SSeiya Wang gic: interrupt-controller@c000000 { 42448489980SSeiya Wang compatible = "arm,gic-v3"; 42548489980SSeiya Wang #interrupt-cells = <4>; 42648489980SSeiya Wang #redistributor-regions = <1>; 42748489980SSeiya Wang interrupt-parent = <&gic>; 42848489980SSeiya Wang interrupt-controller; 42948489980SSeiya Wang reg = <0 0x0c000000 0 0x40000>, 43048489980SSeiya Wang <0 0x0c040000 0 0x200000>; 43148489980SSeiya Wang interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 43248489980SSeiya Wang 43348489980SSeiya Wang ppi-partitions { 43448489980SSeiya Wang ppi_cluster0: interrupt-partition-0 { 43548489980SSeiya Wang affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 43648489980SSeiya Wang }; 43748489980SSeiya Wang ppi_cluster1: interrupt-partition-1 { 43848489980SSeiya Wang affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 43948489980SSeiya Wang }; 44048489980SSeiya Wang }; 44148489980SSeiya Wang }; 44248489980SSeiya Wang 4435d2b897bSChun-Jie Chen topckgen: syscon@10000000 { 4445d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-topckgen", "syscon"; 4455d2b897bSChun-Jie Chen reg = <0 0x10000000 0 0x1000>; 4465d2b897bSChun-Jie Chen #clock-cells = <1>; 4475d2b897bSChun-Jie Chen }; 4485d2b897bSChun-Jie Chen 4495d2b897bSChun-Jie Chen infracfg: syscon@10001000 { 4505d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-infracfg", "syscon"; 4515d2b897bSChun-Jie Chen reg = <0 0x10001000 0 0x1000>; 4525d2b897bSChun-Jie Chen #clock-cells = <1>; 453a30cc07fSRex-BC Chen #reset-cells = <1>; 4545d2b897bSChun-Jie Chen }; 4555d2b897bSChun-Jie Chen 4565d2b897bSChun-Jie Chen pericfg: syscon@10003000 { 4575d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-pericfg", "syscon"; 4585d2b897bSChun-Jie Chen reg = <0 0x10003000 0 0x1000>; 4595d2b897bSChun-Jie Chen #clock-cells = <1>; 4605d2b897bSChun-Jie Chen }; 4615d2b897bSChun-Jie Chen 46248489980SSeiya Wang pio: pinctrl@10005000 { 46348489980SSeiya Wang compatible = "mediatek,mt8192-pinctrl"; 46448489980SSeiya Wang reg = <0 0x10005000 0 0x1000>, 46548489980SSeiya Wang <0 0x11c20000 0 0x1000>, 46648489980SSeiya Wang <0 0x11d10000 0 0x1000>, 46748489980SSeiya Wang <0 0x11d30000 0 0x1000>, 46848489980SSeiya Wang <0 0x11d40000 0 0x1000>, 46948489980SSeiya Wang <0 0x11e20000 0 0x1000>, 47048489980SSeiya Wang <0 0x11e70000 0 0x1000>, 47148489980SSeiya Wang <0 0x11ea0000 0 0x1000>, 47248489980SSeiya Wang <0 0x11f20000 0 0x1000>, 47348489980SSeiya Wang <0 0x11f30000 0 0x1000>, 47448489980SSeiya Wang <0 0x1000b000 0 0x1000>; 47548489980SSeiya Wang reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 47648489980SSeiya Wang "iocfg_bl", "iocfg_br", "iocfg_lm", 47748489980SSeiya Wang "iocfg_lb", "iocfg_rt", "iocfg_lt", 47848489980SSeiya Wang "iocfg_tl", "eint"; 47948489980SSeiya Wang gpio-controller; 48048489980SSeiya Wang #gpio-cells = <2>; 48148489980SSeiya Wang gpio-ranges = <&pio 0 0 220>; 48248489980SSeiya Wang interrupt-controller; 48348489980SSeiya Wang interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 48448489980SSeiya Wang #interrupt-cells = <2>; 48548489980SSeiya Wang }; 48648489980SSeiya Wang 487994a71a3SChun-Jie Chen scpsys: syscon@10006000 { 488d3dfd468STinghan Shen compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 489994a71a3SChun-Jie Chen reg = <0 0x10006000 0 0x1000>; 490994a71a3SChun-Jie Chen 491994a71a3SChun-Jie Chen /* System Power Manager */ 492994a71a3SChun-Jie Chen spm: power-controller { 493994a71a3SChun-Jie Chen compatible = "mediatek,mt8192-power-controller"; 494994a71a3SChun-Jie Chen #address-cells = <1>; 495994a71a3SChun-Jie Chen #size-cells = <0>; 496994a71a3SChun-Jie Chen #power-domain-cells = <1>; 497994a71a3SChun-Jie Chen 498994a71a3SChun-Jie Chen /* power domain of the SoC */ 499994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_AUDIO { 500994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_AUDIO>; 501994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 502994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO_26M_B>, 503994a71a3SChun-Jie Chen <&infracfg CLK_INFRA_AUDIO>; 504994a71a3SChun-Jie Chen clock-names = "audio", "audio1", "audio2"; 505994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 506994a71a3SChun-Jie Chen #power-domain-cells = <0>; 507994a71a3SChun-Jie Chen }; 508994a71a3SChun-Jie Chen 509994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CONN { 510994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CONN>; 511994a71a3SChun-Jie Chen clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 512994a71a3SChun-Jie Chen clock-names = "conn"; 513994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 514994a71a3SChun-Jie Chen #power-domain-cells = <0>; 515994a71a3SChun-Jie Chen }; 516994a71a3SChun-Jie Chen 5176fe90cc5SNícolas F. R. A. Prado mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { 518994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG0>; 51961348fe9SAngeloGioacchino Del Regno clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, 52061348fe9SAngeloGioacchino Del Regno <&topckgen CLK_TOP_MFG_REF_SEL>; 52161348fe9SAngeloGioacchino Del Regno clock-names = "mfg", "alt"; 522994a71a3SChun-Jie Chen #address-cells = <1>; 523994a71a3SChun-Jie Chen #size-cells = <0>; 524994a71a3SChun-Jie Chen #power-domain-cells = <1>; 525994a71a3SChun-Jie Chen 5263daabcb2SAngeloGioacchino Del Regno mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { 527994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG1>; 528994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 529994a71a3SChun-Jie Chen #address-cells = <1>; 530994a71a3SChun-Jie Chen #size-cells = <0>; 531994a71a3SChun-Jie Chen #power-domain-cells = <1>; 532994a71a3SChun-Jie Chen 533994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG2 { 534994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG2>; 535994a71a3SChun-Jie Chen #power-domain-cells = <0>; 536994a71a3SChun-Jie Chen }; 537994a71a3SChun-Jie Chen 538994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG3 { 539994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG3>; 540994a71a3SChun-Jie Chen #power-domain-cells = <0>; 541994a71a3SChun-Jie Chen }; 542994a71a3SChun-Jie Chen 543994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG4 { 544994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG4>; 545994a71a3SChun-Jie Chen #power-domain-cells = <0>; 546994a71a3SChun-Jie Chen }; 547994a71a3SChun-Jie Chen 548994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG5 { 549994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG5>; 550994a71a3SChun-Jie Chen #power-domain-cells = <0>; 551994a71a3SChun-Jie Chen }; 552994a71a3SChun-Jie Chen 553994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MFG6 { 554994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MFG6>; 555994a71a3SChun-Jie Chen #power-domain-cells = <0>; 556994a71a3SChun-Jie Chen }; 557994a71a3SChun-Jie Chen }; 558994a71a3SChun-Jie Chen }; 559994a71a3SChun-Jie Chen 560994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_DISP { 561994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_DISP>; 562994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_DISP_SEL>, 563994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_INFRA>, 564994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_COMMON>, 565994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_GALS>, 566994a71a3SChun-Jie Chen <&mmsys CLK_MM_SMI_IOMMU>; 567994a71a3SChun-Jie Chen clock-names = "disp", "disp-0", "disp-1", "disp-2", 568994a71a3SChun-Jie Chen "disp-3"; 569994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 570994a71a3SChun-Jie Chen #address-cells = <1>; 571994a71a3SChun-Jie Chen #size-cells = <0>; 572994a71a3SChun-Jie Chen #power-domain-cells = <1>; 573994a71a3SChun-Jie Chen 574994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_IPE { 575994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_IPE>; 576994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IPE_SEL>, 577994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB19>, 578994a71a3SChun-Jie Chen <&ipesys CLK_IPE_LARB20>, 579994a71a3SChun-Jie Chen <&ipesys CLK_IPE_SMI_SUBCOM>, 580994a71a3SChun-Jie Chen <&ipesys CLK_IPE_GALS>; 581994a71a3SChun-Jie Chen clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 582994a71a3SChun-Jie Chen "ipe-3"; 583994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 584994a71a3SChun-Jie Chen #power-domain-cells = <0>; 585994a71a3SChun-Jie Chen }; 586994a71a3SChun-Jie Chen 587994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP { 588994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP>; 589994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG1_SEL>, 590994a71a3SChun-Jie Chen <&imgsys CLK_IMG_LARB9>, 591994a71a3SChun-Jie Chen <&imgsys CLK_IMG_GALS>; 592994a71a3SChun-Jie Chen clock-names = "isp", "isp-0", "isp-1"; 593994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 594994a71a3SChun-Jie Chen #power-domain-cells = <0>; 595994a71a3SChun-Jie Chen }; 596994a71a3SChun-Jie Chen 597994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_ISP2 { 598994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_ISP2>; 599994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_IMG2_SEL>, 600994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_LARB11>, 601994a71a3SChun-Jie Chen <&imgsys2 CLK_IMG2_GALS>; 602994a71a3SChun-Jie Chen clock-names = "isp2", "isp2-0", "isp2-1"; 603994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 604994a71a3SChun-Jie Chen #power-domain-cells = <0>; 605994a71a3SChun-Jie Chen }; 606994a71a3SChun-Jie Chen 607994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_MDP { 608994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_MDP>; 609994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_MDP_SEL>, 610994a71a3SChun-Jie Chen <&mdpsys CLK_MDP_SMI0>; 611994a71a3SChun-Jie Chen clock-names = "mdp", "mdp-0"; 612994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 613994a71a3SChun-Jie Chen #power-domain-cells = <0>; 614994a71a3SChun-Jie Chen }; 615994a71a3SChun-Jie Chen 616994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VENC { 617994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VENC>; 618994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VENC_SEL>, 619994a71a3SChun-Jie Chen <&vencsys CLK_VENC_SET1_VENC>; 620994a71a3SChun-Jie Chen clock-names = "venc", "venc-0"; 621994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 622994a71a3SChun-Jie Chen #power-domain-cells = <0>; 623994a71a3SChun-Jie Chen }; 624994a71a3SChun-Jie Chen 625994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC { 626994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC>; 627994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_VDEC_SEL>, 628994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 629994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LAT>, 630994a71a3SChun-Jie Chen <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 631994a71a3SChun-Jie Chen clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 632994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 633994a71a3SChun-Jie Chen #address-cells = <1>; 634994a71a3SChun-Jie Chen #size-cells = <0>; 635994a71a3SChun-Jie Chen #power-domain-cells = <1>; 636994a71a3SChun-Jie Chen 637994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_VDEC2 { 638994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_VDEC2>; 639994a71a3SChun-Jie Chen clocks = <&vdecsys CLK_VDEC_VDEC>, 640994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LAT>, 641994a71a3SChun-Jie Chen <&vdecsys CLK_VDEC_LARB1>; 642994a71a3SChun-Jie Chen clock-names = "vdec2-0", "vdec2-1", 643994a71a3SChun-Jie Chen "vdec2-2"; 644994a71a3SChun-Jie Chen #power-domain-cells = <0>; 645994a71a3SChun-Jie Chen }; 646994a71a3SChun-Jie Chen }; 647994a71a3SChun-Jie Chen 648994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM { 649994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM>; 650994a71a3SChun-Jie Chen clocks = <&topckgen CLK_TOP_CAM_SEL>, 651994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB13>, 652994a71a3SChun-Jie Chen <&camsys CLK_CAM_LARB14>, 653994a71a3SChun-Jie Chen <&camsys CLK_CAM_CCU_GALS>, 654994a71a3SChun-Jie Chen <&camsys CLK_CAM_CAM2MM_GALS>; 655994a71a3SChun-Jie Chen clock-names = "cam", "cam-0", "cam-1", "cam-2", 656994a71a3SChun-Jie Chen "cam-3"; 657994a71a3SChun-Jie Chen mediatek,infracfg = <&infracfg>; 658994a71a3SChun-Jie Chen #address-cells = <1>; 659994a71a3SChun-Jie Chen #size-cells = <0>; 660994a71a3SChun-Jie Chen #power-domain-cells = <1>; 661994a71a3SChun-Jie Chen 662994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 663994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 664994a71a3SChun-Jie Chen clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 665994a71a3SChun-Jie Chen clock-names = "cam_rawa-0"; 666994a71a3SChun-Jie Chen #power-domain-cells = <0>; 667994a71a3SChun-Jie Chen }; 668994a71a3SChun-Jie Chen 669994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 670994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 671994a71a3SChun-Jie Chen clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 672994a71a3SChun-Jie Chen clock-names = "cam_rawb-0"; 673994a71a3SChun-Jie Chen #power-domain-cells = <0>; 674994a71a3SChun-Jie Chen }; 675994a71a3SChun-Jie Chen 676994a71a3SChun-Jie Chen power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 677994a71a3SChun-Jie Chen reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 678994a71a3SChun-Jie Chen clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 679994a71a3SChun-Jie Chen clock-names = "cam_rawc-0"; 680994a71a3SChun-Jie Chen #power-domain-cells = <0>; 681994a71a3SChun-Jie Chen }; 682994a71a3SChun-Jie Chen }; 683994a71a3SChun-Jie Chen }; 684994a71a3SChun-Jie Chen }; 685994a71a3SChun-Jie Chen }; 686994a71a3SChun-Jie Chen 687d1986fbdSAllen-KH Cheng watchdog: watchdog@10007000 { 688d1986fbdSAllen-KH Cheng compatible = "mediatek,mt8192-wdt"; 689d1986fbdSAllen-KH Cheng reg = <0 0x10007000 0 0x100>; 690d1986fbdSAllen-KH Cheng #reset-cells = <1>; 691d1986fbdSAllen-KH Cheng }; 692d1986fbdSAllen-KH Cheng 6935d2b897bSChun-Jie Chen apmixedsys: syscon@1000c000 { 6945d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-apmixedsys", "syscon"; 6955d2b897bSChun-Jie Chen reg = <0 0x1000c000 0 0x1000>; 6965d2b897bSChun-Jie Chen #clock-cells = <1>; 6975d2b897bSChun-Jie Chen }; 6985d2b897bSChun-Jie Chen 69948489980SSeiya Wang systimer: timer@10017000 { 70048489980SSeiya Wang compatible = "mediatek,mt8192-timer", 70148489980SSeiya Wang "mediatek,mt6765-timer"; 70248489980SSeiya Wang reg = <0 0x10017000 0 0x1000>; 70348489980SSeiya Wang interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 704f19f68e5SChen-Yu Tsai clocks = <&clk13m>; 70548489980SSeiya Wang }; 70648489980SSeiya Wang 707261691b4SAllen-KH Cheng pwrap: pwrap@10026000 { 708261691b4SAllen-KH Cheng compatible = "mediatek,mt6873-pwrap"; 709261691b4SAllen-KH Cheng reg = <0 0x10026000 0 0x1000>; 710261691b4SAllen-KH Cheng reg-names = "pwrap"; 711261691b4SAllen-KH Cheng interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 712261691b4SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 713261691b4SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>; 714261691b4SAllen-KH Cheng clock-names = "spi", "wrap"; 715261691b4SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 716261691b4SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 717261691b4SAllen-KH Cheng }; 718261691b4SAllen-KH Cheng 719a8bbcf70SAllen-KH Cheng spmi: spmi@10027000 { 720a8bbcf70SAllen-KH Cheng compatible = "mediatek,mt6873-spmi"; 721a8bbcf70SAllen-KH Cheng reg = <0 0x10027000 0 0x000e00>, 722a8bbcf70SAllen-KH Cheng <0 0x10029000 0 0x000100>; 723a8bbcf70SAllen-KH Cheng reg-names = "pmif", "spmimst"; 724a8bbcf70SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PMIC_AP>, 725a8bbcf70SAllen-KH Cheng <&infracfg CLK_INFRA_PMIC_TMR>, 726a8bbcf70SAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST_SEL>; 727a8bbcf70SAllen-KH Cheng clock-names = "pmif_sys_ck", 728a8bbcf70SAllen-KH Cheng "pmif_tmr_ck", 729a8bbcf70SAllen-KH Cheng "spmimst_clk_mux"; 730a8bbcf70SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 731a8bbcf70SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 732a8bbcf70SAllen-KH Cheng }; 733a8bbcf70SAllen-KH Cheng 734b4b75bacSAllen-KH Cheng gce: mailbox@10228000 { 735b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-gce"; 736b4b75bacSAllen-KH Cheng reg = <0 0x10228000 0 0x4000>; 737b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 738b4b75bacSAllen-KH Cheng #mbox-cells = <2>; 739b4b75bacSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_GCE>; 740b4b75bacSAllen-KH Cheng clock-names = "gce"; 741b4b75bacSAllen-KH Cheng }; 742b4b75bacSAllen-KH Cheng 7435d2b897bSChun-Jie Chen scp_adsp: clock-controller@10720000 { 7445d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-scp_adsp"; 7455d2b897bSChun-Jie Chen reg = <0 0x10720000 0 0x1000>; 7465d2b897bSChun-Jie Chen #clock-cells = <1>; 747089cd717SChen-Yu Tsai /* power domain dependency not upstreamed */ 748089cd717SChen-Yu Tsai status = "fail"; 7495d2b897bSChun-Jie Chen }; 7505d2b897bSChun-Jie Chen 75148489980SSeiya Wang uart0: serial@11002000 { 75248489980SSeiya Wang compatible = "mediatek,mt8192-uart", 75348489980SSeiya Wang "mediatek,mt6577-uart"; 75448489980SSeiya Wang reg = <0 0x11002000 0 0x1000>; 75548489980SSeiya Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 75673ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 75748489980SSeiya Wang clock-names = "baud", "bus"; 75848489980SSeiya Wang status = "disabled"; 75948489980SSeiya Wang }; 76048489980SSeiya Wang 76148489980SSeiya Wang uart1: serial@11003000 { 76248489980SSeiya Wang compatible = "mediatek,mt8192-uart", 76348489980SSeiya Wang "mediatek,mt6577-uart"; 76448489980SSeiya Wang reg = <0 0x11003000 0 0x1000>; 76548489980SSeiya Wang interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 76673ba8502SAllen-KH Cheng clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 76748489980SSeiya Wang clock-names = "baud", "bus"; 76848489980SSeiya Wang status = "disabled"; 76948489980SSeiya Wang }; 77048489980SSeiya Wang 7715d2b897bSChun-Jie Chen imp_iic_wrap_c: clock-controller@11007000 { 7725d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_c"; 7735d2b897bSChun-Jie Chen reg = <0 0x11007000 0 0x1000>; 7745d2b897bSChun-Jie Chen #clock-cells = <1>; 7755d2b897bSChun-Jie Chen }; 7765d2b897bSChun-Jie Chen 77748489980SSeiya Wang spi0: spi@1100a000 { 77848489980SSeiya Wang compatible = "mediatek,mt8192-spi", 77948489980SSeiya Wang "mediatek,mt6765-spi"; 78048489980SSeiya Wang #address-cells = <1>; 78148489980SSeiya Wang #size-cells = <0>; 78248489980SSeiya Wang reg = <0 0x1100a000 0 0x1000>; 78348489980SSeiya Wang interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 7847f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 7857f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 7867f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI0>; 78748489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 78848489980SSeiya Wang status = "disabled"; 78948489980SSeiya Wang }; 79048489980SSeiya Wang 79118222e05SAllen-KH Cheng pwm0: pwm@1100e000 { 79218222e05SAllen-KH Cheng compatible = "mediatek,mt8183-disp-pwm"; 79318222e05SAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 79418222e05SAllen-KH Cheng interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 79518222e05SAllen-KH Cheng #pwm-cells = <2>; 79618222e05SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 79718222e05SAllen-KH Cheng <&infracfg CLK_INFRA_DISP_PWM>; 79818222e05SAllen-KH Cheng clock-names = "main", "mm"; 79918222e05SAllen-KH Cheng status = "disabled"; 80018222e05SAllen-KH Cheng }; 80118222e05SAllen-KH Cheng 80248489980SSeiya Wang spi1: spi@11010000 { 80348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 80448489980SSeiya Wang "mediatek,mt6765-spi"; 80548489980SSeiya Wang #address-cells = <1>; 80648489980SSeiya Wang #size-cells = <0>; 80748489980SSeiya Wang reg = <0 0x11010000 0 0x1000>; 80848489980SSeiya Wang interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 8097f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8107f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8117f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI1>; 81248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 81348489980SSeiya Wang status = "disabled"; 81448489980SSeiya Wang }; 81548489980SSeiya Wang 81648489980SSeiya Wang spi2: spi@11012000 { 81748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 81848489980SSeiya Wang "mediatek,mt6765-spi"; 81948489980SSeiya Wang #address-cells = <1>; 82048489980SSeiya Wang #size-cells = <0>; 82148489980SSeiya Wang reg = <0 0x11012000 0 0x1000>; 82248489980SSeiya Wang interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 8237f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8247f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8257f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI2>; 82648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 82748489980SSeiya Wang status = "disabled"; 82848489980SSeiya Wang }; 82948489980SSeiya Wang 83048489980SSeiya Wang spi3: spi@11013000 { 83148489980SSeiya Wang compatible = "mediatek,mt8192-spi", 83248489980SSeiya Wang "mediatek,mt6765-spi"; 83348489980SSeiya Wang #address-cells = <1>; 83448489980SSeiya Wang #size-cells = <0>; 83548489980SSeiya Wang reg = <0 0x11013000 0 0x1000>; 83648489980SSeiya Wang interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 8377f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8387f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8397f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI3>; 84048489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 84148489980SSeiya Wang status = "disabled"; 84248489980SSeiya Wang }; 84348489980SSeiya Wang 84448489980SSeiya Wang spi4: spi@11018000 { 84548489980SSeiya Wang compatible = "mediatek,mt8192-spi", 84648489980SSeiya Wang "mediatek,mt6765-spi"; 84748489980SSeiya Wang #address-cells = <1>; 84848489980SSeiya Wang #size-cells = <0>; 84948489980SSeiya Wang reg = <0 0x11018000 0 0x1000>; 85048489980SSeiya Wang interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 8517f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8527f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8537f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI4>; 85448489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 85548489980SSeiya Wang status = "disabled"; 85648489980SSeiya Wang }; 85748489980SSeiya Wang 85848489980SSeiya Wang spi5: spi@11019000 { 85948489980SSeiya Wang compatible = "mediatek,mt8192-spi", 86048489980SSeiya Wang "mediatek,mt6765-spi"; 86148489980SSeiya Wang #address-cells = <1>; 86248489980SSeiya Wang #size-cells = <0>; 86348489980SSeiya Wang reg = <0 0x11019000 0 0x1000>; 86448489980SSeiya Wang interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 8657f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8667f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8677f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI5>; 86848489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 86948489980SSeiya Wang status = "disabled"; 87048489980SSeiya Wang }; 87148489980SSeiya Wang 87248489980SSeiya Wang spi6: spi@1101d000 { 87348489980SSeiya Wang compatible = "mediatek,mt8192-spi", 87448489980SSeiya Wang "mediatek,mt6765-spi"; 87548489980SSeiya Wang #address-cells = <1>; 87648489980SSeiya Wang #size-cells = <0>; 87748489980SSeiya Wang reg = <0 0x1101d000 0 0x1000>; 87848489980SSeiya Wang interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 8797f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8807f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8817f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI6>; 88248489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 88348489980SSeiya Wang status = "disabled"; 88448489980SSeiya Wang }; 88548489980SSeiya Wang 88648489980SSeiya Wang spi7: spi@1101e000 { 88748489980SSeiya Wang compatible = "mediatek,mt8192-spi", 88848489980SSeiya Wang "mediatek,mt6765-spi"; 88948489980SSeiya Wang #address-cells = <1>; 89048489980SSeiya Wang #size-cells = <0>; 89148489980SSeiya Wang reg = <0 0x1101e000 0 0x1000>; 89248489980SSeiya Wang interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 8937f0c5b39SAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 8947f0c5b39SAllen-KH Cheng <&topckgen CLK_TOP_SPI_SEL>, 8957f0c5b39SAllen-KH Cheng <&infracfg CLK_INFRA_SPI7>; 89648489980SSeiya Wang clock-names = "parent-clk", "sel-clk", "spi-clk"; 89748489980SSeiya Wang status = "disabled"; 89848489980SSeiya Wang }; 89948489980SSeiya Wang 900c63556ecSAllen-KH Cheng scp: scp@10500000 { 901c63556ecSAllen-KH Cheng compatible = "mediatek,mt8192-scp"; 902c63556ecSAllen-KH Cheng reg = <0 0x10500000 0 0x100000>, 903c7510476SNícolas F. R. A. Prado <0 0x10720000 0 0xe0000>, 904c7510476SNícolas F. R. A. Prado <0 0x10700000 0 0x8000>; 905c7510476SNícolas F. R. A. Prado reg-names = "sram", "cfg", "l1tcm"; 906c63556ecSAllen-KH Cheng interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 907c63556ecSAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SCPSYS>; 908c63556ecSAllen-KH Cheng clock-names = "main"; 909c63556ecSAllen-KH Cheng status = "disabled"; 910c63556ecSAllen-KH Cheng }; 911c63556ecSAllen-KH Cheng 912e5aac225SAllen-KH Cheng xhci: usb@11200000 { 913e5aac225SAllen-KH Cheng compatible = "mediatek,mt8192-xhci", 914e5aac225SAllen-KH Cheng "mediatek,mtk-xhci"; 915e5aac225SAllen-KH Cheng reg = <0 0x11200000 0 0x1000>, 916e5aac225SAllen-KH Cheng <0 0x11203e00 0 0x0100>; 917e5aac225SAllen-KH Cheng reg-names = "mac", "ippc"; 918e5aac225SAllen-KH Cheng interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 919e5aac225SAllen-KH Cheng interrupt-names = "host"; 920e5aac225SAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>, 921e5aac225SAllen-KH Cheng <&u3port0 PHY_TYPE_USB3>; 922e5aac225SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 923e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 924e5aac225SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 925e5aac225SAllen-KH Cheng <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 926e5aac225SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_SSUSB>, 9276210fc2eSNícolas F. R. A. Prado <&apmixedsys CLK_APMIXED_USBPLL>, 9286210fc2eSNícolas F. R. A. Prado <&clk26m>, 9296210fc2eSNícolas F. R. A. Prado <&clk26m>, 9306210fc2eSNícolas F. R. A. Prado <&infracfg CLK_INFRA_SSUSB_XHCI>; 9316210fc2eSNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 9326210fc2eSNícolas F. R. A. Prado "xhci_ck"; 933e5aac225SAllen-KH Cheng wakeup-source; 934e5aac225SAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 102>; 935e5aac225SAllen-KH Cheng status = "disabled"; 936e5aac225SAllen-KH Cheng }; 937e5aac225SAllen-KH Cheng 9381afd9b62SAllen-KH Cheng audsys: syscon@11210000 { 9391afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audsys", "syscon"; 9401afd9b62SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 9411afd9b62SAllen-KH Cheng #clock-cells = <1>; 9421afd9b62SAllen-KH Cheng 9431afd9b62SAllen-KH Cheng afe: mt8192-afe-pcm { 9441afd9b62SAllen-KH Cheng compatible = "mediatek,mt8192-audio"; 9451afd9b62SAllen-KH Cheng interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 9461afd9b62SAllen-KH Cheng resets = <&watchdog 17>; 9471afd9b62SAllen-KH Cheng reset-names = "audiosys"; 9481afd9b62SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 9491afd9b62SAllen-KH Cheng mediatek,infracfg = <&infracfg>; 9501afd9b62SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 9511afd9b62SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 9521afd9b62SAllen-KH Cheng clocks = <&audsys CLK_AUD_AFE>, 9531afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC>, 9541afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_PREDIS>, 9551afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC>, 9561afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC>, 9571afd9b62SAllen-KH Cheng <&audsys CLK_AUD_22M>, 9581afd9b62SAllen-KH Cheng <&audsys CLK_AUD_24M>, 9591afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL_TUNER>, 9601afd9b62SAllen-KH Cheng <&audsys CLK_AUD_APLL2_TUNER>, 9611afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TDM>, 9621afd9b62SAllen-KH Cheng <&audsys CLK_AUD_TML>, 9631afd9b62SAllen-KH Cheng <&audsys CLK_AUD_NLE>, 9641afd9b62SAllen-KH Cheng <&audsys CLK_AUD_DAC_HIRES>, 9651afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES>, 9661afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADC_HIRES_TML>, 9671afd9b62SAllen-KH Cheng <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 9681afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC>, 9691afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_PREDIS>, 9701afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_TML>, 9711afd9b62SAllen-KH Cheng <&audsys CLK_AUD_3RD_DAC_HIRES>, 9721afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO>, 9731afd9b62SAllen-KH Cheng <&infracfg CLK_INFRA_AUDIO_26M_B>, 9741afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_SEL>, 9751afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 9761afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4_D4>, 9771afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1_SEL>, 9781afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1>, 9791afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2_SEL>, 9801afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2>, 9811afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 9821afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D4>, 9831afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 9841afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D4>, 9851afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 9861afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 9871afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 9881afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 9891afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 9901afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 9911afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 9921afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 9931afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 9941afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 9951afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV0>, 9961afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV1>, 9971afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV2>, 9981afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV3>, 9991afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV4>, 10001afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIVB>, 10011afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV5>, 10021afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV6>, 10031afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV7>, 10041afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV8>, 10051afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_DIV9>, 10061afd9b62SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H_SEL>, 10071afd9b62SAllen-KH Cheng <&clk26m>; 10081afd9b62SAllen-KH Cheng clock-names = "aud_afe_clk", 10091afd9b62SAllen-KH Cheng "aud_dac_clk", 10101afd9b62SAllen-KH Cheng "aud_dac_predis_clk", 10111afd9b62SAllen-KH Cheng "aud_adc_clk", 10121afd9b62SAllen-KH Cheng "aud_adda6_adc_clk", 10131afd9b62SAllen-KH Cheng "aud_apll22m_clk", 10141afd9b62SAllen-KH Cheng "aud_apll24m_clk", 10151afd9b62SAllen-KH Cheng "aud_apll1_tuner_clk", 10161afd9b62SAllen-KH Cheng "aud_apll2_tuner_clk", 10171afd9b62SAllen-KH Cheng "aud_tdm_clk", 10181afd9b62SAllen-KH Cheng "aud_tml_clk", 10191afd9b62SAllen-KH Cheng "aud_nle", 10201afd9b62SAllen-KH Cheng "aud_dac_hires_clk", 10211afd9b62SAllen-KH Cheng "aud_adc_hires_clk", 10221afd9b62SAllen-KH Cheng "aud_adc_hires_tml", 10231afd9b62SAllen-KH Cheng "aud_adda6_adc_hires_clk", 10241afd9b62SAllen-KH Cheng "aud_3rd_dac_clk", 10251afd9b62SAllen-KH Cheng "aud_3rd_dac_predis_clk", 10261afd9b62SAllen-KH Cheng "aud_3rd_dac_tml", 10271afd9b62SAllen-KH Cheng "aud_3rd_dac_hires_clk", 10281afd9b62SAllen-KH Cheng "aud_infra_clk", 10291afd9b62SAllen-KH Cheng "aud_infra_26m_clk", 10301afd9b62SAllen-KH Cheng "top_mux_audio", 10311afd9b62SAllen-KH Cheng "top_mux_audio_int", 10321afd9b62SAllen-KH Cheng "top_mainpll_d4_d4", 10331afd9b62SAllen-KH Cheng "top_mux_aud_1", 10341afd9b62SAllen-KH Cheng "top_apll1_ck", 10351afd9b62SAllen-KH Cheng "top_mux_aud_2", 10361afd9b62SAllen-KH Cheng "top_apll2_ck", 10371afd9b62SAllen-KH Cheng "top_mux_aud_eng1", 10381afd9b62SAllen-KH Cheng "top_apll1_d4", 10391afd9b62SAllen-KH Cheng "top_mux_aud_eng2", 10401afd9b62SAllen-KH Cheng "top_apll2_d4", 10411afd9b62SAllen-KH Cheng "top_i2s0_m_sel", 10421afd9b62SAllen-KH Cheng "top_i2s1_m_sel", 10431afd9b62SAllen-KH Cheng "top_i2s2_m_sel", 10441afd9b62SAllen-KH Cheng "top_i2s3_m_sel", 10451afd9b62SAllen-KH Cheng "top_i2s4_m_sel", 10461afd9b62SAllen-KH Cheng "top_i2s5_m_sel", 10471afd9b62SAllen-KH Cheng "top_i2s6_m_sel", 10481afd9b62SAllen-KH Cheng "top_i2s7_m_sel", 10491afd9b62SAllen-KH Cheng "top_i2s8_m_sel", 10501afd9b62SAllen-KH Cheng "top_i2s9_m_sel", 10511afd9b62SAllen-KH Cheng "top_apll12_div0", 10521afd9b62SAllen-KH Cheng "top_apll12_div1", 10531afd9b62SAllen-KH Cheng "top_apll12_div2", 10541afd9b62SAllen-KH Cheng "top_apll12_div3", 10551afd9b62SAllen-KH Cheng "top_apll12_div4", 10561afd9b62SAllen-KH Cheng "top_apll12_divb", 10571afd9b62SAllen-KH Cheng "top_apll12_div5", 10581afd9b62SAllen-KH Cheng "top_apll12_div6", 10591afd9b62SAllen-KH Cheng "top_apll12_div7", 10601afd9b62SAllen-KH Cheng "top_apll12_div8", 10611afd9b62SAllen-KH Cheng "top_apll12_div9", 10621afd9b62SAllen-KH Cheng "top_mux_audio_h", 10631afd9b62SAllen-KH Cheng "top_clk26m_clk"; 10641afd9b62SAllen-KH Cheng }; 10651afd9b62SAllen-KH Cheng }; 10661afd9b62SAllen-KH Cheng 1067e530d080SAllen-KH Cheng pcie: pcie@11230000 { 1068e530d080SAllen-KH Cheng compatible = "mediatek,mt8192-pcie"; 1069e530d080SAllen-KH Cheng device_type = "pci"; 1070e530d080SAllen-KH Cheng reg = <0 0x11230000 0 0x2000>; 1071e530d080SAllen-KH Cheng reg-names = "pcie-mac"; 1072e530d080SAllen-KH Cheng #address-cells = <3>; 1073e530d080SAllen-KH Cheng #size-cells = <2>; 1074e530d080SAllen-KH Cheng clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 1075e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_26M>, 1076e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_96M>, 1077e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TL_32K>, 1078e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_PERI_26M>, 1079e530d080SAllen-KH Cheng <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 1080e530d080SAllen-KH Cheng clock-names = "pl_250m", "tl_26m", "tl_96m", 1081e530d080SAllen-KH Cheng "tl_32k", "peri_26m", "top_133m"; 1082e530d080SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 1083e530d080SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 1084e530d080SAllen-KH Cheng interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 1085e530d080SAllen-KH Cheng bus-range = <0x00 0xff>; 1086e530d080SAllen-KH Cheng ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 1087e530d080SAllen-KH Cheng <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 1088e530d080SAllen-KH Cheng #interrupt-cells = <1>; 1089e530d080SAllen-KH Cheng interrupt-map-mask = <0 0 0 7>; 1090e530d080SAllen-KH Cheng interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1091e530d080SAllen-KH Cheng <0 0 0 2 &pcie_intc0 1>, 1092e530d080SAllen-KH Cheng <0 0 0 3 &pcie_intc0 2>, 1093e530d080SAllen-KH Cheng <0 0 0 4 &pcie_intc0 3>; 1094e530d080SAllen-KH Cheng 1095e530d080SAllen-KH Cheng pcie_intc0: interrupt-controller { 1096e530d080SAllen-KH Cheng interrupt-controller; 1097e530d080SAllen-KH Cheng #address-cells = <0>; 1098e530d080SAllen-KH Cheng #interrupt-cells = <1>; 1099e530d080SAllen-KH Cheng }; 1100e530d080SAllen-KH Cheng }; 1101e530d080SAllen-KH Cheng 1102d0a197a0Sbayi cheng nor_flash: spi@11234000 { 1103d0a197a0Sbayi cheng compatible = "mediatek,mt8192-nor"; 1104d0a197a0Sbayi cheng reg = <0 0x11234000 0 0xe0>; 1105d0a197a0Sbayi cheng interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1106aa247c07SAllen-KH Cheng clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1107aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1108aa247c07SAllen-KH Cheng <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1109d0a197a0Sbayi cheng clock-names = "spi", "sf", "axi"; 1110aa247c07SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1111aa247c07SAllen-KH Cheng assigned-clock-parents = <&clk26m>; 1112d0a197a0Sbayi cheng #address-cells = <1>; 1113d0a197a0Sbayi cheng #size-cells = <0>; 111427f0eb16SAllen-KH Cheng status = "disabled"; 1115d0a197a0Sbayi cheng }; 1116d0a197a0Sbayi cheng 11174d50a433SAllen-KH Cheng efuse: efuse@11c10000 { 1118fda0541cSChunfeng Yun compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 11194d50a433SAllen-KH Cheng reg = <0 0x11c10000 0 0x1000>; 11204d50a433SAllen-KH Cheng #address-cells = <1>; 11214d50a433SAllen-KH Cheng #size-cells = <1>; 11224d50a433SAllen-KH Cheng 11234d50a433SAllen-KH Cheng lvts_e_data1: data1@1c0 { 11244d50a433SAllen-KH Cheng reg = <0x1c0 0x58>; 11254d50a433SAllen-KH Cheng }; 11264d50a433SAllen-KH Cheng 11274d50a433SAllen-KH Cheng svs_calibration: calib@580 { 11284d50a433SAllen-KH Cheng reg = <0x580 0x68>; 11294d50a433SAllen-KH Cheng }; 11304d50a433SAllen-KH Cheng }; 11314d50a433SAllen-KH Cheng 11327f1a9f47SFabien Parent i2c3: i2c@11cb0000 { 113348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 113448489980SSeiya Wang reg = <0 0x11cb0000 0 0x1000>, 113548489980SSeiya Wang <0 0x10217300 0 0x80>; 113648489980SSeiya Wang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 113722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 113822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 113948489980SSeiya Wang clock-names = "main", "dma"; 114048489980SSeiya Wang clock-div = <1>; 114148489980SSeiya Wang #address-cells = <1>; 114248489980SSeiya Wang #size-cells = <0>; 114348489980SSeiya Wang status = "disabled"; 114448489980SSeiya Wang }; 114548489980SSeiya Wang 11465d2b897bSChun-Jie Chen imp_iic_wrap_e: clock-controller@11cb1000 { 11475d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_e"; 11485d2b897bSChun-Jie Chen reg = <0 0x11cb1000 0 0x1000>; 11495d2b897bSChun-Jie Chen #clock-cells = <1>; 11505d2b897bSChun-Jie Chen }; 11515d2b897bSChun-Jie Chen 11527f1a9f47SFabien Parent i2c7: i2c@11d00000 { 115348489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 115448489980SSeiya Wang reg = <0 0x11d00000 0 0x1000>, 115548489980SSeiya Wang <0 0x10217600 0 0x180>; 115648489980SSeiya Wang interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 115722623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 115822623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 115948489980SSeiya Wang clock-names = "main", "dma"; 116048489980SSeiya Wang clock-div = <1>; 116148489980SSeiya Wang #address-cells = <1>; 116248489980SSeiya Wang #size-cells = <0>; 116348489980SSeiya Wang status = "disabled"; 116448489980SSeiya Wang }; 116548489980SSeiya Wang 11667f1a9f47SFabien Parent i2c8: i2c@11d01000 { 116748489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 116848489980SSeiya Wang reg = <0 0x11d01000 0 0x1000>, 116948489980SSeiya Wang <0 0x10217780 0 0x180>; 117048489980SSeiya Wang interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 117122623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 117222623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 117348489980SSeiya Wang clock-names = "main", "dma"; 117448489980SSeiya Wang clock-div = <1>; 117548489980SSeiya Wang #address-cells = <1>; 117648489980SSeiya Wang #size-cells = <0>; 117748489980SSeiya Wang status = "disabled"; 117848489980SSeiya Wang }; 117948489980SSeiya Wang 11807f1a9f47SFabien Parent i2c9: i2c@11d02000 { 118148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 118248489980SSeiya Wang reg = <0 0x11d02000 0 0x1000>, 118348489980SSeiya Wang <0 0x10217900 0 0x180>; 118448489980SSeiya Wang interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 118522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 118622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 118748489980SSeiya Wang clock-names = "main", "dma"; 118848489980SSeiya Wang clock-div = <1>; 118948489980SSeiya Wang #address-cells = <1>; 119048489980SSeiya Wang #size-cells = <0>; 119148489980SSeiya Wang status = "disabled"; 119248489980SSeiya Wang }; 119348489980SSeiya Wang 11945d2b897bSChun-Jie Chen imp_iic_wrap_s: clock-controller@11d03000 { 11955d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_s"; 11965d2b897bSChun-Jie Chen reg = <0 0x11d03000 0 0x1000>; 11975d2b897bSChun-Jie Chen #clock-cells = <1>; 11985d2b897bSChun-Jie Chen }; 11995d2b897bSChun-Jie Chen 12007f1a9f47SFabien Parent i2c1: i2c@11d20000 { 120148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 120248489980SSeiya Wang reg = <0 0x11d20000 0 0x1000>, 120348489980SSeiya Wang <0 0x10217100 0 0x80>; 120448489980SSeiya Wang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 120522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 120622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 120748489980SSeiya Wang clock-names = "main", "dma"; 120848489980SSeiya Wang clock-div = <1>; 120948489980SSeiya Wang #address-cells = <1>; 121048489980SSeiya Wang #size-cells = <0>; 121148489980SSeiya Wang status = "disabled"; 121248489980SSeiya Wang }; 121348489980SSeiya Wang 12147f1a9f47SFabien Parent i2c2: i2c@11d21000 { 121548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 121648489980SSeiya Wang reg = <0 0x11d21000 0 0x1000>, 121748489980SSeiya Wang <0 0x10217180 0 0x180>; 121848489980SSeiya Wang interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 121922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 122022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 122148489980SSeiya Wang clock-names = "main", "dma"; 122248489980SSeiya Wang clock-div = <1>; 122348489980SSeiya Wang #address-cells = <1>; 122448489980SSeiya Wang #size-cells = <0>; 122548489980SSeiya Wang status = "disabled"; 122648489980SSeiya Wang }; 122748489980SSeiya Wang 12287f1a9f47SFabien Parent i2c4: i2c@11d22000 { 122948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 123048489980SSeiya Wang reg = <0 0x11d22000 0 0x1000>, 123148489980SSeiya Wang <0 0x10217380 0 0x180>; 123248489980SSeiya Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 123322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 123422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 123548489980SSeiya Wang clock-names = "main", "dma"; 123648489980SSeiya Wang clock-div = <1>; 123748489980SSeiya Wang #address-cells = <1>; 123848489980SSeiya Wang #size-cells = <0>; 123948489980SSeiya Wang status = "disabled"; 124048489980SSeiya Wang }; 124148489980SSeiya Wang 12425d2b897bSChun-Jie Chen imp_iic_wrap_ws: clock-controller@11d23000 { 12435d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 12445d2b897bSChun-Jie Chen reg = <0 0x11d23000 0 0x1000>; 12455d2b897bSChun-Jie Chen #clock-cells = <1>; 12465d2b897bSChun-Jie Chen }; 12475d2b897bSChun-Jie Chen 12487f1a9f47SFabien Parent i2c5: i2c@11e00000 { 124948489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 125048489980SSeiya Wang reg = <0 0x11e00000 0 0x1000>, 125148489980SSeiya Wang <0 0x10217500 0 0x80>; 125248489980SSeiya Wang interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 125322623154SAllen-KH Cheng clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 125422623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 125548489980SSeiya Wang clock-names = "main", "dma"; 125648489980SSeiya Wang clock-div = <1>; 125748489980SSeiya Wang #address-cells = <1>; 125848489980SSeiya Wang #size-cells = <0>; 125948489980SSeiya Wang status = "disabled"; 126048489980SSeiya Wang }; 126148489980SSeiya Wang 12625d2b897bSChun-Jie Chen imp_iic_wrap_w: clock-controller@11e01000 { 12635d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_w"; 12645d2b897bSChun-Jie Chen reg = <0 0x11e01000 0 0x1000>; 12655d2b897bSChun-Jie Chen #clock-cells = <1>; 12665d2b897bSChun-Jie Chen }; 12675d2b897bSChun-Jie Chen 126840de66b8SAllen-KH Cheng u3phy0: t-phy@11e40000 { 126940de66b8SAllen-KH Cheng compatible = "mediatek,mt8192-tphy", 127040de66b8SAllen-KH Cheng "mediatek,generic-tphy-v2"; 127140de66b8SAllen-KH Cheng #address-cells = <1>; 127240de66b8SAllen-KH Cheng #size-cells = <1>; 127340de66b8SAllen-KH Cheng ranges = <0x0 0x0 0x11e40000 0x1000>; 127440de66b8SAllen-KH Cheng 127540de66b8SAllen-KH Cheng u2port0: usb-phy@0 { 127640de66b8SAllen-KH Cheng reg = <0x0 0x700>; 127740de66b8SAllen-KH Cheng clocks = <&clk26m>; 127840de66b8SAllen-KH Cheng clock-names = "ref"; 127940de66b8SAllen-KH Cheng #phy-cells = <1>; 128040de66b8SAllen-KH Cheng }; 128140de66b8SAllen-KH Cheng 128240de66b8SAllen-KH Cheng u3port0: usb-phy@700 { 128340de66b8SAllen-KH Cheng reg = <0x700 0x900>; 128440de66b8SAllen-KH Cheng clocks = <&clk26m>; 128540de66b8SAllen-KH Cheng clock-names = "ref"; 128640de66b8SAllen-KH Cheng #phy-cells = <1>; 128740de66b8SAllen-KH Cheng }; 128840de66b8SAllen-KH Cheng }; 128940de66b8SAllen-KH Cheng 129085c4ec6fSAllen-KH Cheng mipi_tx0: dsi-phy@11e50000 { 129185c4ec6fSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 129285c4ec6fSAllen-KH Cheng reg = <0 0x11e50000 0 0x1000>; 129385c4ec6fSAllen-KH Cheng clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 129485c4ec6fSAllen-KH Cheng #clock-cells = <0>; 129585c4ec6fSAllen-KH Cheng #phy-cells = <0>; 129685c4ec6fSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 129785c4ec6fSAllen-KH Cheng status = "disabled"; 129885c4ec6fSAllen-KH Cheng }; 129985c4ec6fSAllen-KH Cheng 13007f1a9f47SFabien Parent i2c0: i2c@11f00000 { 130148489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 130248489980SSeiya Wang reg = <0 0x11f00000 0 0x1000>, 130348489980SSeiya Wang <0 0x10217080 0 0x80>; 130448489980SSeiya Wang interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 130522623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 130622623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 130748489980SSeiya Wang clock-names = "main", "dma"; 130848489980SSeiya Wang clock-div = <1>; 130948489980SSeiya Wang #address-cells = <1>; 131048489980SSeiya Wang #size-cells = <0>; 131148489980SSeiya Wang status = "disabled"; 131248489980SSeiya Wang }; 131348489980SSeiya Wang 13147f1a9f47SFabien Parent i2c6: i2c@11f01000 { 131548489980SSeiya Wang compatible = "mediatek,mt8192-i2c"; 131648489980SSeiya Wang reg = <0 0x11f01000 0 0x1000>, 131748489980SSeiya Wang <0 0x10217580 0 0x80>; 131848489980SSeiya Wang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 131922623154SAllen-KH Cheng clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 132022623154SAllen-KH Cheng <&infracfg CLK_INFRA_AP_DMA>; 132148489980SSeiya Wang clock-names = "main", "dma"; 132248489980SSeiya Wang clock-div = <1>; 132348489980SSeiya Wang #address-cells = <1>; 132448489980SSeiya Wang #size-cells = <0>; 132548489980SSeiya Wang status = "disabled"; 132648489980SSeiya Wang }; 13275d2b897bSChun-Jie Chen 13285d2b897bSChun-Jie Chen imp_iic_wrap_n: clock-controller@11f02000 { 13295d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imp_iic_wrap_n"; 13305d2b897bSChun-Jie Chen reg = <0 0x11f02000 0 0x1000>; 13315d2b897bSChun-Jie Chen #clock-cells = <1>; 13325d2b897bSChun-Jie Chen }; 13335d2b897bSChun-Jie Chen 13345d2b897bSChun-Jie Chen msdc_top: clock-controller@11f10000 { 13355d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-msdc_top"; 13365d2b897bSChun-Jie Chen reg = <0 0x11f10000 0 0x1000>; 13375d2b897bSChun-Jie Chen #clock-cells = <1>; 13385d2b897bSChun-Jie Chen }; 13395d2b897bSChun-Jie Chen 1340db61337eSAllen-KH Cheng mmc0: mmc@11f60000 { 1341db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1342db61337eSAllen-KH Cheng reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1343db61337eSAllen-KH Cheng interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1344db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1345db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1346db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1347db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1348db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1349db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1350db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1351db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1352db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1353db61337eSAllen-KH Cheng status = "disabled"; 1354db61337eSAllen-KH Cheng }; 1355db61337eSAllen-KH Cheng 1356db61337eSAllen-KH Cheng mmc1: mmc@11f70000 { 1357db61337eSAllen-KH Cheng compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1358db61337eSAllen-KH Cheng reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1359db61337eSAllen-KH Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1360db61337eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1361db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1362db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1363db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_CFG>, 1364db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1365db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AXI>, 1366db61337eSAllen-KH Cheng <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1367db61337eSAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "sys_cg", 1368db61337eSAllen-KH Cheng "pclk_cg", "axi_cg", "ahb_cg"; 1369db61337eSAllen-KH Cheng status = "disabled"; 13705d2b897bSChun-Jie Chen }; 13715d2b897bSChun-Jie Chen 1372e1233345SAlyssa Rosenzweig gpu: gpu@13000000 { 1373e1233345SAlyssa Rosenzweig compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm"; 1374e1233345SAlyssa Rosenzweig reg = <0 0x13000000 0 0x4000>; 1375e1233345SAlyssa Rosenzweig interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, 1376e1233345SAlyssa Rosenzweig <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, 1377e1233345SAlyssa Rosenzweig <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1378e1233345SAlyssa Rosenzweig interrupt-names = "job", "mmu", "gpu"; 1379e1233345SAlyssa Rosenzweig 1380e1233345SAlyssa Rosenzweig clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 1381e1233345SAlyssa Rosenzweig 1382e1233345SAlyssa Rosenzweig power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>, 1383e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG3>, 1384e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG4>, 1385e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG5>, 1386e1233345SAlyssa Rosenzweig <&spm MT8192_POWER_DOMAIN_MFG6>; 1387e1233345SAlyssa Rosenzweig power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1388e1233345SAlyssa Rosenzweig 1389e1233345SAlyssa Rosenzweig operating-points-v2 = <&gpu_opp_table>; 1390e1233345SAlyssa Rosenzweig 1391e1233345SAlyssa Rosenzweig status = "disabled"; 1392e1233345SAlyssa Rosenzweig }; 1393e1233345SAlyssa Rosenzweig 13945d2b897bSChun-Jie Chen mfgcfg: clock-controller@13fbf000 { 13955d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mfgcfg"; 13965d2b897bSChun-Jie Chen reg = <0 0x13fbf000 0 0x1000>; 13975d2b897bSChun-Jie Chen #clock-cells = <1>; 13985d2b897bSChun-Jie Chen }; 13995d2b897bSChun-Jie Chen 14005d2b897bSChun-Jie Chen mmsys: syscon@14000000 { 14015d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mmsys", "syscon"; 14025d2b897bSChun-Jie Chen reg = <0 0x14000000 0 0x1000>; 14035d2b897bSChun-Jie Chen #clock-cells = <1>; 14047d355378SAllen-KH Cheng #reset-cells = <1>; 1405b4b75bacSAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1406b4b75bacSAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1407b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1408b4b75bacSAllen-KH Cheng }; 1409b4b75bacSAllen-KH Cheng 1410b4b75bacSAllen-KH Cheng mutex: mutex@14001000 { 1411b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-mutex"; 1412b4b75bacSAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 1413b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1414b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1415550ad9aaSNícolas F. R. A. Prado mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1416b4b75bacSAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1417b4b75bacSAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1418b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14195d2b897bSChun-Jie Chen }; 14205d2b897bSChun-Jie Chen 14214a65b0f1SAllen-KH Cheng smi_common: smi@14002000 { 14224a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-common"; 14234a65b0f1SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 14244a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 14254a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 14264a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 14274a65b0f1SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>; 14284a65b0f1SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 14294a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14304a65b0f1SAllen-KH Cheng }; 14314a65b0f1SAllen-KH Cheng 14324a65b0f1SAllen-KH Cheng larb0: larb@14003000 { 14334a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14344a65b0f1SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 14354a65b0f1SAllen-KH Cheng mediatek,larb-id = <0>; 14364a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14374a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 14384a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14394a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14404a65b0f1SAllen-KH Cheng }; 14414a65b0f1SAllen-KH Cheng 14424a65b0f1SAllen-KH Cheng larb1: larb@14004000 { 14434a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 14444a65b0f1SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 14454a65b0f1SAllen-KH Cheng mediatek,larb-id = <1>; 14464a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 14474a65b0f1SAllen-KH Cheng clocks = <&clk26m>, <&clk26m>; 14484a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 14494a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 14504a65b0f1SAllen-KH Cheng }; 14514a65b0f1SAllen-KH Cheng 1452b4b75bacSAllen-KH Cheng ovl0: ovl@14005000 { 1453b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl"; 1454b4b75bacSAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 1455b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1456b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 1457b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1458b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1459b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1460b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1461b4b75bacSAllen-KH Cheng }; 1462b4b75bacSAllen-KH Cheng 1463b4b75bacSAllen-KH Cheng ovl_2l0: ovl@14006000 { 1464b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1465b4b75bacSAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 1466b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1467b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1468b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1469b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1470b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1471b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1472b4b75bacSAllen-KH Cheng }; 1473b4b75bacSAllen-KH Cheng 1474b4b75bacSAllen-KH Cheng rdma0: rdma@14007000 { 1475b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1476b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1477b4b75bacSAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 1478b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1479b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1480b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1481b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <5120>; 1482b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1483b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1484b4b75bacSAllen-KH Cheng }; 1485b4b75bacSAllen-KH Cheng 1486b4b75bacSAllen-KH Cheng color0: color@14009000 { 1487b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-color", 1488b4b75bacSAllen-KH Cheng "mediatek,mt8173-disp-color"; 1489b4b75bacSAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 1490b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1491b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1492b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1493b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1494b4b75bacSAllen-KH Cheng }; 1495b4b75bacSAllen-KH Cheng 1496b4b75bacSAllen-KH Cheng ccorr0: ccorr@1400a000 { 1497b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ccorr"; 1498b4b75bacSAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 1499b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1500b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1501b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1502b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1503b4b75bacSAllen-KH Cheng }; 1504b4b75bacSAllen-KH Cheng 1505b4b75bacSAllen-KH Cheng aal0: aal@1400b000 { 1506b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-aal", 1507b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-aal"; 1508b4b75bacSAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 1509b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1510b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1511b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 1512b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1513b4b75bacSAllen-KH Cheng }; 1514b4b75bacSAllen-KH Cheng 1515b4b75bacSAllen-KH Cheng gamma0: gamma@1400c000 { 1516b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-gamma", 1517b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-gamma"; 1518b4b75bacSAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 1519b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1520b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1521b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1522b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1523b4b75bacSAllen-KH Cheng }; 1524b4b75bacSAllen-KH Cheng 1525b4b75bacSAllen-KH Cheng postmask0: postmask@1400d000 { 1526b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-postmask"; 1527b4b75bacSAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 1528b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1529b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1530b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1531b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1532b4b75bacSAllen-KH Cheng }; 1533b4b75bacSAllen-KH Cheng 1534b4b75bacSAllen-KH Cheng dither0: dither@1400e000 { 1535b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-dither", 1536b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-dither"; 1537b4b75bacSAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 1538b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1539b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1540b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1541b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1542b4b75bacSAllen-KH Cheng }; 1543b4b75bacSAllen-KH Cheng 15440708ed7cSAllen-KH Cheng dsi0: dsi@14010000 { 15450708ed7cSAllen-KH Cheng compatible = "mediatek,mt8183-dsi"; 15460708ed7cSAllen-KH Cheng reg = <0 0x14010000 0 0x1000>; 15470708ed7cSAllen-KH Cheng interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 15480708ed7cSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 15490708ed7cSAllen-KH Cheng <&mmsys CLK_MM_DSI_DSI0>, 15500708ed7cSAllen-KH Cheng <&mipi_tx0>; 15510708ed7cSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 15520708ed7cSAllen-KH Cheng phys = <&mipi_tx0>; 15530708ed7cSAllen-KH Cheng phy-names = "dphy"; 15540708ed7cSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 15550708ed7cSAllen-KH Cheng resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 15560708ed7cSAllen-KH Cheng status = "disabled"; 15570708ed7cSAllen-KH Cheng 15580708ed7cSAllen-KH Cheng port { 15590708ed7cSAllen-KH Cheng dsi_out: endpoint { }; 15600708ed7cSAllen-KH Cheng }; 15610708ed7cSAllen-KH Cheng }; 15620708ed7cSAllen-KH Cheng 1563b4b75bacSAllen-KH Cheng ovl_2l2: ovl@14014000 { 1564b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-ovl-2l"; 1565b4b75bacSAllen-KH Cheng reg = <0 0x14014000 0 0x1000>; 1566b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1567b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1568b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1569b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1570b4b75bacSAllen-KH Cheng <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1571b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1572b4b75bacSAllen-KH Cheng }; 1573b4b75bacSAllen-KH Cheng 1574b4b75bacSAllen-KH Cheng rdma4: rdma@14015000 { 1575b4b75bacSAllen-KH Cheng compatible = "mediatek,mt8192-disp-rdma", 1576b4b75bacSAllen-KH Cheng "mediatek,mt8183-disp-rdma"; 1577b4b75bacSAllen-KH Cheng reg = <0 0x14015000 0 0x1000>; 1578b4b75bacSAllen-KH Cheng interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1579b4b75bacSAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1580b4b75bacSAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1581b4b75bacSAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1582b4b75bacSAllen-KH Cheng mediatek,rdma-fifo-size = <2048>; 1583b4b75bacSAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1584b4b75bacSAllen-KH Cheng }; 1585b4b75bacSAllen-KH Cheng 1586b2edd519SAllen-KH Cheng dpi0: dpi@14016000 { 1587b2edd519SAllen-KH Cheng compatible = "mediatek,mt8192-dpi"; 1588b2edd519SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1589b2edd519SAllen-KH Cheng interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1590b2edd519SAllen-KH Cheng clocks = <&mmsys CLK_MM_DPI_DPI0>, 1591b2edd519SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI0>, 1592b2edd519SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 1593b2edd519SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 1594b2edd519SAllen-KH Cheng status = "disabled"; 1595b2edd519SAllen-KH Cheng }; 1596b2edd519SAllen-KH Cheng 15974a65b0f1SAllen-KH Cheng iommu0: m4u@1401d000 { 15984a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-m4u"; 15994a65b0f1SAllen-KH Cheng reg = <0 0x1401d000 0 0x1000>; 16004a65b0f1SAllen-KH Cheng mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 16014a65b0f1SAllen-KH Cheng <&larb4>, <&larb5>, <&larb7>, 16024a65b0f1SAllen-KH Cheng <&larb9>, <&larb11>, <&larb13>, 16034a65b0f1SAllen-KH Cheng <&larb14>, <&larb16>, <&larb17>, 16044a65b0f1SAllen-KH Cheng <&larb18>, <&larb19>, <&larb20>; 16054a65b0f1SAllen-KH Cheng interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 16064a65b0f1SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 16074a65b0f1SAllen-KH Cheng clock-names = "bclk"; 16084a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 16094a65b0f1SAllen-KH Cheng #iommu-cells = <1>; 16104a65b0f1SAllen-KH Cheng }; 16114a65b0f1SAllen-KH Cheng 16125d2b897bSChun-Jie Chen imgsys: clock-controller@15020000 { 16135d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys"; 16145d2b897bSChun-Jie Chen reg = <0 0x15020000 0 0x1000>; 16155d2b897bSChun-Jie Chen #clock-cells = <1>; 16165d2b897bSChun-Jie Chen }; 16175d2b897bSChun-Jie Chen 16184a65b0f1SAllen-KH Cheng larb9: larb@1502e000 { 16194a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16204a65b0f1SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 16214a65b0f1SAllen-KH Cheng mediatek,larb-id = <9>; 16224a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16234a65b0f1SAllen-KH Cheng clocks = <&imgsys CLK_IMG_LARB9>, 16244a65b0f1SAllen-KH Cheng <&imgsys CLK_IMG_LARB9>; 16254a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16264a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 16274a65b0f1SAllen-KH Cheng }; 16284a65b0f1SAllen-KH Cheng 16295d2b897bSChun-Jie Chen imgsys2: clock-controller@15820000 { 16305d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-imgsys2"; 16315d2b897bSChun-Jie Chen reg = <0 0x15820000 0 0x1000>; 16325d2b897bSChun-Jie Chen #clock-cells = <1>; 16335d2b897bSChun-Jie Chen }; 16345d2b897bSChun-Jie Chen 16354a65b0f1SAllen-KH Cheng larb11: larb@1582e000 { 16364a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 16374a65b0f1SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 16384a65b0f1SAllen-KH Cheng mediatek,larb-id = <11>; 16394a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 16404a65b0f1SAllen-KH Cheng clocks = <&imgsys2 CLK_IMG2_LARB11>, 16414a65b0f1SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB11>; 16424a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 16434a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 16444a65b0f1SAllen-KH Cheng }; 16454a65b0f1SAllen-KH Cheng 16461b85a425SAllen-KH Cheng vcodec_dec: video-codec@16000000 { 16471b85a425SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-dec"; 16481b85a425SAllen-KH Cheng reg = <0 0x16000000 0 0x1000>; 16491b85a425SAllen-KH Cheng mediatek,scp = <&scp>; 16501b85a425SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; 16511b85a425SAllen-KH Cheng #address-cells = <2>; 16521b85a425SAllen-KH Cheng #size-cells = <2>; 16531b85a425SAllen-KH Cheng ranges = <0 0 0 0x16000000 0 0x26000>; 16541b85a425SAllen-KH Cheng 16551b85a425SAllen-KH Cheng video-codec@10000 { 16561b85a425SAllen-KH Cheng compatible = "mediatek,mtk-vcodec-lat"; 16571b85a425SAllen-KH Cheng reg = <0x0 0x10000 0 0x800>; 16581b85a425SAllen-KH Cheng interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; 16591b85a425SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, 16601b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, 16611b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, 16621b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, 16631b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, 16641b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, 16651b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, 16661b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; 16671b85a425SAllen-KH Cheng clocks = <&topckgen CLK_TOP_VDEC_SEL>, 16681b85a425SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 16691b85a425SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LAT>, 16701b85a425SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 16711b85a425SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4>; 16721b85a425SAllen-KH Cheng clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 16731b85a425SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 16741b85a425SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 16751b85a425SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 16761b85a425SAllen-KH Cheng }; 16771b85a425SAllen-KH Cheng 16781b85a425SAllen-KH Cheng video-codec@25000 { 16791b85a425SAllen-KH Cheng compatible = "mediatek,mtk-vcodec-core"; 16801b85a425SAllen-KH Cheng reg = <0 0x25000 0 0x1000>; 16811b85a425SAllen-KH Cheng interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; 16821b85a425SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, 16831b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, 16841b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, 16851b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, 16861b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, 16871b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, 16881b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, 16891b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, 16901b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, 16911b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, 16921b85a425SAllen-KH Cheng <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; 16931b85a425SAllen-KH Cheng clocks = <&topckgen CLK_TOP_VDEC_SEL>, 16941b85a425SAllen-KH Cheng <&vdecsys CLK_VDEC_VDEC>, 16951b85a425SAllen-KH Cheng <&vdecsys CLK_VDEC_LAT>, 16961b85a425SAllen-KH Cheng <&vdecsys CLK_VDEC_LARB1>, 16971b85a425SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D4>; 16981b85a425SAllen-KH Cheng clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 16991b85a425SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 17001b85a425SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 17011b85a425SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 17021b85a425SAllen-KH Cheng }; 17031b85a425SAllen-KH Cheng }; 17041b85a425SAllen-KH Cheng 17054a65b0f1SAllen-KH Cheng larb5: larb@1600d000 { 17064a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17074a65b0f1SAllen-KH Cheng reg = <0 0x1600d000 0 0x1000>; 17084a65b0f1SAllen-KH Cheng mediatek,larb-id = <5>; 17094a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17104a65b0f1SAllen-KH Cheng clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 17114a65b0f1SAllen-KH Cheng <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 17124a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17134a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 17144a65b0f1SAllen-KH Cheng }; 17154a65b0f1SAllen-KH Cheng 17165d2b897bSChun-Jie Chen vdecsys_soc: clock-controller@1600f000 { 17175d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys_soc"; 17185d2b897bSChun-Jie Chen reg = <0 0x1600f000 0 0x1000>; 17195d2b897bSChun-Jie Chen #clock-cells = <1>; 17205d2b897bSChun-Jie Chen }; 17215d2b897bSChun-Jie Chen 17224a65b0f1SAllen-KH Cheng larb4: larb@1602e000 { 17234a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17244a65b0f1SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 17254a65b0f1SAllen-KH Cheng mediatek,larb-id = <4>; 17264a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17274a65b0f1SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 17284a65b0f1SAllen-KH Cheng <&vdecsys CLK_VDEC_SOC_LARB1>; 17294a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17304a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 17314a65b0f1SAllen-KH Cheng }; 17324a65b0f1SAllen-KH Cheng 17335d2b897bSChun-Jie Chen vdecsys: clock-controller@1602f000 { 17345d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vdecsys"; 17355d2b897bSChun-Jie Chen reg = <0 0x1602f000 0 0x1000>; 17365d2b897bSChun-Jie Chen #clock-cells = <1>; 17375d2b897bSChun-Jie Chen }; 17385d2b897bSChun-Jie Chen 17395d2b897bSChun-Jie Chen vencsys: clock-controller@17000000 { 17405d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-vencsys"; 17415d2b897bSChun-Jie Chen reg = <0 0x17000000 0 0x1000>; 17425d2b897bSChun-Jie Chen #clock-cells = <1>; 17435d2b897bSChun-Jie Chen }; 17445d2b897bSChun-Jie Chen 17454a65b0f1SAllen-KH Cheng larb7: larb@17010000 { 17464a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17474a65b0f1SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 17484a65b0f1SAllen-KH Cheng mediatek,larb-id = <7>; 17494a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17504a65b0f1SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET0_LARB>, 17514a65b0f1SAllen-KH Cheng <&vencsys CLK_VENC_SET1_VENC>; 17524a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17534a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 17544a65b0f1SAllen-KH Cheng }; 17554a65b0f1SAllen-KH Cheng 1756aa8f3711SAllen-KH Cheng vcodec_enc: vcodec@17020000 { 1757aa8f3711SAllen-KH Cheng compatible = "mediatek,mt8192-vcodec-enc"; 1758aa8f3711SAllen-KH Cheng reg = <0 0x17020000 0 0x2000>; 1759aa8f3711SAllen-KH Cheng iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1760aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REC>, 1761aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1762aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1763aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1764aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1765aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1766aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1767aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1768aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1769aa8f3711SAllen-KH Cheng <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1770aa8f3711SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1771aa8f3711SAllen-KH Cheng mediatek,scp = <&scp>; 1772aa8f3711SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1773aa8f3711SAllen-KH Cheng clocks = <&vencsys CLK_VENC_SET1_VENC>; 1774a067a7ceSEugen Hristev clock-names = "venc_sel"; 1775aa8f3711SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1776aa8f3711SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1777aa8f3711SAllen-KH Cheng }; 1778aa8f3711SAllen-KH Cheng 17795d2b897bSChun-Jie Chen camsys: clock-controller@1a000000 { 17805d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys"; 17815d2b897bSChun-Jie Chen reg = <0 0x1a000000 0 0x1000>; 17825d2b897bSChun-Jie Chen #clock-cells = <1>; 17835d2b897bSChun-Jie Chen }; 17845d2b897bSChun-Jie Chen 17854a65b0f1SAllen-KH Cheng larb13: larb@1a001000 { 17864a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17874a65b0f1SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 17884a65b0f1SAllen-KH Cheng mediatek,larb-id = <13>; 17894a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 17904a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 17914a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB13>; 17924a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 17934a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 17944a65b0f1SAllen-KH Cheng }; 17954a65b0f1SAllen-KH Cheng 17964a65b0f1SAllen-KH Cheng larb14: larb@1a002000 { 17974a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 17984a65b0f1SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 17994a65b0f1SAllen-KH Cheng mediatek,larb-id = <14>; 18004a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18014a65b0f1SAllen-KH Cheng clocks = <&camsys CLK_CAM_CAM>, 18024a65b0f1SAllen-KH Cheng <&camsys CLK_CAM_LARB14>; 18034a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18044a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 18054a65b0f1SAllen-KH Cheng }; 18064a65b0f1SAllen-KH Cheng 18074a65b0f1SAllen-KH Cheng larb16: larb@1a00f000 { 18084a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18094a65b0f1SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 18104a65b0f1SAllen-KH Cheng mediatek,larb-id = <16>; 18114a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18124a65b0f1SAllen-KH Cheng clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 18134a65b0f1SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX>; 18144a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18154a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 18164a65b0f1SAllen-KH Cheng }; 18174a65b0f1SAllen-KH Cheng 18184a65b0f1SAllen-KH Cheng larb17: larb@1a010000 { 18194a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18204a65b0f1SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 18214a65b0f1SAllen-KH Cheng mediatek,larb-id = <17>; 18224a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18234a65b0f1SAllen-KH Cheng clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 18244a65b0f1SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX>; 18254a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18264a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 18274a65b0f1SAllen-KH Cheng }; 18284a65b0f1SAllen-KH Cheng 18294a65b0f1SAllen-KH Cheng larb18: larb@1a011000 { 18304a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18314a65b0f1SAllen-KH Cheng reg = <0 0x1a011000 0 0x1000>; 18324a65b0f1SAllen-KH Cheng mediatek,larb-id = <18>; 18334a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18344a65b0f1SAllen-KH Cheng clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 18354a65b0f1SAllen-KH Cheng <&camsys_rawc CLK_CAM_RAWC_CAM>; 18364a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18374a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 18384a65b0f1SAllen-KH Cheng }; 18394a65b0f1SAllen-KH Cheng 18405d2b897bSChun-Jie Chen camsys_rawa: clock-controller@1a04f000 { 18415d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawa"; 18425d2b897bSChun-Jie Chen reg = <0 0x1a04f000 0 0x1000>; 18435d2b897bSChun-Jie Chen #clock-cells = <1>; 18445d2b897bSChun-Jie Chen }; 18455d2b897bSChun-Jie Chen 18465d2b897bSChun-Jie Chen camsys_rawb: clock-controller@1a06f000 { 18475d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawb"; 18485d2b897bSChun-Jie Chen reg = <0 0x1a06f000 0 0x1000>; 18495d2b897bSChun-Jie Chen #clock-cells = <1>; 18505d2b897bSChun-Jie Chen }; 18515d2b897bSChun-Jie Chen 18525d2b897bSChun-Jie Chen camsys_rawc: clock-controller@1a08f000 { 18535d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-camsys_rawc"; 18545d2b897bSChun-Jie Chen reg = <0 0x1a08f000 0 0x1000>; 18555d2b897bSChun-Jie Chen #clock-cells = <1>; 18565d2b897bSChun-Jie Chen }; 18575d2b897bSChun-Jie Chen 18585d2b897bSChun-Jie Chen ipesys: clock-controller@1b000000 { 18595d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-ipesys"; 18605d2b897bSChun-Jie Chen reg = <0 0x1b000000 0 0x1000>; 18615d2b897bSChun-Jie Chen #clock-cells = <1>; 18625d2b897bSChun-Jie Chen }; 18635d2b897bSChun-Jie Chen 18644a65b0f1SAllen-KH Cheng larb20: larb@1b00f000 { 18654a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18664a65b0f1SAllen-KH Cheng reg = <0 0x1b00f000 0 0x1000>; 18674a65b0f1SAllen-KH Cheng mediatek,larb-id = <20>; 18684a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18694a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 18704a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB20>; 18714a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18724a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 18734a65b0f1SAllen-KH Cheng }; 18744a65b0f1SAllen-KH Cheng 18754a65b0f1SAllen-KH Cheng larb19: larb@1b10f000 { 18764a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18774a65b0f1SAllen-KH Cheng reg = <0 0x1b10f000 0 0x1000>; 18784a65b0f1SAllen-KH Cheng mediatek,larb-id = <19>; 18794a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18804a65b0f1SAllen-KH Cheng clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 18814a65b0f1SAllen-KH Cheng <&ipesys CLK_IPE_LARB19>; 18824a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 18834a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 18844a65b0f1SAllen-KH Cheng }; 18854a65b0f1SAllen-KH Cheng 18865d2b897bSChun-Jie Chen mdpsys: clock-controller@1f000000 { 18875d2b897bSChun-Jie Chen compatible = "mediatek,mt8192-mdpsys"; 18885d2b897bSChun-Jie Chen reg = <0 0x1f000000 0 0x1000>; 18895d2b897bSChun-Jie Chen #clock-cells = <1>; 18905d2b897bSChun-Jie Chen }; 18914a65b0f1SAllen-KH Cheng 18924a65b0f1SAllen-KH Cheng larb2: larb@1f002000 { 18934a65b0f1SAllen-KH Cheng compatible = "mediatek,mt8192-smi-larb"; 18944a65b0f1SAllen-KH Cheng reg = <0 0x1f002000 0 0x1000>; 18954a65b0f1SAllen-KH Cheng mediatek,larb-id = <2>; 18964a65b0f1SAllen-KH Cheng mediatek,smi = <&smi_common>; 18974a65b0f1SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, 18984a65b0f1SAllen-KH Cheng <&mdpsys CLK_MDP_SMI0>; 18994a65b0f1SAllen-KH Cheng clock-names = "apb", "smi"; 19004a65b0f1SAllen-KH Cheng power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 19014a65b0f1SAllen-KH Cheng }; 190248489980SSeiya Wang }; 190348489980SSeiya Wang}; 1904