1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 aliases { 12 serial0 = &uart0; 13 }; 14 15 chosen { 16 stdout-path = "serial0:115200n8"; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0 0x40000000 0 0x80000000>; 22 }; 23 24 /* system wide LDO 1.8V power rail */ 25 pp1800_ldo_g: regulator-1v8-g { 26 compatible = "regulator-fixed"; 27 regulator-name = "pp1800_ldo_g"; 28 regulator-always-on; 29 regulator-boot-on; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 vin-supply = <&pp3300_g>; 33 }; 34 35 /* system wide switching 3.3V power rail */ 36 pp3300_g: regulator-3v3-g { 37 compatible = "regulator-fixed"; 38 regulator-name = "pp3300_g"; 39 regulator-always-on; 40 regulator-boot-on; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 vin-supply = <&ppvar_sys>; 44 }; 45 46 /* system wide LDO 3.3V power rail */ 47 pp3300_ldo_z: regulator-3v3-z { 48 compatible = "regulator-fixed"; 49 regulator-name = "pp3300_ldo_z"; 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 vin-supply = <&ppvar_sys>; 55 }; 56 57 /* separately switched 3.3V power rail */ 58 pp3300_u: regulator-3v3-u { 59 compatible = "regulator-fixed"; 60 regulator-name = "pp3300_u"; 61 regulator-always-on; 62 regulator-boot-on; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 /* enable pin wired to GPIO controlled by EC */ 66 vin-supply = <&pp3300_g>; 67 }; 68 69 /* system wide switching 5.0V power rail */ 70 pp5000_a: regulator-5v0-a { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp5000_a"; 73 regulator-always-on; 74 regulator-boot-on; 75 regulator-min-microvolt = <5000000>; 76 regulator-max-microvolt = <5000000>; 77 vin-supply = <&ppvar_sys>; 78 }; 79 80 /* system wide semi-regulated power rail from battery or USB */ 81 ppvar_sys: regulator-var-sys { 82 compatible = "regulator-fixed"; 83 regulator-name = "ppvar_sys"; 84 regulator-always-on; 85 regulator-boot-on; 86 }; 87}; 88 89&i2c0 { 90 status = "okay"; 91 92 clock-frequency = <400000>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&i2c0_pins>; 95}; 96 97&i2c1 { 98 status = "okay"; 99 100 clock-frequency = <400000>; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&i2c1_pins>; 103}; 104 105&i2c2 { 106 status = "okay"; 107 108 clock-frequency = <400000>; 109 clock-stretch-ns = <12600>; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&i2c2_pins>; 112 113 trackpad@15 { 114 compatible = "elan,ekth3000"; 115 reg = <0x15>; 116 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&trackpad_pins>; 119 vcc-supply = <&pp3300_u>; 120 wakeup-source; 121 }; 122}; 123 124&i2c3 { 125 status = "okay"; 126 127 clock-frequency = <400000>; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&i2c3_pins>; 130}; 131 132&i2c7 { 133 status = "okay"; 134 135 clock-frequency = <400000>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&i2c7_pins>; 138}; 139 140&pio { 141 /* 220 lines */ 142 gpio-line-names = "I2S_DP_LRCK", 143 "IS_DP_BCLK", 144 "I2S_DP_MCLK", 145 "I2S_DP_DATAOUT", 146 "SAR0_INT_ODL", 147 "EC_AP_INT_ODL", 148 "EDPBRDG_INT_ODL", 149 "DPBRDG_INT_ODL", 150 "DPBRDG_PWREN", 151 "DPBRDG_RST_ODL", 152 "I2S_HP_MCLK", 153 "I2S_HP_BCK", 154 "I2S_HP_LRCK", 155 "I2S_HP_DATAIN", 156 /* 157 * AP_FLASH_WP_L is crossystem ABI. Schematics 158 * call it AP_FLASH_WP_ODL. 159 */ 160 "AP_FLASH_WP_L", 161 "TRACKPAD_INT_ODL", 162 "EC_AP_HPD_OD", 163 "SD_CD_ODL", 164 "HP_INT_ODL_ALC", 165 "EN_PP1000_DPBRDG", 166 "AP_GPIO20", 167 "TOUCH_INT_L_1V8", 168 "UART_BT_WAKE_ODL", 169 "AP_GPIO23", 170 "AP_SPI_FLASH_CS_L", 171 "AP_SPI_FLASH_CLK", 172 "EN_PP3300_DPBRDG_DX", 173 "AP_SPI_FLASH_MOSI", 174 "AP_SPI_FLASH_MISO", 175 "I2S_HP_DATAOUT", 176 "AP_GPIO30", 177 "I2S_SPKR_MCLK", 178 "I2S_SPKR_BCLK", 179 "I2S_SPKR_LRCK", 180 "I2S_SPKR_DATAIN", 181 "I2S_SPKR_DATAOUT", 182 "AP_SPI_H1_TPM_CLK", 183 "AP_SPI_H1_TPM_CS_L", 184 "AP_SPI_H1_TPM_MISO", 185 "AP_SPI_H1_TPM_MOSI", 186 "BL_PWM", 187 "EDPBRDG_PWREN", 188 "EDPBRDG_RST_ODL", 189 "EN_PP3300_HUB", 190 "HUB_RST_L", 191 "", 192 "", 193 "", 194 "", 195 "", 196 "", 197 "SD_CLK", 198 "SD_CMD", 199 "SD_DATA3", 200 "SD_DATA0", 201 "SD_DATA2", 202 "SD_DATA1", 203 "", 204 "", 205 "", 206 "", 207 "", 208 "", 209 "PCIE_WAKE_ODL", 210 "PCIE_RST_L", 211 "PCIE_CLKREQ_ODL", 212 "", 213 "", 214 "", 215 "", 216 "", 217 "", 218 "", 219 "", 220 "", 221 "", 222 "", 223 "", 224 "", 225 "", 226 "", 227 "", 228 "", 229 "", 230 "", 231 "", 232 "", 233 "", 234 "", 235 "SPMI_SCL", 236 "SPMI_SDA", 237 "AP_GOOD", 238 "UART_DBG_TX_AP_RX", 239 "UART_AP_TX_DBG_RX", 240 "UART_AP_TX_BT_RX", 241 "UART_BT_TX_AP_RX", 242 "MIPI_DPI_D0_R", 243 "MIPI_DPI_D1_R", 244 "MIPI_DPI_D2_R", 245 "MIPI_DPI_D3_R", 246 "MIPI_DPI_D4_R", 247 "MIPI_DPI_D5_R", 248 "MIPI_DPI_D6_R", 249 "MIPI_DPI_D7_R", 250 "MIPI_DPI_D8_R", 251 "MIPI_DPI_D9_R", 252 "MIPI_DPI_D10_R", 253 "", 254 "", 255 "MIPI_DPI_DE_R", 256 "MIPI_DPI_D11_R", 257 "MIPI_DPI_VSYNC_R", 258 "MIPI_DPI_CLK_R", 259 "MIPI_DPI_HSYNC_R", 260 "PCM_BT_DATAIN", 261 "PCM_BT_SYNC", 262 "PCM_BT_DATAOUT", 263 "PCM_BT_CLK", 264 "AP_I2C_AUDIO_SCL", 265 "AP_I2C_AUDIO_SDA", 266 "SCP_I2C_SCL", 267 "SCP_I2C_SDA", 268 "AP_I2C_WLAN_SCL", 269 "AP_I2C_WLAN_SDA", 270 "AP_I2C_DPBRDG_SCL", 271 "AP_I2C_DPBRDG_SDA", 272 "EN_PP1800_DPBRDG_DX", 273 "EN_PP3300_EDP_DX", 274 "EN_PP1800_EDPBRDG_DX", 275 "EN_PP1000_EDPBRDG", 276 "SCP_JTAG0_TDO", 277 "SCP_JTAG0_TDI", 278 "SCP_JTAG0_TMS", 279 "SCP_JTAG0_TCK", 280 "SCP_JTAG0_TRSTN", 281 "EN_PP3000_VMC_PMU", 282 "EN_PP3300_DISPLAY_DX", 283 "TOUCH_RST_L_1V8", 284 "TOUCH_REPORT_DISABLE", 285 "", 286 "", 287 "AP_I2C_TRACKPAD_SCL_1V8", 288 "AP_I2C_TRACKPAD_SDA_1V8", 289 "EN_PP3300_WLAN", 290 "BT_KILL_L", 291 "WIFI_KILL_L", 292 "SET_VMC_VOLT_AT_1V8", 293 "EN_SPK", 294 "AP_WARM_RST_REQ", 295 "", 296 "", 297 "EN_PP3000_SD_S3", 298 "AP_EDP_BKLTEN", 299 "", 300 "", 301 "", 302 "AP_SPI_EC_CLK", 303 "AP_SPI_EC_CS_L", 304 "AP_SPI_EC_MISO", 305 "AP_SPI_EC_MOSI", 306 "AP_I2C_EDPBRDG_SCL", 307 "AP_I2C_EDPBRDG_SDA", 308 "MT6315_PROC_INT", 309 "MT6315_GPU_INT", 310 "UART_SERVO_TX_SCP_RX", 311 "UART_SCP_TX_SERVO_RX", 312 "BT_RTS_AP_CTS", 313 "AP_RTS_BT_CTS", 314 "UART_AP_WAKE_BT_ODL", 315 "WLAN_ALERT_ODL", 316 "EC_IN_RW_ODL", 317 "H1_AP_INT_ODL", 318 "", 319 "", 320 "", 321 "", 322 "", 323 "", 324 "", 325 "", 326 "", 327 "", 328 "", 329 "MSDC0_CMD", 330 "MSDC0_DAT0", 331 "MSDC0_DAT2", 332 "MSDC0_DAT4", 333 "MSDC0_DAT6", 334 "MSDC0_DAT1", 335 "MSDC0_DAT5", 336 "MSDC0_DAT7", 337 "MSDC0_DSL", 338 "MSDC0_CLK", 339 "MSDC0_DAT3", 340 "MSDC0_RST_L", 341 "SCP_VREQ_VAO", 342 "AUD_DAT_MOSI2", 343 "AUD_NLE_MOSI1", 344 "AUD_NLE_MOSI0", 345 "AUD_DAT_MISO2", 346 "AP_I2C_SAR_SDA", 347 "AP_I2C_SAR_SCL", 348 "AP_I2C_PWR_SCL", 349 "AP_I2C_PWR_SDA", 350 "AP_I2C_TS_SCL_1V8", 351 "AP_I2C_TS_SDA_1V8", 352 "SRCLKENA0", 353 "SRCLKENA1", 354 "AP_EC_WATCHDOG_L", 355 "PWRAP_SPI0_MI", 356 "PWRAP_SPI0_CSN", 357 "PWRAP_SPI0_MO", 358 "PWRAP_SPI0_CK", 359 "AP_RTC_CLK32K", 360 "AUD_CLK_MOSI", 361 "AUD_SYNC_MOSI", 362 "AUD_DAT_MOSI0", 363 "AUD_DAT_MOSI1", 364 "AUD_DAT_MISO0", 365 "AUD_DAT_MISO1"; 366 367 cr50_int: cr50-irq-default-pins { 368 pins-gsc-ap-int-odl { 369 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 370 input-enable; 371 }; 372 }; 373 374 cros_ec_int: cros-ec-irq-default-pins { 375 pins-ec-ap-int-odl { 376 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 377 input-enable; 378 bias-pull-up; 379 }; 380 }; 381 382 i2c0_pins: i2c0-default-pins { 383 pins-bus { 384 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 385 <PINMUX_GPIO205__FUNC_SDA0>; 386 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 387 drive-strength-microamp = <1000>; 388 }; 389 }; 390 391 i2c1_pins: i2c1-default-pins { 392 pins-bus { 393 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 394 <PINMUX_GPIO119__FUNC_SDA1>; 395 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 396 drive-strength-microamp = <1000>; 397 }; 398 }; 399 400 i2c2_pins: i2c2-default-pins { 401 pins-bus { 402 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 403 <PINMUX_GPIO142__FUNC_SDA2>; 404 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 405 }; 406 }; 407 408 i2c3_pins: i2c3-default-pins { 409 pins-bus { 410 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 411 <PINMUX_GPIO161__FUNC_SDA3>; 412 bias-disable; 413 drive-strength-microamp = <1000>; 414 }; 415 }; 416 417 i2c7_pins: i2c7-default-pins { 418 pins-bus { 419 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 420 <PINMUX_GPIO125__FUNC_SDA7>; 421 bias-disable; 422 drive-strength-microamp = <1000>; 423 }; 424 }; 425 426 spi1_pins: spi1-default-pins { 427 pins-cs-mosi-clk { 428 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 429 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 430 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 431 bias-disable; 432 }; 433 434 pins-miso { 435 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 436 bias-pull-down; 437 }; 438 }; 439 440 spi5_pins: spi5-default-pins { 441 pins-bus { 442 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 443 <PINMUX_GPIO37__FUNC_GPIO37>, 444 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 445 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 446 bias-disable; 447 }; 448 }; 449 450 trackpad_pins: trackpad-default-pins { 451 pins-int-n { 452 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 453 input-enable; 454 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 455 }; 456 }; 457}; 458 459&spi1 { 460 status = "okay"; 461 462 mediatek,pad-select = <0>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&spi1_pins>; 465 466 cros_ec: ec@0 { 467 compatible = "google,cros-ec-spi"; 468 reg = <0>; 469 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 470 spi-max-frequency = <3000000>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&cros_ec_int>; 473 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 base_detection: cbas { 478 compatible = "google,cros-cbas"; 479 }; 480 481 cros_ec_pwm: pwm { 482 compatible = "google,cros-ec-pwm"; 483 #pwm-cells = <1>; 484 485 status = "disabled"; 486 }; 487 488 i2c_tunnel: i2c-tunnel { 489 compatible = "google,cros-ec-i2c-tunnel"; 490 google,remote-bus = <0>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 }; 494 495 mt6360_ldo3_reg: regulator@0 { 496 compatible = "google,cros-ec-regulator"; 497 reg = <0>; 498 regulator-min-microvolt = <1800000>; 499 regulator-max-microvolt = <3300000>; 500 }; 501 502 mt6360_ldo5_reg: regulator@1 { 503 compatible = "google,cros-ec-regulator"; 504 reg = <1>; 505 regulator-min-microvolt = <3300000>; 506 regulator-max-microvolt = <3300000>; 507 }; 508 509 typec { 510 compatible = "google,cros-ec-typec"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 514 usb_c0: connector@0 { 515 compatible = "usb-c-connector"; 516 reg = <0>; 517 label = "left"; 518 power-role = "dual"; 519 data-role = "host"; 520 try-power-role = "source"; 521 }; 522 523 usb_c1: connector@1 { 524 compatible = "usb-c-connector"; 525 reg = <1>; 526 label = "right"; 527 power-role = "dual"; 528 data-role = "host"; 529 try-power-role = "source"; 530 }; 531 }; 532 }; 533}; 534 535&spi5 { 536 status = "okay"; 537 538 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 539 mediatek,pad-select = <0>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&spi5_pins>; 542 543 cr50@0 { 544 compatible = "google,cr50"; 545 reg = <0>; 546 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 547 spi-max-frequency = <1000000>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&cr50_int>; 550 }; 551}; 552 553&uart0 { 554 status = "okay"; 555}; 556 557#include <arm/cros-ec-keyboard.dtsi> 558#include <arm/cros-ec-sbs.dtsi> 559