1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6/dts-v1/;
7#include "mt8192.dtsi"
8
9/ {
10	aliases {
11		serial0 = &uart0;
12	};
13
14	chosen {
15		stdout-path = "serial0:115200n8";
16	};
17
18	memory@40000000 {
19		device_type = "memory";
20		reg = <0 0x40000000 0 0x80000000>;
21	};
22
23	/* system wide LDO 1.8V power rail */
24	pp1800_ldo_g: regulator-1v8-g {
25		compatible = "regulator-fixed";
26		regulator-name = "pp1800_ldo_g";
27		regulator-always-on;
28		regulator-boot-on;
29		regulator-min-microvolt = <1800000>;
30		regulator-max-microvolt = <1800000>;
31		vin-supply = <&pp3300_g>;
32	};
33
34	/* system wide switching 3.3V power rail */
35	pp3300_g: regulator-3v3-g {
36		compatible = "regulator-fixed";
37		regulator-name = "pp3300_g";
38		regulator-always-on;
39		regulator-boot-on;
40		regulator-min-microvolt = <3300000>;
41		regulator-max-microvolt = <3300000>;
42		vin-supply = <&ppvar_sys>;
43	};
44
45	/* system wide LDO 3.3V power rail */
46	pp3300_ldo_z: regulator-3v3-z {
47		compatible = "regulator-fixed";
48		regulator-name = "pp3300_ldo_z";
49		regulator-always-on;
50		regulator-boot-on;
51		regulator-min-microvolt = <3300000>;
52		regulator-max-microvolt = <3300000>;
53		vin-supply = <&ppvar_sys>;
54	};
55
56	/* separately switched 3.3V power rail */
57	pp3300_u: regulator-3v3-u {
58		compatible = "regulator-fixed";
59		regulator-name = "pp3300_u";
60		regulator-always-on;
61		regulator-boot-on;
62		regulator-min-microvolt = <3300000>;
63		regulator-max-microvolt = <3300000>;
64		/* enable pin wired to GPIO controlled by EC */
65		vin-supply = <&pp3300_g>;
66	};
67
68	/* system wide switching 5.0V power rail */
69	pp5000_a: regulator-5v0-a {
70		compatible = "regulator-fixed";
71		regulator-name = "pp5000_a";
72		regulator-always-on;
73		regulator-boot-on;
74		regulator-min-microvolt = <5000000>;
75		regulator-max-microvolt = <5000000>;
76		vin-supply = <&ppvar_sys>;
77	};
78
79	/* system wide semi-regulated power rail from battery or USB */
80	ppvar_sys: regulator-var-sys {
81		compatible = "regulator-fixed";
82		regulator-name = "ppvar_sys";
83		regulator-always-on;
84		regulator-boot-on;
85	};
86};
87
88&pio {
89	/* 220 lines */
90	gpio-line-names = "I2S_DP_LRCK",
91			  "IS_DP_BCLK",
92			  "I2S_DP_MCLK",
93			  "I2S_DP_DATAOUT",
94			  "SAR0_INT_ODL",
95			  "EC_AP_INT_ODL",
96			  "EDPBRDG_INT_ODL",
97			  "DPBRDG_INT_ODL",
98			  "DPBRDG_PWREN",
99			  "DPBRDG_RST_ODL",
100			  "I2S_HP_MCLK",
101			  "I2S_HP_BCK",
102			  "I2S_HP_LRCK",
103			  "I2S_HP_DATAIN",
104			  /*
105			   * AP_FLASH_WP_L is crossystem ABI. Schematics
106			   * call it AP_FLASH_WP_ODL.
107			   */
108			  "AP_FLASH_WP_L",
109			  "TRACKPAD_INT_ODL",
110			  "EC_AP_HPD_OD",
111			  "SD_CD_ODL",
112			  "HP_INT_ODL_ALC",
113			  "EN_PP1000_DPBRDG",
114			  "AP_GPIO20",
115			  "TOUCH_INT_L_1V8",
116			  "UART_BT_WAKE_ODL",
117			  "AP_GPIO23",
118			  "AP_SPI_FLASH_CS_L",
119			  "AP_SPI_FLASH_CLK",
120			  "EN_PP3300_DPBRDG_DX",
121			  "AP_SPI_FLASH_MOSI",
122			  "AP_SPI_FLASH_MISO",
123			  "I2S_HP_DATAOUT",
124			  "AP_GPIO30",
125			  "I2S_SPKR_MCLK",
126			  "I2S_SPKR_BCLK",
127			  "I2S_SPKR_LRCK",
128			  "I2S_SPKR_DATAIN",
129			  "I2S_SPKR_DATAOUT",
130			  "AP_SPI_H1_TPM_CLK",
131			  "AP_SPI_H1_TPM_CS_L",
132			  "AP_SPI_H1_TPM_MISO",
133			  "AP_SPI_H1_TPM_MOSI",
134			  "BL_PWM",
135			  "EDPBRDG_PWREN",
136			  "EDPBRDG_RST_ODL",
137			  "EN_PP3300_HUB",
138			  "HUB_RST_L",
139			  "",
140			  "",
141			  "",
142			  "",
143			  "",
144			  "",
145			  "SD_CLK",
146			  "SD_CMD",
147			  "SD_DATA3",
148			  "SD_DATA0",
149			  "SD_DATA2",
150			  "SD_DATA1",
151			  "",
152			  "",
153			  "",
154			  "",
155			  "",
156			  "",
157			  "PCIE_WAKE_ODL",
158			  "PCIE_RST_L",
159			  "PCIE_CLKREQ_ODL",
160			  "",
161			  "",
162			  "",
163			  "",
164			  "",
165			  "",
166			  "",
167			  "",
168			  "",
169			  "",
170			  "",
171			  "",
172			  "",
173			  "",
174			  "",
175			  "",
176			  "",
177			  "",
178			  "",
179			  "",
180			  "",
181			  "",
182			  "",
183			  "SPMI_SCL",
184			  "SPMI_SDA",
185			  "AP_GOOD",
186			  "UART_DBG_TX_AP_RX",
187			  "UART_AP_TX_DBG_RX",
188			  "UART_AP_TX_BT_RX",
189			  "UART_BT_TX_AP_RX",
190			  "MIPI_DPI_D0_R",
191			  "MIPI_DPI_D1_R",
192			  "MIPI_DPI_D2_R",
193			  "MIPI_DPI_D3_R",
194			  "MIPI_DPI_D4_R",
195			  "MIPI_DPI_D5_R",
196			  "MIPI_DPI_D6_R",
197			  "MIPI_DPI_D7_R",
198			  "MIPI_DPI_D8_R",
199			  "MIPI_DPI_D9_R",
200			  "MIPI_DPI_D10_R",
201			  "",
202			  "",
203			  "MIPI_DPI_DE_R",
204			  "MIPI_DPI_D11_R",
205			  "MIPI_DPI_VSYNC_R",
206			  "MIPI_DPI_CLK_R",
207			  "MIPI_DPI_HSYNC_R",
208			  "PCM_BT_DATAIN",
209			  "PCM_BT_SYNC",
210			  "PCM_BT_DATAOUT",
211			  "PCM_BT_CLK",
212			  "AP_I2C_AUDIO_SCL",
213			  "AP_I2C_AUDIO_SDA",
214			  "SCP_I2C_SCL",
215			  "SCP_I2C_SDA",
216			  "AP_I2C_WLAN_SCL",
217			  "AP_I2C_WLAN_SDA",
218			  "AP_I2C_DPBRDG_SCL",
219			  "AP_I2C_DPBRDG_SDA",
220			  "EN_PP1800_DPBRDG_DX",
221			  "EN_PP3300_EDP_DX",
222			  "EN_PP1800_EDPBRDG_DX",
223			  "EN_PP1000_EDPBRDG",
224			  "SCP_JTAG0_TDO",
225			  "SCP_JTAG0_TDI",
226			  "SCP_JTAG0_TMS",
227			  "SCP_JTAG0_TCK",
228			  "SCP_JTAG0_TRSTN",
229			  "EN_PP3000_VMC_PMU",
230			  "EN_PP3300_DISPLAY_DX",
231			  "TOUCH_RST_L_1V8",
232			  "TOUCH_REPORT_DISABLE",
233			  "",
234			  "",
235			  "AP_I2C_TRACKPAD_SCL_1V8",
236			  "AP_I2C_TRACKPAD_SDA_1V8",
237			  "EN_PP3300_WLAN",
238			  "BT_KILL_L",
239			  "WIFI_KILL_L",
240			  "SET_VMC_VOLT_AT_1V8",
241			  "EN_SPK",
242			  "AP_WARM_RST_REQ",
243			  "",
244			  "",
245			  "EN_PP3000_SD_S3",
246			  "AP_EDP_BKLTEN",
247			  "",
248			  "",
249			  "",
250			  "AP_SPI_EC_CLK",
251			  "AP_SPI_EC_CS_L",
252			  "AP_SPI_EC_MISO",
253			  "AP_SPI_EC_MOSI",
254			  "AP_I2C_EDPBRDG_SCL",
255			  "AP_I2C_EDPBRDG_SDA",
256			  "MT6315_PROC_INT",
257			  "MT6315_GPU_INT",
258			  "UART_SERVO_TX_SCP_RX",
259			  "UART_SCP_TX_SERVO_RX",
260			  "BT_RTS_AP_CTS",
261			  "AP_RTS_BT_CTS",
262			  "UART_AP_WAKE_BT_ODL",
263			  "WLAN_ALERT_ODL",
264			  "EC_IN_RW_ODL",
265			  "H1_AP_INT_ODL",
266			  "",
267			  "",
268			  "",
269			  "",
270			  "",
271			  "",
272			  "",
273			  "",
274			  "",
275			  "",
276			  "",
277			  "MSDC0_CMD",
278			  "MSDC0_DAT0",
279			  "MSDC0_DAT2",
280			  "MSDC0_DAT4",
281			  "MSDC0_DAT6",
282			  "MSDC0_DAT1",
283			  "MSDC0_DAT5",
284			  "MSDC0_DAT7",
285			  "MSDC0_DSL",
286			  "MSDC0_CLK",
287			  "MSDC0_DAT3",
288			  "MSDC0_RST_L",
289			  "SCP_VREQ_VAO",
290			  "AUD_DAT_MOSI2",
291			  "AUD_NLE_MOSI1",
292			  "AUD_NLE_MOSI0",
293			  "AUD_DAT_MISO2",
294			  "AP_I2C_SAR_SDA",
295			  "AP_I2C_SAR_SCL",
296			  "AP_I2C_PWR_SCL",
297			  "AP_I2C_PWR_SDA",
298			  "AP_I2C_TS_SCL_1V8",
299			  "AP_I2C_TS_SDA_1V8",
300			  "SRCLKENA0",
301			  "SRCLKENA1",
302			  "AP_EC_WATCHDOG_L",
303			  "PWRAP_SPI0_MI",
304			  "PWRAP_SPI0_CSN",
305			  "PWRAP_SPI0_MO",
306			  "PWRAP_SPI0_CK",
307			  "AP_RTC_CLK32K",
308			  "AUD_CLK_MOSI",
309			  "AUD_SYNC_MOSI",
310			  "AUD_DAT_MOSI0",
311			  "AUD_DAT_MOSI1",
312			  "AUD_DAT_MISO0",
313			  "AUD_DAT_MISO1";
314};
315
316&uart0 {
317	status = "okay";
318};
319