1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 sound: sound { 214 mediatek,platform = <&afe>; 215 pinctrl-names = "aud_clk_mosi_off", 216 "aud_clk_mosi_on", 217 "aud_dat_mosi_off", 218 "aud_dat_mosi_on", 219 "aud_dat_miso_off", 220 "aud_dat_miso_on", 221 "vow_dat_miso_off", 222 "vow_dat_miso_on", 223 "vow_clk_miso_off", 224 "vow_clk_miso_on", 225 "aud_nle_mosi_off", 226 "aud_nle_mosi_on", 227 "aud_dat_miso2_off", 228 "aud_dat_miso2_on", 229 "aud_gpio_i2s3_off", 230 "aud_gpio_i2s3_on", 231 "aud_gpio_i2s8_off", 232 "aud_gpio_i2s8_on", 233 "aud_gpio_i2s9_off", 234 "aud_gpio_i2s9_on", 235 "aud_dat_mosi_ch34_off", 236 "aud_dat_mosi_ch34_on", 237 "aud_dat_miso_ch34_off", 238 "aud_dat_miso_ch34_on", 239 "aud_gpio_tdm_off", 240 "aud_gpio_tdm_on"; 241 pinctrl-0 = <&aud_clk_mosi_off_pins>; 242 pinctrl-1 = <&aud_clk_mosi_on_pins>; 243 pinctrl-2 = <&aud_dat_mosi_off_pins>; 244 pinctrl-3 = <&aud_dat_mosi_on_pins>; 245 pinctrl-4 = <&aud_dat_miso_off_pins>; 246 pinctrl-5 = <&aud_dat_miso_on_pins>; 247 pinctrl-6 = <&vow_dat_miso_off_pins>; 248 pinctrl-7 = <&vow_dat_miso_on_pins>; 249 pinctrl-8 = <&vow_clk_miso_off_pins>; 250 pinctrl-9 = <&vow_clk_miso_on_pins>; 251 pinctrl-10 = <&aud_nle_mosi_off_pins>; 252 pinctrl-11 = <&aud_nle_mosi_on_pins>; 253 pinctrl-12 = <&aud_dat_miso2_off_pins>; 254 pinctrl-13 = <&aud_dat_miso2_on_pins>; 255 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 256 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 257 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 258 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 259 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 260 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 261 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 262 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 263 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 264 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 265 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 266 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 267 }; 268}; 269 270&dsi0 { 271 status = "okay"; 272}; 273 274&dsi_out { 275 remote-endpoint = <&anx7625_in>; 276}; 277 278&i2c0 { 279 status = "okay"; 280 281 clock-frequency = <400000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c0_pins>; 284 285 touchscreen: touchscreen@10 { 286 reg = <0x10>; 287 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&touchscreen_pins>; 290 }; 291}; 292 293&i2c1 { 294 status = "okay"; 295 296 clock-frequency = <400000>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c1_pins>; 299}; 300 301&i2c2 { 302 status = "okay"; 303 304 clock-frequency = <400000>; 305 clock-stretch-ns = <12600>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&i2c2_pins>; 308 309 trackpad@15 { 310 compatible = "elan,ekth3000"; 311 reg = <0x15>; 312 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&trackpad_pins>; 315 vcc-supply = <&pp3300_u>; 316 wakeup-source; 317 }; 318}; 319 320&i2c3 { 321 status = "okay"; 322 323 clock-frequency = <400000>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c3_pins>; 326 327 anx_bridge: anx7625@58 { 328 compatible = "analogix,anx7625"; 329 reg = <0x58>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&anx7625_pins>; 332 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 333 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 334 vdd10-supply = <&pp1000_mipibrdg>; 335 vdd18-supply = <&pp1800_mipibrdg>; 336 vdd33-supply = <&pp3300_mipibrdg>; 337 338 ports { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 port@0 { 343 reg = <0>; 344 345 anx7625_in: endpoint { 346 remote-endpoint = <&dsi_out>; 347 }; 348 }; 349 350 port@1 { 351 reg = <1>; 352 353 anx7625_out: endpoint { 354 remote-endpoint = <&panel_in>; 355 }; 356 }; 357 }; 358 359 aux-bus { 360 panel: panel { 361 compatible = "edp-panel"; 362 power-supply = <&pp3300_mipibrdg>; 363 backlight = <&backlight_lcd0>; 364 365 port { 366 panel_in: endpoint { 367 remote-endpoint = <&anx7625_out>; 368 }; 369 }; 370 }; 371 }; 372 }; 373}; 374 375&i2c7 { 376 status = "okay"; 377 378 clock-frequency = <400000>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c7_pins>; 381}; 382 383&mfg0 { 384 domain-supply = <&mt6315_7_vbuck1>; 385}; 386 387&mfg1 { 388 domain-supply = <&mt6359_vsram_others_ldo_reg>; 389}; 390 391&mipi_tx0 { 392 status = "okay"; 393}; 394 395&mmc0 { 396 status = "okay"; 397 398 pinctrl-names = "default", "state_uhs"; 399 pinctrl-0 = <&mmc0_default_pins>; 400 pinctrl-1 = <&mmc0_uhs_pins>; 401 bus-width = <8>; 402 max-frequency = <200000000>; 403 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 404 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 405 cap-mmc-highspeed; 406 mmc-hs200-1_8v; 407 mmc-hs400-1_8v; 408 supports-cqe; 409 cap-mmc-hw-reset; 410 mmc-hs400-enhanced-strobe; 411 hs400-ds-delay = <0x12814>; 412 no-sdio; 413 no-sd; 414 non-removable; 415}; 416 417&mmc1 { 418 status = "okay"; 419 420 pinctrl-names = "default", "state_uhs"; 421 pinctrl-0 = <&mmc1_default_pins>; 422 pinctrl-1 = <&mmc1_uhs_pins>; 423 bus-width = <4>; 424 max-frequency = <200000000>; 425 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 426 vmmc-supply = <&mt6360_ldo5_reg>; 427 vqmmc-supply = <&mt6360_ldo3_reg>; 428 cap-sd-highspeed; 429 sd-uhs-sdr50; 430 sd-uhs-sdr104; 431 no-sdio; 432 no-mmc; 433}; 434 435/* for CORE */ 436&mt6359_vgpu11_buck_reg { 437 regulator-always-on; 438}; 439 440&mt6359_vgpu11_sshub_buck_reg { 441 regulator-always-on; 442 regulator-min-microvolt = <575000>; 443 regulator-max-microvolt = <575000>; 444}; 445 446&mt6359_vrf12_ldo_reg { 447 regulator-always-on; 448}; 449 450&mt6359_vsram_others_ldo_reg { 451 regulator-min-microvolt = <750000>; 452 regulator-max-microvolt = <800000>; 453 regulator-coupled-with = <&mt6315_7_vbuck1>; 454 regulator-coupled-max-spread = <10000>; 455}; 456 457&mt6359_vufs_ldo_reg { 458 regulator-always-on; 459}; 460 461&mt6359codec { 462 mediatek,dmic-mode = <1>; /* one-wire */ 463 mediatek,mic-type-0 = <2>; /* DMIC */ 464 mediatek,mic-type-2 = <2>; /* DMIC */ 465}; 466 467&nor_flash { 468 status = "okay"; 469 470 pinctrl-names = "default"; 471 pinctrl-0 = <&nor_flash_pins>; 472 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 474 475 flash@0 { 476 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 477 reg = <0>; 478 spi-max-frequency = <52000000>; 479 spi-rx-bus-width = <2>; 480 spi-tx-bus-width = <2>; 481 }; 482}; 483 484&pcie { 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pcie_pins>; 487 488 pcie0: pcie@0,0 { 489 device_type = "pci"; 490 reg = <0x0000 0 0 0 0>; 491 num-lanes = <1>; 492 bus-range = <0x1 0x1>; 493 494 #address-cells = <3>; 495 #size-cells = <2>; 496 ranges; 497 498 wifi: wifi@0,0 { 499 reg = <0x10000 0 0 0 0x100000>, 500 <0x10000 0 0x100000 0 0x100000>; 501 memory-region = <&wifi_restricted_dma_region>; 502 }; 503 }; 504}; 505 506&pio { 507 /* 220 lines */ 508 gpio-line-names = "I2S_DP_LRCK", 509 "IS_DP_BCLK", 510 "I2S_DP_MCLK", 511 "I2S_DP_DATAOUT", 512 "SAR0_INT_ODL", 513 "EC_AP_INT_ODL", 514 "EDPBRDG_INT_ODL", 515 "DPBRDG_INT_ODL", 516 "DPBRDG_PWREN", 517 "DPBRDG_RST_ODL", 518 "I2S_HP_MCLK", 519 "I2S_HP_BCK", 520 "I2S_HP_LRCK", 521 "I2S_HP_DATAIN", 522 /* 523 * AP_FLASH_WP_L is crossystem ABI. Schematics 524 * call it AP_FLASH_WP_ODL. 525 */ 526 "AP_FLASH_WP_L", 527 "TRACKPAD_INT_ODL", 528 "EC_AP_HPD_OD", 529 "SD_CD_ODL", 530 "HP_INT_ODL_ALC", 531 "EN_PP1000_DPBRDG", 532 "AP_GPIO20", 533 "TOUCH_INT_L_1V8", 534 "UART_BT_WAKE_ODL", 535 "AP_GPIO23", 536 "AP_SPI_FLASH_CS_L", 537 "AP_SPI_FLASH_CLK", 538 "EN_PP3300_DPBRDG_DX", 539 "AP_SPI_FLASH_MOSI", 540 "AP_SPI_FLASH_MISO", 541 "I2S_HP_DATAOUT", 542 "AP_GPIO30", 543 "I2S_SPKR_MCLK", 544 "I2S_SPKR_BCLK", 545 "I2S_SPKR_LRCK", 546 "I2S_SPKR_DATAIN", 547 "I2S_SPKR_DATAOUT", 548 "AP_SPI_H1_TPM_CLK", 549 "AP_SPI_H1_TPM_CS_L", 550 "AP_SPI_H1_TPM_MISO", 551 "AP_SPI_H1_TPM_MOSI", 552 "BL_PWM", 553 "EDPBRDG_PWREN", 554 "EDPBRDG_RST_ODL", 555 "EN_PP3300_HUB", 556 "HUB_RST_L", 557 "", 558 "", 559 "", 560 "", 561 "", 562 "", 563 "SD_CLK", 564 "SD_CMD", 565 "SD_DATA3", 566 "SD_DATA0", 567 "SD_DATA2", 568 "SD_DATA1", 569 "", 570 "", 571 "", 572 "", 573 "", 574 "", 575 "PCIE_WAKE_ODL", 576 "PCIE_RST_L", 577 "PCIE_CLKREQ_ODL", 578 "", 579 "", 580 "", 581 "", 582 "", 583 "", 584 "", 585 "", 586 "", 587 "", 588 "", 589 "", 590 "", 591 "", 592 "", 593 "", 594 "", 595 "", 596 "", 597 "", 598 "", 599 "", 600 "", 601 "SPMI_SCL", 602 "SPMI_SDA", 603 "AP_GOOD", 604 "UART_DBG_TX_AP_RX", 605 "UART_AP_TX_DBG_RX", 606 "UART_AP_TX_BT_RX", 607 "UART_BT_TX_AP_RX", 608 "MIPI_DPI_D0_R", 609 "MIPI_DPI_D1_R", 610 "MIPI_DPI_D2_R", 611 "MIPI_DPI_D3_R", 612 "MIPI_DPI_D4_R", 613 "MIPI_DPI_D5_R", 614 "MIPI_DPI_D6_R", 615 "MIPI_DPI_D7_R", 616 "MIPI_DPI_D8_R", 617 "MIPI_DPI_D9_R", 618 "MIPI_DPI_D10_R", 619 "", 620 "", 621 "MIPI_DPI_DE_R", 622 "MIPI_DPI_D11_R", 623 "MIPI_DPI_VSYNC_R", 624 "MIPI_DPI_CLK_R", 625 "MIPI_DPI_HSYNC_R", 626 "PCM_BT_DATAIN", 627 "PCM_BT_SYNC", 628 "PCM_BT_DATAOUT", 629 "PCM_BT_CLK", 630 "AP_I2C_AUDIO_SCL", 631 "AP_I2C_AUDIO_SDA", 632 "SCP_I2C_SCL", 633 "SCP_I2C_SDA", 634 "AP_I2C_WLAN_SCL", 635 "AP_I2C_WLAN_SDA", 636 "AP_I2C_DPBRDG_SCL", 637 "AP_I2C_DPBRDG_SDA", 638 "EN_PP1800_DPBRDG_DX", 639 "EN_PP3300_EDP_DX", 640 "EN_PP1800_EDPBRDG_DX", 641 "EN_PP1000_EDPBRDG", 642 "SCP_JTAG0_TDO", 643 "SCP_JTAG0_TDI", 644 "SCP_JTAG0_TMS", 645 "SCP_JTAG0_TCK", 646 "SCP_JTAG0_TRSTN", 647 "EN_PP3000_VMC_PMU", 648 "EN_PP3300_DISPLAY_DX", 649 "TOUCH_RST_L_1V8", 650 "TOUCH_REPORT_DISABLE", 651 "", 652 "", 653 "AP_I2C_TRACKPAD_SCL_1V8", 654 "AP_I2C_TRACKPAD_SDA_1V8", 655 "EN_PP3300_WLAN", 656 "BT_KILL_L", 657 "WIFI_KILL_L", 658 "SET_VMC_VOLT_AT_1V8", 659 "EN_SPK", 660 "AP_WARM_RST_REQ", 661 "", 662 "", 663 "EN_PP3000_SD_S3", 664 "AP_EDP_BKLTEN", 665 "", 666 "", 667 "", 668 "AP_SPI_EC_CLK", 669 "AP_SPI_EC_CS_L", 670 "AP_SPI_EC_MISO", 671 "AP_SPI_EC_MOSI", 672 "AP_I2C_EDPBRDG_SCL", 673 "AP_I2C_EDPBRDG_SDA", 674 "MT6315_PROC_INT", 675 "MT6315_GPU_INT", 676 "UART_SERVO_TX_SCP_RX", 677 "UART_SCP_TX_SERVO_RX", 678 "BT_RTS_AP_CTS", 679 "AP_RTS_BT_CTS", 680 "UART_AP_WAKE_BT_ODL", 681 "WLAN_ALERT_ODL", 682 "EC_IN_RW_ODL", 683 "H1_AP_INT_ODL", 684 "", 685 "", 686 "", 687 "", 688 "", 689 "", 690 "", 691 "", 692 "", 693 "", 694 "", 695 "MSDC0_CMD", 696 "MSDC0_DAT0", 697 "MSDC0_DAT2", 698 "MSDC0_DAT4", 699 "MSDC0_DAT6", 700 "MSDC0_DAT1", 701 "MSDC0_DAT5", 702 "MSDC0_DAT7", 703 "MSDC0_DSL", 704 "MSDC0_CLK", 705 "MSDC0_DAT3", 706 "MSDC0_RST_L", 707 "SCP_VREQ_VAO", 708 "AUD_DAT_MOSI2", 709 "AUD_NLE_MOSI1", 710 "AUD_NLE_MOSI0", 711 "AUD_DAT_MISO2", 712 "AP_I2C_SAR_SDA", 713 "AP_I2C_SAR_SCL", 714 "AP_I2C_PWR_SCL", 715 "AP_I2C_PWR_SDA", 716 "AP_I2C_TS_SCL_1V8", 717 "AP_I2C_TS_SDA_1V8", 718 "SRCLKENA0", 719 "SRCLKENA1", 720 "AP_EC_WATCHDOG_L", 721 "PWRAP_SPI0_MI", 722 "PWRAP_SPI0_CSN", 723 "PWRAP_SPI0_MO", 724 "PWRAP_SPI0_CK", 725 "AP_RTC_CLK32K", 726 "AUD_CLK_MOSI", 727 "AUD_SYNC_MOSI", 728 "AUD_DAT_MOSI0", 729 "AUD_DAT_MOSI1", 730 "AUD_DAT_MISO0", 731 "AUD_DAT_MISO1"; 732 733 anx7625_pins: anx7625-default-pins { 734 pins-out { 735 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 736 <PINMUX_GPIO42__FUNC_GPIO42>; 737 output-low; 738 }; 739 740 pins-in { 741 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 742 input-enable; 743 bias-pull-up; 744 }; 745 }; 746 747 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 748 pins-mosi-off { 749 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 750 <PINMUX_GPIO215__FUNC_GPIO215>; 751 }; 752 }; 753 754 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 755 pins-mosi-on { 756 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 757 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 758 drive-strength = <10>; 759 }; 760 }; 761 762 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 763 pins-miso-off { 764 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 765 }; 766 }; 767 768 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 769 pins-miso-on { 770 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 771 }; 772 }; 773 774 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 775 pins-miso-off { 776 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 777 <PINMUX_GPIO219__FUNC_GPIO219>; 778 }; 779 }; 780 781 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 782 pins-miso-on { 783 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 784 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 785 drive-strength = <10>; 786 }; 787 }; 788 789 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 790 pins-miso-off { 791 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 792 }; 793 }; 794 795 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 796 pins-miso-on { 797 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 798 }; 799 }; 800 801 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 802 pins-mosi-off { 803 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 804 }; 805 }; 806 807 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 808 pins-mosi-on { 809 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 810 }; 811 }; 812 813 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 814 pins-mosi-off { 815 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 816 <PINMUX_GPIO217__FUNC_GPIO217>; 817 }; 818 }; 819 820 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 821 pins-mosi-on { 822 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 823 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 824 drive-strength = <10>; 825 }; 826 }; 827 828 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 829 pins-i2s3-off { 830 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 831 <PINMUX_GPIO33__FUNC_GPIO33>, 832 <PINMUX_GPIO35__FUNC_GPIO35>; 833 }; 834 }; 835 836 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 837 pins-i2s3-on { 838 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 839 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 840 <PINMUX_GPIO35__FUNC_I2S3_DO>; 841 }; 842 }; 843 844 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 845 pins-i2s8-off { 846 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 847 <PINMUX_GPIO11__FUNC_GPIO11>, 848 <PINMUX_GPIO12__FUNC_GPIO12>, 849 <PINMUX_GPIO13__FUNC_GPIO13>; 850 }; 851 }; 852 853 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 854 pins-i2s8-on { 855 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 856 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 857 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 858 <PINMUX_GPIO13__FUNC_I2S8_DI>; 859 }; 860 }; 861 862 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 863 pins-i2s9-off { 864 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 865 }; 866 }; 867 868 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 869 pins-i2s9-on { 870 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 871 }; 872 }; 873 874 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 875 pins-tdm-off { 876 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 877 <PINMUX_GPIO1__FUNC_GPIO1>, 878 <PINMUX_GPIO2__FUNC_GPIO2>, 879 <PINMUX_GPIO3__FUNC_GPIO3>; 880 }; 881 }; 882 883 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 884 pins-tdm-on { 885 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 886 <PINMUX_GPIO1__FUNC_TDM_BCK>, 887 <PINMUX_GPIO2__FUNC_TDM_MCK>, 888 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 889 }; 890 }; 891 892 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 893 pins-nle-mosi-off { 894 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 895 <PINMUX_GPIO198__FUNC_GPIO198>; 896 }; 897 }; 898 899 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 900 pins-nle-mosi-on { 901 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 902 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 903 }; 904 }; 905 906 cr50_int: cr50-irq-default-pins { 907 pins-gsc-ap-int-odl { 908 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 909 input-enable; 910 }; 911 }; 912 913 cros_ec_int: cros-ec-irq-default-pins { 914 pins-ec-ap-int-odl { 915 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 916 input-enable; 917 bias-pull-up; 918 }; 919 }; 920 921 i2c0_pins: i2c0-default-pins { 922 pins-bus { 923 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 924 <PINMUX_GPIO205__FUNC_SDA0>; 925 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 926 drive-strength-microamp = <1000>; 927 }; 928 }; 929 930 i2c1_pins: i2c1-default-pins { 931 pins-bus { 932 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 933 <PINMUX_GPIO119__FUNC_SDA1>; 934 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 935 drive-strength-microamp = <1000>; 936 }; 937 }; 938 939 i2c2_pins: i2c2-default-pins { 940 pins-bus { 941 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 942 <PINMUX_GPIO142__FUNC_SDA2>; 943 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 944 }; 945 }; 946 947 i2c3_pins: i2c3-default-pins { 948 pins-bus { 949 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 950 <PINMUX_GPIO161__FUNC_SDA3>; 951 bias-disable; 952 drive-strength-microamp = <1000>; 953 }; 954 }; 955 956 i2c7_pins: i2c7-default-pins { 957 pins-bus { 958 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 959 <PINMUX_GPIO125__FUNC_SDA7>; 960 bias-disable; 961 drive-strength-microamp = <1000>; 962 }; 963 }; 964 965 mmc0_default_pins: mmc0-default-pins { 966 pins-cmd-dat { 967 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 968 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 969 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 970 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 971 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 972 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 973 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 974 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 975 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 976 input-enable; 977 drive-strength = <8>; 978 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 979 }; 980 981 pins-clk { 982 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 983 drive-strength = <8>; 984 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 985 }; 986 987 pins-rst { 988 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 989 drive-strength = <8>; 990 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 991 }; 992 }; 993 994 mmc0_uhs_pins: mmc0-uhs-pins { 995 pins-cmd-dat { 996 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 997 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 998 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 999 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1000 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1001 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1002 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1003 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1004 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1005 input-enable; 1006 drive-strength = <10>; 1007 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1008 }; 1009 1010 pins-clk { 1011 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1012 drive-strength = <10>; 1013 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1014 }; 1015 1016 pins-rst { 1017 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1018 drive-strength = <8>; 1019 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1020 }; 1021 1022 pins-ds { 1023 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1024 drive-strength = <10>; 1025 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1026 }; 1027 }; 1028 1029 mmc1_default_pins: mmc1-default-pins { 1030 pins-cmd-dat { 1031 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1032 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1033 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1034 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1035 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1036 input-enable; 1037 drive-strength = <8>; 1038 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1039 }; 1040 1041 pins-clk { 1042 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1043 drive-strength = <8>; 1044 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1045 }; 1046 1047 pins-insert { 1048 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1049 input-enable; 1050 bias-pull-up; 1051 }; 1052 }; 1053 1054 mmc1_uhs_pins: mmc1-uhs-pins { 1055 pins-cmd-dat { 1056 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1057 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1058 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1059 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1060 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1061 input-enable; 1062 drive-strength = <8>; 1063 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1064 }; 1065 1066 pins-clk { 1067 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1068 input-enable; 1069 drive-strength = <8>; 1070 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1071 }; 1072 }; 1073 1074 nor_flash_pins: nor-flash-default-pins { 1075 pins-cs-io1 { 1076 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1077 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1078 input-enable; 1079 bias-pull-up; 1080 drive-strength = <10>; 1081 }; 1082 1083 pins-io0 { 1084 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1085 bias-pull-up; 1086 drive-strength = <10>; 1087 }; 1088 1089 pins-clk { 1090 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1091 input-enable; 1092 bias-pull-up; 1093 drive-strength = <10>; 1094 }; 1095 }; 1096 1097 pcie_pins: pcie-default-pins { 1098 pins-pcie-wake { 1099 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1100 bias-pull-up; 1101 }; 1102 1103 pins-pcie-pereset { 1104 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1105 }; 1106 1107 pins-pcie-clkreq { 1108 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1109 bias-pull-up; 1110 }; 1111 1112 pins-wifi-kill { 1113 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1114 output-high; 1115 }; 1116 }; 1117 1118 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1119 pins-en { 1120 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1121 output-low; 1122 }; 1123 }; 1124 1125 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1126 pins-en { 1127 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1128 output-low; 1129 }; 1130 }; 1131 1132 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1133 pins-en { 1134 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1135 output-low; 1136 }; 1137 }; 1138 1139 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1140 pins-en { 1141 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1142 output-low; 1143 }; 1144 }; 1145 1146 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1147 pins-en { 1148 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1149 output-low; 1150 }; 1151 }; 1152 1153 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1154 pins-en { 1155 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1156 output-low; 1157 }; 1158 }; 1159 1160 pp3300_wlan_pins: pp3300-wlan-pins { 1161 pins-pcie-en-pp3300-wlan { 1162 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1163 output-high; 1164 }; 1165 }; 1166 1167 pwm0_pins: pwm0-default-pins { 1168 pins-pwm { 1169 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1170 }; 1171 1172 pins-inhibit { 1173 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1174 output-high; 1175 }; 1176 }; 1177 1178 scp_pins: scp-pins { 1179 pins-vreq-vao { 1180 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1181 }; 1182 }; 1183 1184 spi1_pins: spi1-default-pins { 1185 pins-cs-mosi-clk { 1186 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1187 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1188 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1189 bias-disable; 1190 }; 1191 1192 pins-miso { 1193 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1194 bias-pull-down; 1195 }; 1196 }; 1197 1198 spi5_pins: spi5-default-pins { 1199 pins-bus { 1200 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1201 <PINMUX_GPIO37__FUNC_GPIO37>, 1202 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1203 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1204 bias-disable; 1205 }; 1206 }; 1207 1208 trackpad_pins: trackpad-default-pins { 1209 pins-int-n { 1210 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1211 input-enable; 1212 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1213 }; 1214 }; 1215 1216 touchscreen_pins: touchscreen-default-pins { 1217 pins-irq { 1218 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1219 input-enable; 1220 bias-pull-up; 1221 }; 1222 1223 pins-reset { 1224 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1225 output-high; 1226 }; 1227 1228 pins-report-sw { 1229 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1230 output-low; 1231 }; 1232 }; 1233 1234 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1235 pins-miso-off { 1236 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1237 }; 1238 }; 1239 1240 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1241 pins-miso-on { 1242 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1243 }; 1244 }; 1245 1246 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1247 pins-miso-off { 1248 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1249 }; 1250 }; 1251 1252 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1253 pins-miso-on { 1254 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1255 }; 1256 }; 1257}; 1258 1259&pmic { 1260 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1261}; 1262 1263&pwm0 { 1264 status = "okay"; 1265 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&pwm0_pins>; 1268}; 1269 1270&scp { 1271 status = "okay"; 1272 1273 firmware-name = "mediatek/mt8192/scp.img"; 1274 memory-region = <&scp_mem_reserved>; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&scp_pins>; 1277 1278 cros-ec { 1279 compatible = "google,cros-ec-rpmsg"; 1280 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1281 }; 1282}; 1283 1284&spi1 { 1285 status = "okay"; 1286 1287 mediatek,pad-select = <0>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&spi1_pins>; 1290 1291 cros_ec: ec@0 { 1292 compatible = "google,cros-ec-spi"; 1293 reg = <0>; 1294 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1295 spi-max-frequency = <3000000>; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&cros_ec_int>; 1298 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 1302 base_detection: cbas { 1303 compatible = "google,cros-cbas"; 1304 }; 1305 1306 cros_ec_pwm: pwm { 1307 compatible = "google,cros-ec-pwm"; 1308 #pwm-cells = <1>; 1309 1310 status = "disabled"; 1311 }; 1312 1313 i2c_tunnel: i2c-tunnel { 1314 compatible = "google,cros-ec-i2c-tunnel"; 1315 google,remote-bus = <0>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 }; 1319 1320 mt6360_ldo3_reg: regulator@0 { 1321 compatible = "google,cros-ec-regulator"; 1322 reg = <0>; 1323 regulator-min-microvolt = <1800000>; 1324 regulator-max-microvolt = <3300000>; 1325 }; 1326 1327 mt6360_ldo5_reg: regulator@1 { 1328 compatible = "google,cros-ec-regulator"; 1329 reg = <1>; 1330 regulator-min-microvolt = <3300000>; 1331 regulator-max-microvolt = <3300000>; 1332 }; 1333 1334 typec { 1335 compatible = "google,cros-ec-typec"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 1339 usb_c0: connector@0 { 1340 compatible = "usb-c-connector"; 1341 reg = <0>; 1342 label = "left"; 1343 power-role = "dual"; 1344 data-role = "host"; 1345 try-power-role = "source"; 1346 }; 1347 1348 usb_c1: connector@1 { 1349 compatible = "usb-c-connector"; 1350 reg = <1>; 1351 label = "right"; 1352 power-role = "dual"; 1353 data-role = "host"; 1354 try-power-role = "source"; 1355 }; 1356 }; 1357 }; 1358}; 1359 1360&spi5 { 1361 status = "okay"; 1362 1363 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1364 mediatek,pad-select = <0>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&spi5_pins>; 1367 1368 cr50@0 { 1369 compatible = "google,cr50"; 1370 reg = <0>; 1371 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1372 spi-max-frequency = <1000000>; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&cr50_int>; 1375 }; 1376}; 1377 1378&spmi { 1379 #address-cells = <2>; 1380 #size-cells = <0>; 1381 1382 mt6315_6: pmic@6 { 1383 compatible = "mediatek,mt6315-regulator"; 1384 reg = <0x6 SPMI_USID>; 1385 1386 regulators { 1387 mt6315_6_vbuck1: vbuck1 { 1388 regulator-compatible = "vbuck1"; 1389 regulator-name = "Vbcpu"; 1390 regulator-min-microvolt = <300000>; 1391 regulator-max-microvolt = <1193750>; 1392 regulator-enable-ramp-delay = <256>; 1393 regulator-allowed-modes = <0 1 2>; 1394 regulator-always-on; 1395 }; 1396 1397 mt6315_6_vbuck3: vbuck3 { 1398 regulator-compatible = "vbuck3"; 1399 regulator-name = "Vlcpu"; 1400 regulator-min-microvolt = <300000>; 1401 regulator-max-microvolt = <1193750>; 1402 regulator-enable-ramp-delay = <256>; 1403 regulator-allowed-modes = <0 1 2>; 1404 regulator-always-on; 1405 }; 1406 }; 1407 }; 1408 1409 mt6315_7: pmic@7 { 1410 compatible = "mediatek,mt6315-regulator"; 1411 reg = <0x7 SPMI_USID>; 1412 1413 regulators { 1414 mt6315_7_vbuck1: vbuck1 { 1415 regulator-compatible = "vbuck1"; 1416 regulator-name = "Vgpu"; 1417 regulator-min-microvolt = <606250>; 1418 regulator-max-microvolt = <800000>; 1419 regulator-enable-ramp-delay = <256>; 1420 regulator-allowed-modes = <0 1 2>; 1421 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1422 regulator-coupled-max-spread = <10000>; 1423 }; 1424 }; 1425 }; 1426}; 1427 1428&uart0 { 1429 status = "okay"; 1430}; 1431 1432&xhci { 1433 status = "okay"; 1434 1435 wakeup-source; 1436 vusb33-supply = <&pp3300_g>; 1437 vbus-supply = <&pp5000_a>; 1438}; 1439 1440#include <arm/cros-ec-keyboard.dtsi> 1441#include <arm/cros-ec-sbs.dtsi> 1442