1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 backlight_lcd0: backlight-lcd0 { 27 compatible = "pwm-backlight"; 28 pwms = <&pwm0 0 500000>; 29 power-supply = <&ppvar_sys>; 30 enable-gpios = <&pio 152 0>; 31 brightness-levels = <0 1023>; 32 num-interpolated-steps = <1023>; 33 default-brightness-level = <576>; 34 }; 35 36 dmic_codec: dmic-codec { 37 compatible = "dmic-codec"; 38 num-channels = <2>; 39 wakeup-delay-ms = <50>; 40 }; 41 42 pp1000_dpbrdg: regulator-1v0-dpbrdg { 43 compatible = "regulator-fixed"; 44 regulator-name = "pp1000_dpbrdg"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 47 regulator-min-microvolt = <1000000>; 48 regulator-max-microvolt = <1000000>; 49 enable-active-high; 50 regulator-boot-on; 51 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 52 vin-supply = <&mt6359_vs2_buck_reg>; 53 }; 54 55 pp1000_mipibrdg: regulator-1v0-mipibrdg { 56 compatible = "regulator-fixed"; 57 regulator-name = "pp1000_mipibrdg"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 60 regulator-min-microvolt = <1000000>; 61 regulator-max-microvolt = <1000000>; 62 enable-active-high; 63 regulator-boot-on; 64 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 65 vin-supply = <&mt6359_vs2_buck_reg>; 66 }; 67 68 pp1800_dpbrdg: regulator-1v8-dpbrdg { 69 compatible = "regulator-fixed"; 70 regulator-name = "pp1800_dpbrdg"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 73 enable-active-high; 74 regulator-boot-on; 75 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 76 vin-supply = <&mt6359_vio18_ldo_reg>; 77 }; 78 79 /* system wide LDO 1.8V power rail */ 80 pp1800_ldo_g: regulator-1v8-g { 81 compatible = "regulator-fixed"; 82 regulator-name = "pp1800_ldo_g"; 83 regulator-always-on; 84 regulator-boot-on; 85 regulator-min-microvolt = <1800000>; 86 regulator-max-microvolt = <1800000>; 87 vin-supply = <&pp3300_g>; 88 }; 89 90 pp1800_mipibrdg: regulator-1v8-mipibrdg { 91 compatible = "regulator-fixed"; 92 regulator-name = "pp1800_mipibrdg"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 95 enable-active-high; 96 regulator-boot-on; 97 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 98 vin-supply = <&mt6359_vio18_ldo_reg>; 99 }; 100 101 pp3300_dpbrdg: regulator-3v3-dpbrdg { 102 compatible = "regulator-fixed"; 103 regulator-name = "pp3300_dpbrdg"; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 106 enable-active-high; 107 regulator-boot-on; 108 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 109 vin-supply = <&pp3300_g>; 110 }; 111 112 /* system wide switching 3.3V power rail */ 113 pp3300_g: regulator-3v3-g { 114 compatible = "regulator-fixed"; 115 regulator-name = "pp3300_g"; 116 regulator-always-on; 117 regulator-boot-on; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 vin-supply = <&ppvar_sys>; 121 }; 122 123 /* system wide LDO 3.3V power rail */ 124 pp3300_ldo_z: regulator-3v3-z { 125 compatible = "regulator-fixed"; 126 regulator-name = "pp3300_ldo_z"; 127 regulator-always-on; 128 regulator-boot-on; 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 vin-supply = <&ppvar_sys>; 132 }; 133 134 pp3300_mipibrdg: regulator-3v3-mipibrdg { 135 compatible = "regulator-fixed"; 136 regulator-name = "pp3300_mipibrdg"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 139 enable-active-high; 140 regulator-boot-on; 141 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 142 vin-supply = <&pp3300_g>; 143 }; 144 145 /* separately switched 3.3V power rail */ 146 pp3300_u: regulator-3v3-u { 147 compatible = "regulator-fixed"; 148 regulator-name = "pp3300_u"; 149 regulator-always-on; 150 regulator-boot-on; 151 regulator-min-microvolt = <3300000>; 152 regulator-max-microvolt = <3300000>; 153 /* enable pin wired to GPIO controlled by EC */ 154 vin-supply = <&pp3300_g>; 155 }; 156 157 pp3300_wlan: regulator-3v3-wlan { 158 compatible = "regulator-fixed"; 159 regulator-name = "pp3300_wlan"; 160 regulator-always-on; 161 regulator-boot-on; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pp3300_wlan_pins>; 166 enable-active-high; 167 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 168 }; 169 170 /* system wide switching 5.0V power rail */ 171 pp5000_a: regulator-5v0-a { 172 compatible = "regulator-fixed"; 173 regulator-name = "pp5000_a"; 174 regulator-always-on; 175 regulator-boot-on; 176 regulator-min-microvolt = <5000000>; 177 regulator-max-microvolt = <5000000>; 178 vin-supply = <&ppvar_sys>; 179 }; 180 181 /* system wide semi-regulated power rail from battery or USB */ 182 ppvar_sys: regulator-var-sys { 183 compatible = "regulator-fixed"; 184 regulator-name = "ppvar_sys"; 185 regulator-always-on; 186 regulator-boot-on; 187 }; 188 189 reserved_memory: reserved-memory { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 scp_mem_reserved: scp@50000000 { 195 compatible = "shared-dma-pool"; 196 reg = <0 0x50000000 0 0x2900000>; 197 no-map; 198 }; 199 200 wifi_restricted_dma_region: wifi@c0000000 { 201 compatible = "restricted-dma-pool"; 202 reg = <0 0xc0000000 0 0x4000000>; 203 }; 204 }; 205 206 sound: sound { 207 mediatek,platform = <&afe>; 208 pinctrl-names = "aud_clk_mosi_off", 209 "aud_clk_mosi_on", 210 "aud_dat_mosi_off", 211 "aud_dat_mosi_on", 212 "aud_dat_miso_off", 213 "aud_dat_miso_on", 214 "vow_dat_miso_off", 215 "vow_dat_miso_on", 216 "vow_clk_miso_off", 217 "vow_clk_miso_on", 218 "aud_nle_mosi_off", 219 "aud_nle_mosi_on", 220 "aud_dat_miso2_off", 221 "aud_dat_miso2_on", 222 "aud_gpio_i2s3_off", 223 "aud_gpio_i2s3_on", 224 "aud_gpio_i2s8_off", 225 "aud_gpio_i2s8_on", 226 "aud_gpio_i2s9_off", 227 "aud_gpio_i2s9_on", 228 "aud_dat_mosi_ch34_off", 229 "aud_dat_mosi_ch34_on", 230 "aud_dat_miso_ch34_off", 231 "aud_dat_miso_ch34_on", 232 "aud_gpio_tdm_off", 233 "aud_gpio_tdm_on"; 234 pinctrl-0 = <&aud_clk_mosi_off_pins>; 235 pinctrl-1 = <&aud_clk_mosi_on_pins>; 236 pinctrl-2 = <&aud_dat_mosi_off_pins>; 237 pinctrl-3 = <&aud_dat_mosi_on_pins>; 238 pinctrl-4 = <&aud_dat_miso_off_pins>; 239 pinctrl-5 = <&aud_dat_miso_on_pins>; 240 pinctrl-6 = <&vow_dat_miso_off_pins>; 241 pinctrl-7 = <&vow_dat_miso_on_pins>; 242 pinctrl-8 = <&vow_clk_miso_off_pins>; 243 pinctrl-9 = <&vow_clk_miso_on_pins>; 244 pinctrl-10 = <&aud_nle_mosi_off_pins>; 245 pinctrl-11 = <&aud_nle_mosi_on_pins>; 246 pinctrl-12 = <&aud_dat_miso2_off_pins>; 247 pinctrl-13 = <&aud_dat_miso2_on_pins>; 248 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 249 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 250 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 251 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 252 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 253 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 254 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 255 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 256 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 257 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 258 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 259 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 260 }; 261}; 262 263&dsi0 { 264 status = "okay"; 265}; 266 267&dsi_out { 268 remote-endpoint = <&anx7625_in>; 269}; 270 271&i2c0 { 272 status = "okay"; 273 274 clock-frequency = <400000>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2c0_pins>; 277 278 touchscreen: touchscreen@10 { 279 reg = <0x10>; 280 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&touchscreen_pins>; 283 }; 284}; 285 286&i2c1 { 287 status = "okay"; 288 289 clock-frequency = <400000>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&i2c1_pins>; 292}; 293 294&i2c2 { 295 status = "okay"; 296 297 clock-frequency = <400000>; 298 clock-stretch-ns = <12600>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&i2c2_pins>; 301 302 trackpad@15 { 303 compatible = "elan,ekth3000"; 304 reg = <0x15>; 305 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&trackpad_pins>; 308 vcc-supply = <&pp3300_u>; 309 wakeup-source; 310 }; 311}; 312 313&i2c3 { 314 status = "okay"; 315 316 clock-frequency = <400000>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&i2c3_pins>; 319 320 anx_bridge: anx7625@58 { 321 compatible = "analogix,anx7625"; 322 reg = <0x58>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&anx7625_pins>; 325 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 326 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 327 vdd10-supply = <&pp1000_mipibrdg>; 328 vdd18-supply = <&pp1800_mipibrdg>; 329 vdd33-supply = <&pp3300_mipibrdg>; 330 331 ports { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 335 port@0 { 336 reg = <0>; 337 338 anx7625_in: endpoint { 339 remote-endpoint = <&dsi_out>; 340 }; 341 }; 342 343 port@1 { 344 reg = <1>; 345 346 anx7625_out: endpoint { 347 remote-endpoint = <&panel_in>; 348 }; 349 }; 350 }; 351 352 aux-bus { 353 panel: panel { 354 compatible = "edp-panel"; 355 power-supply = <&pp3300_mipibrdg>; 356 backlight = <&backlight_lcd0>; 357 358 port { 359 panel_in: endpoint { 360 remote-endpoint = <&anx7625_out>; 361 }; 362 }; 363 }; 364 }; 365 }; 366}; 367 368&i2c7 { 369 status = "okay"; 370 371 clock-frequency = <400000>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&i2c7_pins>; 374}; 375 376&mipi_tx0 { 377 status = "okay"; 378}; 379 380&mmc0 { 381 status = "okay"; 382 383 pinctrl-names = "default", "state_uhs"; 384 pinctrl-0 = <&mmc0_default_pins>; 385 pinctrl-1 = <&mmc0_uhs_pins>; 386 bus-width = <8>; 387 max-frequency = <200000000>; 388 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 389 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 390 cap-mmc-highspeed; 391 mmc-hs200-1_8v; 392 mmc-hs400-1_8v; 393 supports-cqe; 394 cap-mmc-hw-reset; 395 mmc-hs400-enhanced-strobe; 396 hs400-ds-delay = <0x12814>; 397 no-sdio; 398 no-sd; 399 non-removable; 400}; 401 402&mmc1 { 403 status = "okay"; 404 405 pinctrl-names = "default", "state_uhs"; 406 pinctrl-0 = <&mmc1_default_pins>; 407 pinctrl-1 = <&mmc1_uhs_pins>; 408 bus-width = <4>; 409 max-frequency = <200000000>; 410 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 411 vmmc-supply = <&mt6360_ldo5_reg>; 412 vqmmc-supply = <&mt6360_ldo3_reg>; 413 cap-sd-highspeed; 414 sd-uhs-sdr50; 415 sd-uhs-sdr104; 416 no-sdio; 417 no-mmc; 418}; 419 420/* for CORE */ 421&mt6359_vgpu11_buck_reg { 422 regulator-always-on; 423}; 424 425&mt6359_vgpu11_sshub_buck_reg { 426 regulator-always-on; 427 regulator-min-microvolt = <575000>; 428 regulator-max-microvolt = <575000>; 429}; 430 431&mt6359_vrf12_ldo_reg { 432 regulator-always-on; 433}; 434 435&mt6359_vufs_ldo_reg { 436 regulator-always-on; 437}; 438 439&mt6359codec { 440 mediatek,dmic-mode = <1>; /* one-wire */ 441 mediatek,mic-type-0 = <2>; /* DMIC */ 442 mediatek,mic-type-2 = <2>; /* DMIC */ 443}; 444 445&nor_flash { 446 status = "okay"; 447 448 pinctrl-names = "default"; 449 pinctrl-0 = <&nor_flash_pins>; 450 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 451 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 452 453 flash@0 { 454 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 455 reg = <0>; 456 spi-max-frequency = <52000000>; 457 spi-rx-bus-width = <2>; 458 spi-tx-bus-width = <2>; 459 }; 460}; 461 462&pcie { 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pcie_pins>; 465 466 pcie0: pcie@0,0 { 467 device_type = "pci"; 468 reg = <0x0000 0 0 0 0>; 469 num-lanes = <1>; 470 bus-range = <0x1 0x1>; 471 472 #address-cells = <3>; 473 #size-cells = <2>; 474 ranges; 475 476 wifi: wifi@0,0 { 477 reg = <0x10000 0 0 0 0x100000>, 478 <0x10000 0 0x100000 0 0x100000>; 479 memory-region = <&wifi_restricted_dma_region>; 480 }; 481 }; 482}; 483 484&pio { 485 /* 220 lines */ 486 gpio-line-names = "I2S_DP_LRCK", 487 "IS_DP_BCLK", 488 "I2S_DP_MCLK", 489 "I2S_DP_DATAOUT", 490 "SAR0_INT_ODL", 491 "EC_AP_INT_ODL", 492 "EDPBRDG_INT_ODL", 493 "DPBRDG_INT_ODL", 494 "DPBRDG_PWREN", 495 "DPBRDG_RST_ODL", 496 "I2S_HP_MCLK", 497 "I2S_HP_BCK", 498 "I2S_HP_LRCK", 499 "I2S_HP_DATAIN", 500 /* 501 * AP_FLASH_WP_L is crossystem ABI. Schematics 502 * call it AP_FLASH_WP_ODL. 503 */ 504 "AP_FLASH_WP_L", 505 "TRACKPAD_INT_ODL", 506 "EC_AP_HPD_OD", 507 "SD_CD_ODL", 508 "HP_INT_ODL_ALC", 509 "EN_PP1000_DPBRDG", 510 "AP_GPIO20", 511 "TOUCH_INT_L_1V8", 512 "UART_BT_WAKE_ODL", 513 "AP_GPIO23", 514 "AP_SPI_FLASH_CS_L", 515 "AP_SPI_FLASH_CLK", 516 "EN_PP3300_DPBRDG_DX", 517 "AP_SPI_FLASH_MOSI", 518 "AP_SPI_FLASH_MISO", 519 "I2S_HP_DATAOUT", 520 "AP_GPIO30", 521 "I2S_SPKR_MCLK", 522 "I2S_SPKR_BCLK", 523 "I2S_SPKR_LRCK", 524 "I2S_SPKR_DATAIN", 525 "I2S_SPKR_DATAOUT", 526 "AP_SPI_H1_TPM_CLK", 527 "AP_SPI_H1_TPM_CS_L", 528 "AP_SPI_H1_TPM_MISO", 529 "AP_SPI_H1_TPM_MOSI", 530 "BL_PWM", 531 "EDPBRDG_PWREN", 532 "EDPBRDG_RST_ODL", 533 "EN_PP3300_HUB", 534 "HUB_RST_L", 535 "", 536 "", 537 "", 538 "", 539 "", 540 "", 541 "SD_CLK", 542 "SD_CMD", 543 "SD_DATA3", 544 "SD_DATA0", 545 "SD_DATA2", 546 "SD_DATA1", 547 "", 548 "", 549 "", 550 "", 551 "", 552 "", 553 "PCIE_WAKE_ODL", 554 "PCIE_RST_L", 555 "PCIE_CLKREQ_ODL", 556 "", 557 "", 558 "", 559 "", 560 "", 561 "", 562 "", 563 "", 564 "", 565 "", 566 "", 567 "", 568 "", 569 "", 570 "", 571 "", 572 "", 573 "", 574 "", 575 "", 576 "", 577 "", 578 "", 579 "SPMI_SCL", 580 "SPMI_SDA", 581 "AP_GOOD", 582 "UART_DBG_TX_AP_RX", 583 "UART_AP_TX_DBG_RX", 584 "UART_AP_TX_BT_RX", 585 "UART_BT_TX_AP_RX", 586 "MIPI_DPI_D0_R", 587 "MIPI_DPI_D1_R", 588 "MIPI_DPI_D2_R", 589 "MIPI_DPI_D3_R", 590 "MIPI_DPI_D4_R", 591 "MIPI_DPI_D5_R", 592 "MIPI_DPI_D6_R", 593 "MIPI_DPI_D7_R", 594 "MIPI_DPI_D8_R", 595 "MIPI_DPI_D9_R", 596 "MIPI_DPI_D10_R", 597 "", 598 "", 599 "MIPI_DPI_DE_R", 600 "MIPI_DPI_D11_R", 601 "MIPI_DPI_VSYNC_R", 602 "MIPI_DPI_CLK_R", 603 "MIPI_DPI_HSYNC_R", 604 "PCM_BT_DATAIN", 605 "PCM_BT_SYNC", 606 "PCM_BT_DATAOUT", 607 "PCM_BT_CLK", 608 "AP_I2C_AUDIO_SCL", 609 "AP_I2C_AUDIO_SDA", 610 "SCP_I2C_SCL", 611 "SCP_I2C_SDA", 612 "AP_I2C_WLAN_SCL", 613 "AP_I2C_WLAN_SDA", 614 "AP_I2C_DPBRDG_SCL", 615 "AP_I2C_DPBRDG_SDA", 616 "EN_PP1800_DPBRDG_DX", 617 "EN_PP3300_EDP_DX", 618 "EN_PP1800_EDPBRDG_DX", 619 "EN_PP1000_EDPBRDG", 620 "SCP_JTAG0_TDO", 621 "SCP_JTAG0_TDI", 622 "SCP_JTAG0_TMS", 623 "SCP_JTAG0_TCK", 624 "SCP_JTAG0_TRSTN", 625 "EN_PP3000_VMC_PMU", 626 "EN_PP3300_DISPLAY_DX", 627 "TOUCH_RST_L_1V8", 628 "TOUCH_REPORT_DISABLE", 629 "", 630 "", 631 "AP_I2C_TRACKPAD_SCL_1V8", 632 "AP_I2C_TRACKPAD_SDA_1V8", 633 "EN_PP3300_WLAN", 634 "BT_KILL_L", 635 "WIFI_KILL_L", 636 "SET_VMC_VOLT_AT_1V8", 637 "EN_SPK", 638 "AP_WARM_RST_REQ", 639 "", 640 "", 641 "EN_PP3000_SD_S3", 642 "AP_EDP_BKLTEN", 643 "", 644 "", 645 "", 646 "AP_SPI_EC_CLK", 647 "AP_SPI_EC_CS_L", 648 "AP_SPI_EC_MISO", 649 "AP_SPI_EC_MOSI", 650 "AP_I2C_EDPBRDG_SCL", 651 "AP_I2C_EDPBRDG_SDA", 652 "MT6315_PROC_INT", 653 "MT6315_GPU_INT", 654 "UART_SERVO_TX_SCP_RX", 655 "UART_SCP_TX_SERVO_RX", 656 "BT_RTS_AP_CTS", 657 "AP_RTS_BT_CTS", 658 "UART_AP_WAKE_BT_ODL", 659 "WLAN_ALERT_ODL", 660 "EC_IN_RW_ODL", 661 "H1_AP_INT_ODL", 662 "", 663 "", 664 "", 665 "", 666 "", 667 "", 668 "", 669 "", 670 "", 671 "", 672 "", 673 "MSDC0_CMD", 674 "MSDC0_DAT0", 675 "MSDC0_DAT2", 676 "MSDC0_DAT4", 677 "MSDC0_DAT6", 678 "MSDC0_DAT1", 679 "MSDC0_DAT5", 680 "MSDC0_DAT7", 681 "MSDC0_DSL", 682 "MSDC0_CLK", 683 "MSDC0_DAT3", 684 "MSDC0_RST_L", 685 "SCP_VREQ_VAO", 686 "AUD_DAT_MOSI2", 687 "AUD_NLE_MOSI1", 688 "AUD_NLE_MOSI0", 689 "AUD_DAT_MISO2", 690 "AP_I2C_SAR_SDA", 691 "AP_I2C_SAR_SCL", 692 "AP_I2C_PWR_SCL", 693 "AP_I2C_PWR_SDA", 694 "AP_I2C_TS_SCL_1V8", 695 "AP_I2C_TS_SDA_1V8", 696 "SRCLKENA0", 697 "SRCLKENA1", 698 "AP_EC_WATCHDOG_L", 699 "PWRAP_SPI0_MI", 700 "PWRAP_SPI0_CSN", 701 "PWRAP_SPI0_MO", 702 "PWRAP_SPI0_CK", 703 "AP_RTC_CLK32K", 704 "AUD_CLK_MOSI", 705 "AUD_SYNC_MOSI", 706 "AUD_DAT_MOSI0", 707 "AUD_DAT_MOSI1", 708 "AUD_DAT_MISO0", 709 "AUD_DAT_MISO1"; 710 711 anx7625_pins: anx7625-default-pins { 712 pins-out { 713 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 714 <PINMUX_GPIO42__FUNC_GPIO42>; 715 output-low; 716 }; 717 718 pins-in { 719 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 720 input-enable; 721 bias-pull-up; 722 }; 723 }; 724 725 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 726 pins-mosi-off { 727 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 728 <PINMUX_GPIO215__FUNC_GPIO215>; 729 }; 730 }; 731 732 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 733 pins-mosi-on { 734 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 735 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 736 drive-strength = <10>; 737 }; 738 }; 739 740 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 741 pins-miso-off { 742 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 743 }; 744 }; 745 746 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 747 pins-miso-on { 748 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 749 }; 750 }; 751 752 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 753 pins-miso-off { 754 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 755 <PINMUX_GPIO219__FUNC_GPIO219>; 756 }; 757 }; 758 759 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 760 pins-miso-on { 761 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 762 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 763 drive-strength = <10>; 764 }; 765 }; 766 767 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 768 pins-miso-off { 769 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 770 }; 771 }; 772 773 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 774 pins-miso-on { 775 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 776 }; 777 }; 778 779 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 780 pins-mosi-off { 781 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 782 }; 783 }; 784 785 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 786 pins-mosi-on { 787 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 788 }; 789 }; 790 791 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 792 pins-mosi-off { 793 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 794 <PINMUX_GPIO217__FUNC_GPIO217>; 795 }; 796 }; 797 798 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 799 pins-mosi-on { 800 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 801 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 802 drive-strength = <10>; 803 }; 804 }; 805 806 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 807 pins-i2s3-off { 808 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 809 <PINMUX_GPIO33__FUNC_GPIO33>, 810 <PINMUX_GPIO35__FUNC_GPIO35>; 811 }; 812 }; 813 814 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 815 pins-i2s3-on { 816 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 817 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 818 <PINMUX_GPIO35__FUNC_I2S3_DO>; 819 }; 820 }; 821 822 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 823 pins-i2s8-off { 824 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 825 <PINMUX_GPIO11__FUNC_GPIO11>, 826 <PINMUX_GPIO12__FUNC_GPIO12>, 827 <PINMUX_GPIO13__FUNC_GPIO13>; 828 }; 829 }; 830 831 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 832 pins-i2s8-on { 833 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 834 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 835 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 836 <PINMUX_GPIO13__FUNC_I2S8_DI>; 837 }; 838 }; 839 840 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 841 pins-i2s9-off { 842 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 843 }; 844 }; 845 846 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 847 pins-i2s9-on { 848 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 849 }; 850 }; 851 852 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 853 pins-tdm-off { 854 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 855 <PINMUX_GPIO1__FUNC_GPIO1>, 856 <PINMUX_GPIO2__FUNC_GPIO2>, 857 <PINMUX_GPIO3__FUNC_GPIO3>; 858 }; 859 }; 860 861 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 862 pins-tdm-on { 863 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 864 <PINMUX_GPIO1__FUNC_TDM_BCK>, 865 <PINMUX_GPIO2__FUNC_TDM_MCK>, 866 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 867 }; 868 }; 869 870 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 871 pins-nle-mosi-off { 872 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 873 <PINMUX_GPIO198__FUNC_GPIO198>; 874 }; 875 }; 876 877 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 878 pins-nle-mosi-on { 879 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 880 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 881 }; 882 }; 883 884 cr50_int: cr50-irq-default-pins { 885 pins-gsc-ap-int-odl { 886 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 887 input-enable; 888 }; 889 }; 890 891 cros_ec_int: cros-ec-irq-default-pins { 892 pins-ec-ap-int-odl { 893 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 894 input-enable; 895 bias-pull-up; 896 }; 897 }; 898 899 i2c0_pins: i2c0-default-pins { 900 pins-bus { 901 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 902 <PINMUX_GPIO205__FUNC_SDA0>; 903 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 904 drive-strength-microamp = <1000>; 905 }; 906 }; 907 908 i2c1_pins: i2c1-default-pins { 909 pins-bus { 910 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 911 <PINMUX_GPIO119__FUNC_SDA1>; 912 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 913 drive-strength-microamp = <1000>; 914 }; 915 }; 916 917 i2c2_pins: i2c2-default-pins { 918 pins-bus { 919 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 920 <PINMUX_GPIO142__FUNC_SDA2>; 921 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 922 }; 923 }; 924 925 i2c3_pins: i2c3-default-pins { 926 pins-bus { 927 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 928 <PINMUX_GPIO161__FUNC_SDA3>; 929 bias-disable; 930 drive-strength-microamp = <1000>; 931 }; 932 }; 933 934 i2c7_pins: i2c7-default-pins { 935 pins-bus { 936 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 937 <PINMUX_GPIO125__FUNC_SDA7>; 938 bias-disable; 939 drive-strength-microamp = <1000>; 940 }; 941 }; 942 943 mmc0_default_pins: mmc0-default-pins { 944 pins-cmd-dat { 945 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 946 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 947 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 948 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 949 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 950 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 951 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 952 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 953 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 954 input-enable; 955 drive-strength = <8>; 956 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 957 }; 958 959 pins-clk { 960 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 961 drive-strength = <8>; 962 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 963 }; 964 965 pins-rst { 966 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 967 drive-strength = <8>; 968 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 969 }; 970 }; 971 972 mmc0_uhs_pins: mmc0-uhs-pins { 973 pins-cmd-dat { 974 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 975 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 976 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 977 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 978 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 979 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 980 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 981 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 982 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 983 input-enable; 984 drive-strength = <10>; 985 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 986 }; 987 988 pins-clk { 989 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 990 drive-strength = <10>; 991 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 992 }; 993 994 pins-rst { 995 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 996 drive-strength = <8>; 997 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 998 }; 999 1000 pins-ds { 1001 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1002 drive-strength = <10>; 1003 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1004 }; 1005 }; 1006 1007 mmc1_default_pins: mmc1-default-pins { 1008 pins-cmd-dat { 1009 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1010 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1011 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1012 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1013 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1014 input-enable; 1015 drive-strength = <8>; 1016 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1017 }; 1018 1019 pins-clk { 1020 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1021 drive-strength = <8>; 1022 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1023 }; 1024 1025 pins-insert { 1026 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1027 input-enable; 1028 bias-pull-up; 1029 }; 1030 }; 1031 1032 mmc1_uhs_pins: mmc1-uhs-pins { 1033 pins-cmd-dat { 1034 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1035 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1036 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1037 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1038 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1039 input-enable; 1040 drive-strength = <8>; 1041 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1042 }; 1043 1044 pins-clk { 1045 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1046 input-enable; 1047 drive-strength = <8>; 1048 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1049 }; 1050 }; 1051 1052 nor_flash_pins: nor-flash-default-pins { 1053 pins-cs-io1 { 1054 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1055 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1056 input-enable; 1057 bias-pull-up; 1058 drive-strength = <10>; 1059 }; 1060 1061 pins-io0 { 1062 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1063 bias-pull-up; 1064 drive-strength = <10>; 1065 }; 1066 1067 pins-clk { 1068 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1069 input-enable; 1070 bias-pull-up; 1071 drive-strength = <10>; 1072 }; 1073 }; 1074 1075 pcie_pins: pcie-default-pins { 1076 pins-pcie-wake { 1077 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1078 bias-pull-up; 1079 }; 1080 1081 pins-pcie-pereset { 1082 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1083 }; 1084 1085 pins-pcie-clkreq { 1086 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1087 bias-pull-up; 1088 }; 1089 1090 pins-wifi-kill { 1091 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1092 output-high; 1093 }; 1094 }; 1095 1096 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1097 pins-en { 1098 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1099 output-low; 1100 }; 1101 }; 1102 1103 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1104 pins-en { 1105 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1106 output-low; 1107 }; 1108 }; 1109 1110 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1111 pins-en { 1112 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1113 output-low; 1114 }; 1115 }; 1116 1117 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1118 pins-en { 1119 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1120 output-low; 1121 }; 1122 }; 1123 1124 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1125 pins-en { 1126 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1127 output-low; 1128 }; 1129 }; 1130 1131 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1132 pins-en { 1133 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1134 output-low; 1135 }; 1136 }; 1137 1138 pp3300_wlan_pins: pp3300-wlan-pins { 1139 pins-pcie-en-pp3300-wlan { 1140 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1141 output-high; 1142 }; 1143 }; 1144 1145 pwm0_pins: pwm0-default-pins { 1146 pins-pwm { 1147 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1148 }; 1149 1150 pins-inhibit { 1151 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1152 output-high; 1153 }; 1154 }; 1155 1156 scp_pins: scp-pins { 1157 pins-vreq-vao { 1158 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1159 }; 1160 }; 1161 1162 spi1_pins: spi1-default-pins { 1163 pins-cs-mosi-clk { 1164 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1165 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1166 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1167 bias-disable; 1168 }; 1169 1170 pins-miso { 1171 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1172 bias-pull-down; 1173 }; 1174 }; 1175 1176 spi5_pins: spi5-default-pins { 1177 pins-bus { 1178 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1179 <PINMUX_GPIO37__FUNC_GPIO37>, 1180 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1181 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1182 bias-disable; 1183 }; 1184 }; 1185 1186 trackpad_pins: trackpad-default-pins { 1187 pins-int-n { 1188 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1189 input-enable; 1190 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1191 }; 1192 }; 1193 1194 touchscreen_pins: touchscreen-default-pins { 1195 pins-irq { 1196 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1197 input-enable; 1198 bias-pull-up; 1199 }; 1200 1201 pins-reset { 1202 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1203 output-high; 1204 }; 1205 1206 pins-report-sw { 1207 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1208 output-low; 1209 }; 1210 }; 1211 1212 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1213 pins-miso-off { 1214 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1215 }; 1216 }; 1217 1218 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1219 pins-miso-on { 1220 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1221 }; 1222 }; 1223 1224 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1225 pins-miso-off { 1226 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1227 }; 1228 }; 1229 1230 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1231 pins-miso-on { 1232 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1233 }; 1234 }; 1235}; 1236 1237&pmic { 1238 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1239}; 1240 1241&pwm0 { 1242 status = "okay"; 1243 1244 pinctrl-names = "default"; 1245 pinctrl-0 = <&pwm0_pins>; 1246}; 1247 1248&scp { 1249 status = "okay"; 1250 1251 firmware-name = "mediatek/mt8192/scp.img"; 1252 memory-region = <&scp_mem_reserved>; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&scp_pins>; 1255 1256 cros-ec { 1257 compatible = "google,cros-ec-rpmsg"; 1258 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1259 }; 1260}; 1261 1262&spi1 { 1263 status = "okay"; 1264 1265 mediatek,pad-select = <0>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&spi1_pins>; 1268 1269 cros_ec: ec@0 { 1270 compatible = "google,cros-ec-spi"; 1271 reg = <0>; 1272 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1273 spi-max-frequency = <3000000>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&cros_ec_int>; 1276 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 1280 base_detection: cbas { 1281 compatible = "google,cros-cbas"; 1282 }; 1283 1284 cros_ec_pwm: pwm { 1285 compatible = "google,cros-ec-pwm"; 1286 #pwm-cells = <1>; 1287 1288 status = "disabled"; 1289 }; 1290 1291 i2c_tunnel: i2c-tunnel { 1292 compatible = "google,cros-ec-i2c-tunnel"; 1293 google,remote-bus = <0>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 }; 1297 1298 mt6360_ldo3_reg: regulator@0 { 1299 compatible = "google,cros-ec-regulator"; 1300 reg = <0>; 1301 regulator-min-microvolt = <1800000>; 1302 regulator-max-microvolt = <3300000>; 1303 }; 1304 1305 mt6360_ldo5_reg: regulator@1 { 1306 compatible = "google,cros-ec-regulator"; 1307 reg = <1>; 1308 regulator-min-microvolt = <3300000>; 1309 regulator-max-microvolt = <3300000>; 1310 }; 1311 1312 typec { 1313 compatible = "google,cros-ec-typec"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 1317 usb_c0: connector@0 { 1318 compatible = "usb-c-connector"; 1319 reg = <0>; 1320 label = "left"; 1321 power-role = "dual"; 1322 data-role = "host"; 1323 try-power-role = "source"; 1324 }; 1325 1326 usb_c1: connector@1 { 1327 compatible = "usb-c-connector"; 1328 reg = <1>; 1329 label = "right"; 1330 power-role = "dual"; 1331 data-role = "host"; 1332 try-power-role = "source"; 1333 }; 1334 }; 1335 }; 1336}; 1337 1338&spi5 { 1339 status = "okay"; 1340 1341 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1342 mediatek,pad-select = <0>; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&spi5_pins>; 1345 1346 cr50@0 { 1347 compatible = "google,cr50"; 1348 reg = <0>; 1349 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1350 spi-max-frequency = <1000000>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&cr50_int>; 1353 }; 1354}; 1355 1356&spmi { 1357 #address-cells = <2>; 1358 #size-cells = <0>; 1359 1360 mt6315_6: pmic@6 { 1361 compatible = "mediatek,mt6315-regulator"; 1362 reg = <0x6 SPMI_USID>; 1363 1364 regulators { 1365 mt6315_6_vbuck1: vbuck1 { 1366 regulator-compatible = "vbuck1"; 1367 regulator-name = "Vbcpu"; 1368 regulator-min-microvolt = <300000>; 1369 regulator-max-microvolt = <1193750>; 1370 regulator-enable-ramp-delay = <256>; 1371 regulator-allowed-modes = <0 1 2>; 1372 regulator-always-on; 1373 }; 1374 1375 mt6315_6_vbuck3: vbuck3 { 1376 regulator-compatible = "vbuck3"; 1377 regulator-name = "Vlcpu"; 1378 regulator-min-microvolt = <300000>; 1379 regulator-max-microvolt = <1193750>; 1380 regulator-enable-ramp-delay = <256>; 1381 regulator-allowed-modes = <0 1 2>; 1382 regulator-always-on; 1383 }; 1384 }; 1385 }; 1386 1387 mt6315_7: pmic@7 { 1388 compatible = "mediatek,mt6315-regulator"; 1389 reg = <0x7 SPMI_USID>; 1390 1391 regulators { 1392 mt6315_7_vbuck1: vbuck1 { 1393 regulator-compatible = "vbuck1"; 1394 regulator-name = "Vgpu"; 1395 regulator-min-microvolt = <606250>; 1396 regulator-max-microvolt = <1193750>; 1397 regulator-enable-ramp-delay = <256>; 1398 regulator-allowed-modes = <0 1 2>; 1399 }; 1400 }; 1401 }; 1402}; 1403 1404&uart0 { 1405 status = "okay"; 1406}; 1407 1408&xhci { 1409 status = "okay"; 1410 1411 wakeup-source; 1412 vusb33-supply = <&pp3300_g>; 1413 vbus-supply = <&pp5000_a>; 1414}; 1415 1416#include <arm/cros-ec-keyboard.dtsi> 1417#include <arm/cros-ec-sbs.dtsi> 1418