1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 /* system wide LDO 1.8V power rail */ 27 pp1800_ldo_g: regulator-1v8-g { 28 compatible = "regulator-fixed"; 29 regulator-name = "pp1800_ldo_g"; 30 regulator-always-on; 31 regulator-boot-on; 32 regulator-min-microvolt = <1800000>; 33 regulator-max-microvolt = <1800000>; 34 vin-supply = <&pp3300_g>; 35 }; 36 37 /* system wide switching 3.3V power rail */ 38 pp3300_g: regulator-3v3-g { 39 compatible = "regulator-fixed"; 40 regulator-name = "pp3300_g"; 41 regulator-always-on; 42 regulator-boot-on; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 vin-supply = <&ppvar_sys>; 46 }; 47 48 /* system wide LDO 3.3V power rail */ 49 pp3300_ldo_z: regulator-3v3-z { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp3300_ldo_z"; 52 regulator-always-on; 53 regulator-boot-on; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 /* separately switched 3.3V power rail */ 60 pp3300_u: regulator-3v3-u { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp3300_u"; 63 regulator-always-on; 64 regulator-boot-on; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 /* enable pin wired to GPIO controlled by EC */ 68 vin-supply = <&pp3300_g>; 69 }; 70 71 pp3300_wlan: regulator-3v3-wlan { 72 compatible = "regulator-fixed"; 73 regulator-name = "pp3300_wlan"; 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp3300_wlan_pins>; 80 enable-active-high; 81 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 82 }; 83 84 /* system wide switching 5.0V power rail */ 85 pp5000_a: regulator-5v0-a { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp5000_a"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>; 92 vin-supply = <&ppvar_sys>; 93 }; 94 95 /* system wide semi-regulated power rail from battery or USB */ 96 ppvar_sys: regulator-var-sys { 97 compatible = "regulator-fixed"; 98 regulator-name = "ppvar_sys"; 99 regulator-always-on; 100 regulator-boot-on; 101 }; 102 103 reserved_memory: reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 wifi_restricted_dma_region: wifi@c0000000 { 109 compatible = "restricted-dma-pool"; 110 reg = <0 0xc0000000 0 0x4000000>; 111 }; 112 }; 113}; 114 115&i2c0 { 116 status = "okay"; 117 118 clock-frequency = <400000>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&i2c0_pins>; 121 122 touchscreen: touchscreen@10 { 123 reg = <0x10>; 124 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&touchscreen_pins>; 127 }; 128}; 129 130&i2c1 { 131 status = "okay"; 132 133 clock-frequency = <400000>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&i2c1_pins>; 136}; 137 138&i2c2 { 139 status = "okay"; 140 141 clock-frequency = <400000>; 142 clock-stretch-ns = <12600>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&i2c2_pins>; 145 146 trackpad@15 { 147 compatible = "elan,ekth3000"; 148 reg = <0x15>; 149 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&trackpad_pins>; 152 vcc-supply = <&pp3300_u>; 153 wakeup-source; 154 }; 155}; 156 157&i2c3 { 158 status = "okay"; 159 160 clock-frequency = <400000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&i2c3_pins>; 163}; 164 165&i2c7 { 166 status = "okay"; 167 168 clock-frequency = <400000>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&i2c7_pins>; 171}; 172 173/* for CORE */ 174&mt6359_vgpu11_buck_reg { 175 regulator-always-on; 176}; 177 178&mt6359_vgpu11_sshub_buck_reg { 179 regulator-always-on; 180 regulator-min-microvolt = <575000>; 181 regulator-max-microvolt = <575000>; 182}; 183 184&mt6359_vrf12_ldo_reg { 185 regulator-always-on; 186}; 187 188&mt6359_vufs_ldo_reg { 189 regulator-always-on; 190}; 191 192&mt6359codec { 193 mediatek,dmic-mode = <1>; /* one-wire */ 194 mediatek,mic-type-0 = <2>; /* DMIC */ 195 mediatek,mic-type-2 = <2>; /* DMIC */ 196}; 197 198&pcie { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pcie_pins>; 201 202 pcie0: pcie@0,0 { 203 device_type = "pci"; 204 reg = <0x0000 0 0 0 0>; 205 num-lanes = <1>; 206 bus-range = <0x1 0x1>; 207 208 #address-cells = <3>; 209 #size-cells = <2>; 210 ranges; 211 212 wifi: wifi@0,0 { 213 reg = <0x10000 0 0 0 0x100000>, 214 <0x10000 0 0x100000 0 0x100000>; 215 memory-region = <&wifi_restricted_dma_region>; 216 }; 217 }; 218}; 219 220&pio { 221 /* 220 lines */ 222 gpio-line-names = "I2S_DP_LRCK", 223 "IS_DP_BCLK", 224 "I2S_DP_MCLK", 225 "I2S_DP_DATAOUT", 226 "SAR0_INT_ODL", 227 "EC_AP_INT_ODL", 228 "EDPBRDG_INT_ODL", 229 "DPBRDG_INT_ODL", 230 "DPBRDG_PWREN", 231 "DPBRDG_RST_ODL", 232 "I2S_HP_MCLK", 233 "I2S_HP_BCK", 234 "I2S_HP_LRCK", 235 "I2S_HP_DATAIN", 236 /* 237 * AP_FLASH_WP_L is crossystem ABI. Schematics 238 * call it AP_FLASH_WP_ODL. 239 */ 240 "AP_FLASH_WP_L", 241 "TRACKPAD_INT_ODL", 242 "EC_AP_HPD_OD", 243 "SD_CD_ODL", 244 "HP_INT_ODL_ALC", 245 "EN_PP1000_DPBRDG", 246 "AP_GPIO20", 247 "TOUCH_INT_L_1V8", 248 "UART_BT_WAKE_ODL", 249 "AP_GPIO23", 250 "AP_SPI_FLASH_CS_L", 251 "AP_SPI_FLASH_CLK", 252 "EN_PP3300_DPBRDG_DX", 253 "AP_SPI_FLASH_MOSI", 254 "AP_SPI_FLASH_MISO", 255 "I2S_HP_DATAOUT", 256 "AP_GPIO30", 257 "I2S_SPKR_MCLK", 258 "I2S_SPKR_BCLK", 259 "I2S_SPKR_LRCK", 260 "I2S_SPKR_DATAIN", 261 "I2S_SPKR_DATAOUT", 262 "AP_SPI_H1_TPM_CLK", 263 "AP_SPI_H1_TPM_CS_L", 264 "AP_SPI_H1_TPM_MISO", 265 "AP_SPI_H1_TPM_MOSI", 266 "BL_PWM", 267 "EDPBRDG_PWREN", 268 "EDPBRDG_RST_ODL", 269 "EN_PP3300_HUB", 270 "HUB_RST_L", 271 "", 272 "", 273 "", 274 "", 275 "", 276 "", 277 "SD_CLK", 278 "SD_CMD", 279 "SD_DATA3", 280 "SD_DATA0", 281 "SD_DATA2", 282 "SD_DATA1", 283 "", 284 "", 285 "", 286 "", 287 "", 288 "", 289 "PCIE_WAKE_ODL", 290 "PCIE_RST_L", 291 "PCIE_CLKREQ_ODL", 292 "", 293 "", 294 "", 295 "", 296 "", 297 "", 298 "", 299 "", 300 "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "", 310 "", 311 "", 312 "", 313 "", 314 "", 315 "SPMI_SCL", 316 "SPMI_SDA", 317 "AP_GOOD", 318 "UART_DBG_TX_AP_RX", 319 "UART_AP_TX_DBG_RX", 320 "UART_AP_TX_BT_RX", 321 "UART_BT_TX_AP_RX", 322 "MIPI_DPI_D0_R", 323 "MIPI_DPI_D1_R", 324 "MIPI_DPI_D2_R", 325 "MIPI_DPI_D3_R", 326 "MIPI_DPI_D4_R", 327 "MIPI_DPI_D5_R", 328 "MIPI_DPI_D6_R", 329 "MIPI_DPI_D7_R", 330 "MIPI_DPI_D8_R", 331 "MIPI_DPI_D9_R", 332 "MIPI_DPI_D10_R", 333 "", 334 "", 335 "MIPI_DPI_DE_R", 336 "MIPI_DPI_D11_R", 337 "MIPI_DPI_VSYNC_R", 338 "MIPI_DPI_CLK_R", 339 "MIPI_DPI_HSYNC_R", 340 "PCM_BT_DATAIN", 341 "PCM_BT_SYNC", 342 "PCM_BT_DATAOUT", 343 "PCM_BT_CLK", 344 "AP_I2C_AUDIO_SCL", 345 "AP_I2C_AUDIO_SDA", 346 "SCP_I2C_SCL", 347 "SCP_I2C_SDA", 348 "AP_I2C_WLAN_SCL", 349 "AP_I2C_WLAN_SDA", 350 "AP_I2C_DPBRDG_SCL", 351 "AP_I2C_DPBRDG_SDA", 352 "EN_PP1800_DPBRDG_DX", 353 "EN_PP3300_EDP_DX", 354 "EN_PP1800_EDPBRDG_DX", 355 "EN_PP1000_EDPBRDG", 356 "SCP_JTAG0_TDO", 357 "SCP_JTAG0_TDI", 358 "SCP_JTAG0_TMS", 359 "SCP_JTAG0_TCK", 360 "SCP_JTAG0_TRSTN", 361 "EN_PP3000_VMC_PMU", 362 "EN_PP3300_DISPLAY_DX", 363 "TOUCH_RST_L_1V8", 364 "TOUCH_REPORT_DISABLE", 365 "", 366 "", 367 "AP_I2C_TRACKPAD_SCL_1V8", 368 "AP_I2C_TRACKPAD_SDA_1V8", 369 "EN_PP3300_WLAN", 370 "BT_KILL_L", 371 "WIFI_KILL_L", 372 "SET_VMC_VOLT_AT_1V8", 373 "EN_SPK", 374 "AP_WARM_RST_REQ", 375 "", 376 "", 377 "EN_PP3000_SD_S3", 378 "AP_EDP_BKLTEN", 379 "", 380 "", 381 "", 382 "AP_SPI_EC_CLK", 383 "AP_SPI_EC_CS_L", 384 "AP_SPI_EC_MISO", 385 "AP_SPI_EC_MOSI", 386 "AP_I2C_EDPBRDG_SCL", 387 "AP_I2C_EDPBRDG_SDA", 388 "MT6315_PROC_INT", 389 "MT6315_GPU_INT", 390 "UART_SERVO_TX_SCP_RX", 391 "UART_SCP_TX_SERVO_RX", 392 "BT_RTS_AP_CTS", 393 "AP_RTS_BT_CTS", 394 "UART_AP_WAKE_BT_ODL", 395 "WLAN_ALERT_ODL", 396 "EC_IN_RW_ODL", 397 "H1_AP_INT_ODL", 398 "", 399 "", 400 "", 401 "", 402 "", 403 "", 404 "", 405 "", 406 "", 407 "", 408 "", 409 "MSDC0_CMD", 410 "MSDC0_DAT0", 411 "MSDC0_DAT2", 412 "MSDC0_DAT4", 413 "MSDC0_DAT6", 414 "MSDC0_DAT1", 415 "MSDC0_DAT5", 416 "MSDC0_DAT7", 417 "MSDC0_DSL", 418 "MSDC0_CLK", 419 "MSDC0_DAT3", 420 "MSDC0_RST_L", 421 "SCP_VREQ_VAO", 422 "AUD_DAT_MOSI2", 423 "AUD_NLE_MOSI1", 424 "AUD_NLE_MOSI0", 425 "AUD_DAT_MISO2", 426 "AP_I2C_SAR_SDA", 427 "AP_I2C_SAR_SCL", 428 "AP_I2C_PWR_SCL", 429 "AP_I2C_PWR_SDA", 430 "AP_I2C_TS_SCL_1V8", 431 "AP_I2C_TS_SDA_1V8", 432 "SRCLKENA0", 433 "SRCLKENA1", 434 "AP_EC_WATCHDOG_L", 435 "PWRAP_SPI0_MI", 436 "PWRAP_SPI0_CSN", 437 "PWRAP_SPI0_MO", 438 "PWRAP_SPI0_CK", 439 "AP_RTC_CLK32K", 440 "AUD_CLK_MOSI", 441 "AUD_SYNC_MOSI", 442 "AUD_DAT_MOSI0", 443 "AUD_DAT_MOSI1", 444 "AUD_DAT_MISO0", 445 "AUD_DAT_MISO1"; 446 447 cr50_int: cr50-irq-default-pins { 448 pins-gsc-ap-int-odl { 449 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 450 input-enable; 451 }; 452 }; 453 454 cros_ec_int: cros-ec-irq-default-pins { 455 pins-ec-ap-int-odl { 456 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 457 input-enable; 458 bias-pull-up; 459 }; 460 }; 461 462 i2c0_pins: i2c0-default-pins { 463 pins-bus { 464 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 465 <PINMUX_GPIO205__FUNC_SDA0>; 466 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 467 drive-strength-microamp = <1000>; 468 }; 469 }; 470 471 i2c1_pins: i2c1-default-pins { 472 pins-bus { 473 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 474 <PINMUX_GPIO119__FUNC_SDA1>; 475 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 476 drive-strength-microamp = <1000>; 477 }; 478 }; 479 480 i2c2_pins: i2c2-default-pins { 481 pins-bus { 482 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 483 <PINMUX_GPIO142__FUNC_SDA2>; 484 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 485 }; 486 }; 487 488 i2c3_pins: i2c3-default-pins { 489 pins-bus { 490 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 491 <PINMUX_GPIO161__FUNC_SDA3>; 492 bias-disable; 493 drive-strength-microamp = <1000>; 494 }; 495 }; 496 497 i2c7_pins: i2c7-default-pins { 498 pins-bus { 499 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 500 <PINMUX_GPIO125__FUNC_SDA7>; 501 bias-disable; 502 drive-strength-microamp = <1000>; 503 }; 504 }; 505 506 pcie_pins: pcie-default-pins { 507 pins-pcie-wake { 508 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 509 bias-pull-up; 510 }; 511 512 pins-pcie-pereset { 513 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 514 }; 515 516 pins-pcie-clkreq { 517 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 518 bias-pull-up; 519 }; 520 521 pins-wifi-kill { 522 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 523 output-high; 524 }; 525 }; 526 527 pp3300_wlan_pins: pp3300-wlan-pins { 528 pins-pcie-en-pp3300-wlan { 529 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 530 output-high; 531 }; 532 }; 533 534 spi1_pins: spi1-default-pins { 535 pins-cs-mosi-clk { 536 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 537 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 538 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 539 bias-disable; 540 }; 541 542 pins-miso { 543 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 544 bias-pull-down; 545 }; 546 }; 547 548 spi5_pins: spi5-default-pins { 549 pins-bus { 550 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 551 <PINMUX_GPIO37__FUNC_GPIO37>, 552 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 553 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 554 bias-disable; 555 }; 556 }; 557 558 trackpad_pins: trackpad-default-pins { 559 pins-int-n { 560 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 561 input-enable; 562 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 563 }; 564 }; 565 566 touchscreen_pins: touchscreen-default-pins { 567 pins-irq { 568 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 569 input-enable; 570 bias-pull-up; 571 }; 572 573 pins-reset { 574 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 575 output-high; 576 }; 577 578 pins-report-sw { 579 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 580 output-low; 581 }; 582 }; 583}; 584 585&pmic { 586 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 587}; 588 589&spi1 { 590 status = "okay"; 591 592 mediatek,pad-select = <0>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&spi1_pins>; 595 596 cros_ec: ec@0 { 597 compatible = "google,cros-ec-spi"; 598 reg = <0>; 599 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 600 spi-max-frequency = <3000000>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&cros_ec_int>; 603 604 #address-cells = <1>; 605 #size-cells = <0>; 606 607 base_detection: cbas { 608 compatible = "google,cros-cbas"; 609 }; 610 611 cros_ec_pwm: pwm { 612 compatible = "google,cros-ec-pwm"; 613 #pwm-cells = <1>; 614 615 status = "disabled"; 616 }; 617 618 i2c_tunnel: i2c-tunnel { 619 compatible = "google,cros-ec-i2c-tunnel"; 620 google,remote-bus = <0>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 }; 624 625 mt6360_ldo3_reg: regulator@0 { 626 compatible = "google,cros-ec-regulator"; 627 reg = <0>; 628 regulator-min-microvolt = <1800000>; 629 regulator-max-microvolt = <3300000>; 630 }; 631 632 mt6360_ldo5_reg: regulator@1 { 633 compatible = "google,cros-ec-regulator"; 634 reg = <1>; 635 regulator-min-microvolt = <3300000>; 636 regulator-max-microvolt = <3300000>; 637 }; 638 639 typec { 640 compatible = "google,cros-ec-typec"; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 usb_c0: connector@0 { 645 compatible = "usb-c-connector"; 646 reg = <0>; 647 label = "left"; 648 power-role = "dual"; 649 data-role = "host"; 650 try-power-role = "source"; 651 }; 652 653 usb_c1: connector@1 { 654 compatible = "usb-c-connector"; 655 reg = <1>; 656 label = "right"; 657 power-role = "dual"; 658 data-role = "host"; 659 try-power-role = "source"; 660 }; 661 }; 662 }; 663}; 664 665&spi5 { 666 status = "okay"; 667 668 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 669 mediatek,pad-select = <0>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&spi5_pins>; 672 673 cr50@0 { 674 compatible = "google,cr50"; 675 reg = <0>; 676 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 677 spi-max-frequency = <1000000>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&cr50_int>; 680 }; 681}; 682 683&spmi { 684 #address-cells = <2>; 685 #size-cells = <0>; 686 687 mt6315_6: pmic@6 { 688 compatible = "mediatek,mt6315-regulator"; 689 reg = <0x6 SPMI_USID>; 690 691 regulators { 692 mt6315_6_vbuck1: vbuck1 { 693 regulator-compatible = "vbuck1"; 694 regulator-name = "Vbcpu"; 695 regulator-min-microvolt = <300000>; 696 regulator-max-microvolt = <1193750>; 697 regulator-enable-ramp-delay = <256>; 698 regulator-allowed-modes = <0 1 2>; 699 regulator-always-on; 700 }; 701 702 mt6315_6_vbuck3: vbuck3 { 703 regulator-compatible = "vbuck3"; 704 regulator-name = "Vlcpu"; 705 regulator-min-microvolt = <300000>; 706 regulator-max-microvolt = <1193750>; 707 regulator-enable-ramp-delay = <256>; 708 regulator-allowed-modes = <0 1 2>; 709 regulator-always-on; 710 }; 711 }; 712 }; 713 714 mt6315_7: pmic@7 { 715 compatible = "mediatek,mt6315-regulator"; 716 reg = <0x7 SPMI_USID>; 717 718 regulators { 719 mt6315_7_vbuck1: vbuck1 { 720 regulator-compatible = "vbuck1"; 721 regulator-name = "Vgpu"; 722 regulator-min-microvolt = <606250>; 723 regulator-max-microvolt = <1193750>; 724 regulator-enable-ramp-delay = <256>; 725 regulator-allowed-modes = <0 1 2>; 726 }; 727 }; 728 }; 729}; 730 731&uart0 { 732 status = "okay"; 733}; 734 735&xhci { 736 status = "okay"; 737 738 wakeup-source; 739 vusb33-supply = <&pp3300_g>; 740 vbus-supply = <&pp5000_a>; 741}; 742 743#include <arm/cros-ec-keyboard.dtsi> 744#include <arm/cros-ec-sbs.dtsi> 745