1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6/dts-v1/;
7#include "mt8192.dtsi"
8
9/ {
10	aliases {
11		serial0 = &uart0;
12	};
13
14	chosen {
15		stdout-path = "serial0:115200n8";
16	};
17
18	memory@40000000 {
19		device_type = "memory";
20		reg = <0 0x40000000 0 0x80000000>;
21	};
22
23	/* system wide LDO 1.8V power rail */
24	pp1800_ldo_g: regulator-1v8-g {
25		compatible = "regulator-fixed";
26		regulator-name = "pp1800_ldo_g";
27		regulator-always-on;
28		regulator-boot-on;
29		regulator-min-microvolt = <1800000>;
30		regulator-max-microvolt = <1800000>;
31		vin-supply = <&pp3300_g>;
32	};
33
34	/* system wide switching 3.3V power rail */
35	pp3300_g: regulator-3v3-g {
36		compatible = "regulator-fixed";
37		regulator-name = "pp3300_g";
38		regulator-always-on;
39		regulator-boot-on;
40		regulator-min-microvolt = <3300000>;
41		regulator-max-microvolt = <3300000>;
42		vin-supply = <&ppvar_sys>;
43	};
44
45	/* system wide LDO 3.3V power rail */
46	pp3300_ldo_z: regulator-3v3-z {
47		compatible = "regulator-fixed";
48		regulator-name = "pp3300_ldo_z";
49		regulator-always-on;
50		regulator-boot-on;
51		regulator-min-microvolt = <3300000>;
52		regulator-max-microvolt = <3300000>;
53		vin-supply = <&ppvar_sys>;
54	};
55
56	/* separately switched 3.3V power rail */
57	pp3300_u: regulator-3v3-u {
58		compatible = "regulator-fixed";
59		regulator-name = "pp3300_u";
60		regulator-always-on;
61		regulator-boot-on;
62		regulator-min-microvolt = <3300000>;
63		regulator-max-microvolt = <3300000>;
64		/* enable pin wired to GPIO controlled by EC */
65		vin-supply = <&pp3300_g>;
66	};
67
68	/* system wide switching 5.0V power rail */
69	pp5000_a: regulator-5v0-a {
70		compatible = "regulator-fixed";
71		regulator-name = "pp5000_a";
72		regulator-always-on;
73		regulator-boot-on;
74		regulator-min-microvolt = <5000000>;
75		regulator-max-microvolt = <5000000>;
76		vin-supply = <&ppvar_sys>;
77	};
78
79	/* system wide semi-regulated power rail from battery or USB */
80	ppvar_sys: regulator-var-sys {
81		compatible = "regulator-fixed";
82		regulator-name = "ppvar_sys";
83		regulator-always-on;
84		regulator-boot-on;
85	};
86};
87
88&i2c0 {
89	status = "okay";
90
91	clock-frequency = <400000>;
92	pinctrl-names = "default";
93	pinctrl-0 = <&i2c0_pins>;
94};
95
96&i2c1 {
97	status = "okay";
98
99	clock-frequency = <400000>;
100	pinctrl-names = "default";
101	pinctrl-0 = <&i2c1_pins>;
102};
103
104&i2c2 {
105	status = "okay";
106
107	clock-frequency = <400000>;
108	clock-stretch-ns = <12600>;
109	pinctrl-names = "default";
110	pinctrl-0 = <&i2c2_pins>;
111};
112
113&i2c3 {
114	status = "okay";
115
116	clock-frequency = <400000>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&i2c3_pins>;
119};
120
121&i2c7 {
122	status = "okay";
123
124	clock-frequency = <400000>;
125	pinctrl-names = "default";
126	pinctrl-0 = <&i2c7_pins>;
127};
128
129&pio {
130	/* 220 lines */
131	gpio-line-names = "I2S_DP_LRCK",
132			  "IS_DP_BCLK",
133			  "I2S_DP_MCLK",
134			  "I2S_DP_DATAOUT",
135			  "SAR0_INT_ODL",
136			  "EC_AP_INT_ODL",
137			  "EDPBRDG_INT_ODL",
138			  "DPBRDG_INT_ODL",
139			  "DPBRDG_PWREN",
140			  "DPBRDG_RST_ODL",
141			  "I2S_HP_MCLK",
142			  "I2S_HP_BCK",
143			  "I2S_HP_LRCK",
144			  "I2S_HP_DATAIN",
145			  /*
146			   * AP_FLASH_WP_L is crossystem ABI. Schematics
147			   * call it AP_FLASH_WP_ODL.
148			   */
149			  "AP_FLASH_WP_L",
150			  "TRACKPAD_INT_ODL",
151			  "EC_AP_HPD_OD",
152			  "SD_CD_ODL",
153			  "HP_INT_ODL_ALC",
154			  "EN_PP1000_DPBRDG",
155			  "AP_GPIO20",
156			  "TOUCH_INT_L_1V8",
157			  "UART_BT_WAKE_ODL",
158			  "AP_GPIO23",
159			  "AP_SPI_FLASH_CS_L",
160			  "AP_SPI_FLASH_CLK",
161			  "EN_PP3300_DPBRDG_DX",
162			  "AP_SPI_FLASH_MOSI",
163			  "AP_SPI_FLASH_MISO",
164			  "I2S_HP_DATAOUT",
165			  "AP_GPIO30",
166			  "I2S_SPKR_MCLK",
167			  "I2S_SPKR_BCLK",
168			  "I2S_SPKR_LRCK",
169			  "I2S_SPKR_DATAIN",
170			  "I2S_SPKR_DATAOUT",
171			  "AP_SPI_H1_TPM_CLK",
172			  "AP_SPI_H1_TPM_CS_L",
173			  "AP_SPI_H1_TPM_MISO",
174			  "AP_SPI_H1_TPM_MOSI",
175			  "BL_PWM",
176			  "EDPBRDG_PWREN",
177			  "EDPBRDG_RST_ODL",
178			  "EN_PP3300_HUB",
179			  "HUB_RST_L",
180			  "",
181			  "",
182			  "",
183			  "",
184			  "",
185			  "",
186			  "SD_CLK",
187			  "SD_CMD",
188			  "SD_DATA3",
189			  "SD_DATA0",
190			  "SD_DATA2",
191			  "SD_DATA1",
192			  "",
193			  "",
194			  "",
195			  "",
196			  "",
197			  "",
198			  "PCIE_WAKE_ODL",
199			  "PCIE_RST_L",
200			  "PCIE_CLKREQ_ODL",
201			  "",
202			  "",
203			  "",
204			  "",
205			  "",
206			  "",
207			  "",
208			  "",
209			  "",
210			  "",
211			  "",
212			  "",
213			  "",
214			  "",
215			  "",
216			  "",
217			  "",
218			  "",
219			  "",
220			  "",
221			  "",
222			  "",
223			  "",
224			  "SPMI_SCL",
225			  "SPMI_SDA",
226			  "AP_GOOD",
227			  "UART_DBG_TX_AP_RX",
228			  "UART_AP_TX_DBG_RX",
229			  "UART_AP_TX_BT_RX",
230			  "UART_BT_TX_AP_RX",
231			  "MIPI_DPI_D0_R",
232			  "MIPI_DPI_D1_R",
233			  "MIPI_DPI_D2_R",
234			  "MIPI_DPI_D3_R",
235			  "MIPI_DPI_D4_R",
236			  "MIPI_DPI_D5_R",
237			  "MIPI_DPI_D6_R",
238			  "MIPI_DPI_D7_R",
239			  "MIPI_DPI_D8_R",
240			  "MIPI_DPI_D9_R",
241			  "MIPI_DPI_D10_R",
242			  "",
243			  "",
244			  "MIPI_DPI_DE_R",
245			  "MIPI_DPI_D11_R",
246			  "MIPI_DPI_VSYNC_R",
247			  "MIPI_DPI_CLK_R",
248			  "MIPI_DPI_HSYNC_R",
249			  "PCM_BT_DATAIN",
250			  "PCM_BT_SYNC",
251			  "PCM_BT_DATAOUT",
252			  "PCM_BT_CLK",
253			  "AP_I2C_AUDIO_SCL",
254			  "AP_I2C_AUDIO_SDA",
255			  "SCP_I2C_SCL",
256			  "SCP_I2C_SDA",
257			  "AP_I2C_WLAN_SCL",
258			  "AP_I2C_WLAN_SDA",
259			  "AP_I2C_DPBRDG_SCL",
260			  "AP_I2C_DPBRDG_SDA",
261			  "EN_PP1800_DPBRDG_DX",
262			  "EN_PP3300_EDP_DX",
263			  "EN_PP1800_EDPBRDG_DX",
264			  "EN_PP1000_EDPBRDG",
265			  "SCP_JTAG0_TDO",
266			  "SCP_JTAG0_TDI",
267			  "SCP_JTAG0_TMS",
268			  "SCP_JTAG0_TCK",
269			  "SCP_JTAG0_TRSTN",
270			  "EN_PP3000_VMC_PMU",
271			  "EN_PP3300_DISPLAY_DX",
272			  "TOUCH_RST_L_1V8",
273			  "TOUCH_REPORT_DISABLE",
274			  "",
275			  "",
276			  "AP_I2C_TRACKPAD_SCL_1V8",
277			  "AP_I2C_TRACKPAD_SDA_1V8",
278			  "EN_PP3300_WLAN",
279			  "BT_KILL_L",
280			  "WIFI_KILL_L",
281			  "SET_VMC_VOLT_AT_1V8",
282			  "EN_SPK",
283			  "AP_WARM_RST_REQ",
284			  "",
285			  "",
286			  "EN_PP3000_SD_S3",
287			  "AP_EDP_BKLTEN",
288			  "",
289			  "",
290			  "",
291			  "AP_SPI_EC_CLK",
292			  "AP_SPI_EC_CS_L",
293			  "AP_SPI_EC_MISO",
294			  "AP_SPI_EC_MOSI",
295			  "AP_I2C_EDPBRDG_SCL",
296			  "AP_I2C_EDPBRDG_SDA",
297			  "MT6315_PROC_INT",
298			  "MT6315_GPU_INT",
299			  "UART_SERVO_TX_SCP_RX",
300			  "UART_SCP_TX_SERVO_RX",
301			  "BT_RTS_AP_CTS",
302			  "AP_RTS_BT_CTS",
303			  "UART_AP_WAKE_BT_ODL",
304			  "WLAN_ALERT_ODL",
305			  "EC_IN_RW_ODL",
306			  "H1_AP_INT_ODL",
307			  "",
308			  "",
309			  "",
310			  "",
311			  "",
312			  "",
313			  "",
314			  "",
315			  "",
316			  "",
317			  "",
318			  "MSDC0_CMD",
319			  "MSDC0_DAT0",
320			  "MSDC0_DAT2",
321			  "MSDC0_DAT4",
322			  "MSDC0_DAT6",
323			  "MSDC0_DAT1",
324			  "MSDC0_DAT5",
325			  "MSDC0_DAT7",
326			  "MSDC0_DSL",
327			  "MSDC0_CLK",
328			  "MSDC0_DAT3",
329			  "MSDC0_RST_L",
330			  "SCP_VREQ_VAO",
331			  "AUD_DAT_MOSI2",
332			  "AUD_NLE_MOSI1",
333			  "AUD_NLE_MOSI0",
334			  "AUD_DAT_MISO2",
335			  "AP_I2C_SAR_SDA",
336			  "AP_I2C_SAR_SCL",
337			  "AP_I2C_PWR_SCL",
338			  "AP_I2C_PWR_SDA",
339			  "AP_I2C_TS_SCL_1V8",
340			  "AP_I2C_TS_SDA_1V8",
341			  "SRCLKENA0",
342			  "SRCLKENA1",
343			  "AP_EC_WATCHDOG_L",
344			  "PWRAP_SPI0_MI",
345			  "PWRAP_SPI0_CSN",
346			  "PWRAP_SPI0_MO",
347			  "PWRAP_SPI0_CK",
348			  "AP_RTC_CLK32K",
349			  "AUD_CLK_MOSI",
350			  "AUD_SYNC_MOSI",
351			  "AUD_DAT_MOSI0",
352			  "AUD_DAT_MOSI1",
353			  "AUD_DAT_MISO0",
354			  "AUD_DAT_MISO1";
355
356	i2c0_pins: i2c0-default-pins {
357		pins-bus {
358			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
359				 <PINMUX_GPIO205__FUNC_SDA0>;
360			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
361			drive-strength-microamp = <1000>;
362		};
363	};
364
365	i2c1_pins: i2c1-default-pins {
366		pins-bus {
367			pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
368				 <PINMUX_GPIO119__FUNC_SDA1>;
369			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
370			drive-strength-microamp = <1000>;
371		};
372	};
373
374	i2c2_pins: i2c2-default-pins {
375		pins-bus {
376			pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
377				 <PINMUX_GPIO142__FUNC_SDA2>;
378			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
379		};
380	};
381
382	i2c3_pins: i2c3-default-pins {
383		pins-bus {
384			pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
385				 <PINMUX_GPIO161__FUNC_SDA3>;
386			bias-disable;
387			drive-strength-microamp = <1000>;
388		};
389	};
390
391	i2c7_pins: i2c7-default-pins {
392		pins-bus {
393			pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
394				 <PINMUX_GPIO125__FUNC_SDA7>;
395			bias-disable;
396			drive-strength-microamp = <1000>;
397		};
398	};
399
400	spi1_pins: spi1-default-pins {
401		pins-cs-mosi-clk {
402			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
403				 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
404				 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
405			bias-disable;
406		};
407
408		pins-miso {
409			pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
410			bias-pull-down;
411		};
412	};
413
414	spi5_pins: spi5-default-pins {
415		pins-bus {
416			pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
417				 <PINMUX_GPIO37__FUNC_GPIO37>,
418				 <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
419				 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
420			bias-disable;
421		};
422	};
423};
424
425&spi1 {
426	status = "okay";
427
428	mediatek,pad-select = <0>;
429	pinctrl-names = "default";
430	pinctrl-0 = <&spi1_pins>;
431};
432
433&spi5 {
434	status = "okay";
435
436	cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
437	mediatek,pad-select = <0>;
438	pinctrl-names = "default";
439	pinctrl-0 = <&spi5_pins>;
440};
441
442&uart0 {
443	status = "okay";
444};
445