1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 /* system wide LDO 1.8V power rail */ 27 pp1800_ldo_g: regulator-1v8-g { 28 compatible = "regulator-fixed"; 29 regulator-name = "pp1800_ldo_g"; 30 regulator-always-on; 31 regulator-boot-on; 32 regulator-min-microvolt = <1800000>; 33 regulator-max-microvolt = <1800000>; 34 vin-supply = <&pp3300_g>; 35 }; 36 37 /* system wide switching 3.3V power rail */ 38 pp3300_g: regulator-3v3-g { 39 compatible = "regulator-fixed"; 40 regulator-name = "pp3300_g"; 41 regulator-always-on; 42 regulator-boot-on; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 vin-supply = <&ppvar_sys>; 46 }; 47 48 /* system wide LDO 3.3V power rail */ 49 pp3300_ldo_z: regulator-3v3-z { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp3300_ldo_z"; 52 regulator-always-on; 53 regulator-boot-on; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 /* separately switched 3.3V power rail */ 60 pp3300_u: regulator-3v3-u { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp3300_u"; 63 regulator-always-on; 64 regulator-boot-on; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 /* enable pin wired to GPIO controlled by EC */ 68 vin-supply = <&pp3300_g>; 69 }; 70 71 pp3300_wlan: regulator-3v3-wlan { 72 compatible = "regulator-fixed"; 73 regulator-name = "pp3300_wlan"; 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp3300_wlan_pins>; 80 enable-active-high; 81 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 82 }; 83 84 /* system wide switching 5.0V power rail */ 85 pp5000_a: regulator-5v0-a { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp5000_a"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>; 92 vin-supply = <&ppvar_sys>; 93 }; 94 95 /* system wide semi-regulated power rail from battery or USB */ 96 ppvar_sys: regulator-var-sys { 97 compatible = "regulator-fixed"; 98 regulator-name = "ppvar_sys"; 99 regulator-always-on; 100 regulator-boot-on; 101 }; 102 103 reserved_memory: reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 wifi_restricted_dma_region: wifi@c0000000 { 109 compatible = "restricted-dma-pool"; 110 reg = <0 0xc0000000 0 0x4000000>; 111 }; 112 }; 113}; 114 115&i2c0 { 116 status = "okay"; 117 118 clock-frequency = <400000>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&i2c0_pins>; 121 122 touchscreen: touchscreen@10 { 123 reg = <0x10>; 124 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&touchscreen_pins>; 127 }; 128}; 129 130&i2c1 { 131 status = "okay"; 132 133 clock-frequency = <400000>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&i2c1_pins>; 136}; 137 138&i2c2 { 139 status = "okay"; 140 141 clock-frequency = <400000>; 142 clock-stretch-ns = <12600>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&i2c2_pins>; 145 146 trackpad@15 { 147 compatible = "elan,ekth3000"; 148 reg = <0x15>; 149 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&trackpad_pins>; 152 vcc-supply = <&pp3300_u>; 153 wakeup-source; 154 }; 155}; 156 157&i2c3 { 158 status = "okay"; 159 160 clock-frequency = <400000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&i2c3_pins>; 163}; 164 165&i2c7 { 166 status = "okay"; 167 168 clock-frequency = <400000>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&i2c7_pins>; 171}; 172 173&mmc0 { 174 status = "okay"; 175 176 pinctrl-names = "default", "state_uhs"; 177 pinctrl-0 = <&mmc0_default_pins>; 178 pinctrl-1 = <&mmc0_uhs_pins>; 179 bus-width = <8>; 180 max-frequency = <200000000>; 181 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 182 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 183 cap-mmc-highspeed; 184 mmc-hs200-1_8v; 185 mmc-hs400-1_8v; 186 supports-cqe; 187 cap-mmc-hw-reset; 188 mmc-hs400-enhanced-strobe; 189 hs400-ds-delay = <0x12814>; 190 no-sdio; 191 no-sd; 192 non-removable; 193}; 194 195&mmc1 { 196 status = "okay"; 197 198 pinctrl-names = "default", "state_uhs"; 199 pinctrl-0 = <&mmc1_default_pins>; 200 pinctrl-1 = <&mmc1_uhs_pins>; 201 bus-width = <4>; 202 max-frequency = <200000000>; 203 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 204 vmmc-supply = <&mt6360_ldo5_reg>; 205 vqmmc-supply = <&mt6360_ldo3_reg>; 206 cap-sd-highspeed; 207 sd-uhs-sdr50; 208 sd-uhs-sdr104; 209 no-sdio; 210 no-mmc; 211}; 212 213/* for CORE */ 214&mt6359_vgpu11_buck_reg { 215 regulator-always-on; 216}; 217 218&mt6359_vgpu11_sshub_buck_reg { 219 regulator-always-on; 220 regulator-min-microvolt = <575000>; 221 regulator-max-microvolt = <575000>; 222}; 223 224&mt6359_vrf12_ldo_reg { 225 regulator-always-on; 226}; 227 228&mt6359_vufs_ldo_reg { 229 regulator-always-on; 230}; 231 232&mt6359codec { 233 mediatek,dmic-mode = <1>; /* one-wire */ 234 mediatek,mic-type-0 = <2>; /* DMIC */ 235 mediatek,mic-type-2 = <2>; /* DMIC */ 236}; 237 238&pcie { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pcie_pins>; 241 242 pcie0: pcie@0,0 { 243 device_type = "pci"; 244 reg = <0x0000 0 0 0 0>; 245 num-lanes = <1>; 246 bus-range = <0x1 0x1>; 247 248 #address-cells = <3>; 249 #size-cells = <2>; 250 ranges; 251 252 wifi: wifi@0,0 { 253 reg = <0x10000 0 0 0 0x100000>, 254 <0x10000 0 0x100000 0 0x100000>; 255 memory-region = <&wifi_restricted_dma_region>; 256 }; 257 }; 258}; 259 260&pio { 261 /* 220 lines */ 262 gpio-line-names = "I2S_DP_LRCK", 263 "IS_DP_BCLK", 264 "I2S_DP_MCLK", 265 "I2S_DP_DATAOUT", 266 "SAR0_INT_ODL", 267 "EC_AP_INT_ODL", 268 "EDPBRDG_INT_ODL", 269 "DPBRDG_INT_ODL", 270 "DPBRDG_PWREN", 271 "DPBRDG_RST_ODL", 272 "I2S_HP_MCLK", 273 "I2S_HP_BCK", 274 "I2S_HP_LRCK", 275 "I2S_HP_DATAIN", 276 /* 277 * AP_FLASH_WP_L is crossystem ABI. Schematics 278 * call it AP_FLASH_WP_ODL. 279 */ 280 "AP_FLASH_WP_L", 281 "TRACKPAD_INT_ODL", 282 "EC_AP_HPD_OD", 283 "SD_CD_ODL", 284 "HP_INT_ODL_ALC", 285 "EN_PP1000_DPBRDG", 286 "AP_GPIO20", 287 "TOUCH_INT_L_1V8", 288 "UART_BT_WAKE_ODL", 289 "AP_GPIO23", 290 "AP_SPI_FLASH_CS_L", 291 "AP_SPI_FLASH_CLK", 292 "EN_PP3300_DPBRDG_DX", 293 "AP_SPI_FLASH_MOSI", 294 "AP_SPI_FLASH_MISO", 295 "I2S_HP_DATAOUT", 296 "AP_GPIO30", 297 "I2S_SPKR_MCLK", 298 "I2S_SPKR_BCLK", 299 "I2S_SPKR_LRCK", 300 "I2S_SPKR_DATAIN", 301 "I2S_SPKR_DATAOUT", 302 "AP_SPI_H1_TPM_CLK", 303 "AP_SPI_H1_TPM_CS_L", 304 "AP_SPI_H1_TPM_MISO", 305 "AP_SPI_H1_TPM_MOSI", 306 "BL_PWM", 307 "EDPBRDG_PWREN", 308 "EDPBRDG_RST_ODL", 309 "EN_PP3300_HUB", 310 "HUB_RST_L", 311 "", 312 "", 313 "", 314 "", 315 "", 316 "", 317 "SD_CLK", 318 "SD_CMD", 319 "SD_DATA3", 320 "SD_DATA0", 321 "SD_DATA2", 322 "SD_DATA1", 323 "", 324 "", 325 "", 326 "", 327 "", 328 "", 329 "PCIE_WAKE_ODL", 330 "PCIE_RST_L", 331 "PCIE_CLKREQ_ODL", 332 "", 333 "", 334 "", 335 "", 336 "", 337 "", 338 "", 339 "", 340 "", 341 "", 342 "", 343 "", 344 "", 345 "", 346 "", 347 "", 348 "", 349 "", 350 "", 351 "", 352 "", 353 "", 354 "", 355 "SPMI_SCL", 356 "SPMI_SDA", 357 "AP_GOOD", 358 "UART_DBG_TX_AP_RX", 359 "UART_AP_TX_DBG_RX", 360 "UART_AP_TX_BT_RX", 361 "UART_BT_TX_AP_RX", 362 "MIPI_DPI_D0_R", 363 "MIPI_DPI_D1_R", 364 "MIPI_DPI_D2_R", 365 "MIPI_DPI_D3_R", 366 "MIPI_DPI_D4_R", 367 "MIPI_DPI_D5_R", 368 "MIPI_DPI_D6_R", 369 "MIPI_DPI_D7_R", 370 "MIPI_DPI_D8_R", 371 "MIPI_DPI_D9_R", 372 "MIPI_DPI_D10_R", 373 "", 374 "", 375 "MIPI_DPI_DE_R", 376 "MIPI_DPI_D11_R", 377 "MIPI_DPI_VSYNC_R", 378 "MIPI_DPI_CLK_R", 379 "MIPI_DPI_HSYNC_R", 380 "PCM_BT_DATAIN", 381 "PCM_BT_SYNC", 382 "PCM_BT_DATAOUT", 383 "PCM_BT_CLK", 384 "AP_I2C_AUDIO_SCL", 385 "AP_I2C_AUDIO_SDA", 386 "SCP_I2C_SCL", 387 "SCP_I2C_SDA", 388 "AP_I2C_WLAN_SCL", 389 "AP_I2C_WLAN_SDA", 390 "AP_I2C_DPBRDG_SCL", 391 "AP_I2C_DPBRDG_SDA", 392 "EN_PP1800_DPBRDG_DX", 393 "EN_PP3300_EDP_DX", 394 "EN_PP1800_EDPBRDG_DX", 395 "EN_PP1000_EDPBRDG", 396 "SCP_JTAG0_TDO", 397 "SCP_JTAG0_TDI", 398 "SCP_JTAG0_TMS", 399 "SCP_JTAG0_TCK", 400 "SCP_JTAG0_TRSTN", 401 "EN_PP3000_VMC_PMU", 402 "EN_PP3300_DISPLAY_DX", 403 "TOUCH_RST_L_1V8", 404 "TOUCH_REPORT_DISABLE", 405 "", 406 "", 407 "AP_I2C_TRACKPAD_SCL_1V8", 408 "AP_I2C_TRACKPAD_SDA_1V8", 409 "EN_PP3300_WLAN", 410 "BT_KILL_L", 411 "WIFI_KILL_L", 412 "SET_VMC_VOLT_AT_1V8", 413 "EN_SPK", 414 "AP_WARM_RST_REQ", 415 "", 416 "", 417 "EN_PP3000_SD_S3", 418 "AP_EDP_BKLTEN", 419 "", 420 "", 421 "", 422 "AP_SPI_EC_CLK", 423 "AP_SPI_EC_CS_L", 424 "AP_SPI_EC_MISO", 425 "AP_SPI_EC_MOSI", 426 "AP_I2C_EDPBRDG_SCL", 427 "AP_I2C_EDPBRDG_SDA", 428 "MT6315_PROC_INT", 429 "MT6315_GPU_INT", 430 "UART_SERVO_TX_SCP_RX", 431 "UART_SCP_TX_SERVO_RX", 432 "BT_RTS_AP_CTS", 433 "AP_RTS_BT_CTS", 434 "UART_AP_WAKE_BT_ODL", 435 "WLAN_ALERT_ODL", 436 "EC_IN_RW_ODL", 437 "H1_AP_INT_ODL", 438 "", 439 "", 440 "", 441 "", 442 "", 443 "", 444 "", 445 "", 446 "", 447 "", 448 "", 449 "MSDC0_CMD", 450 "MSDC0_DAT0", 451 "MSDC0_DAT2", 452 "MSDC0_DAT4", 453 "MSDC0_DAT6", 454 "MSDC0_DAT1", 455 "MSDC0_DAT5", 456 "MSDC0_DAT7", 457 "MSDC0_DSL", 458 "MSDC0_CLK", 459 "MSDC0_DAT3", 460 "MSDC0_RST_L", 461 "SCP_VREQ_VAO", 462 "AUD_DAT_MOSI2", 463 "AUD_NLE_MOSI1", 464 "AUD_NLE_MOSI0", 465 "AUD_DAT_MISO2", 466 "AP_I2C_SAR_SDA", 467 "AP_I2C_SAR_SCL", 468 "AP_I2C_PWR_SCL", 469 "AP_I2C_PWR_SDA", 470 "AP_I2C_TS_SCL_1V8", 471 "AP_I2C_TS_SDA_1V8", 472 "SRCLKENA0", 473 "SRCLKENA1", 474 "AP_EC_WATCHDOG_L", 475 "PWRAP_SPI0_MI", 476 "PWRAP_SPI0_CSN", 477 "PWRAP_SPI0_MO", 478 "PWRAP_SPI0_CK", 479 "AP_RTC_CLK32K", 480 "AUD_CLK_MOSI", 481 "AUD_SYNC_MOSI", 482 "AUD_DAT_MOSI0", 483 "AUD_DAT_MOSI1", 484 "AUD_DAT_MISO0", 485 "AUD_DAT_MISO1"; 486 487 cr50_int: cr50-irq-default-pins { 488 pins-gsc-ap-int-odl { 489 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 490 input-enable; 491 }; 492 }; 493 494 cros_ec_int: cros-ec-irq-default-pins { 495 pins-ec-ap-int-odl { 496 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 497 input-enable; 498 bias-pull-up; 499 }; 500 }; 501 502 i2c0_pins: i2c0-default-pins { 503 pins-bus { 504 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 505 <PINMUX_GPIO205__FUNC_SDA0>; 506 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 507 drive-strength-microamp = <1000>; 508 }; 509 }; 510 511 i2c1_pins: i2c1-default-pins { 512 pins-bus { 513 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 514 <PINMUX_GPIO119__FUNC_SDA1>; 515 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 516 drive-strength-microamp = <1000>; 517 }; 518 }; 519 520 i2c2_pins: i2c2-default-pins { 521 pins-bus { 522 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 523 <PINMUX_GPIO142__FUNC_SDA2>; 524 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 525 }; 526 }; 527 528 i2c3_pins: i2c3-default-pins { 529 pins-bus { 530 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 531 <PINMUX_GPIO161__FUNC_SDA3>; 532 bias-disable; 533 drive-strength-microamp = <1000>; 534 }; 535 }; 536 537 i2c7_pins: i2c7-default-pins { 538 pins-bus { 539 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 540 <PINMUX_GPIO125__FUNC_SDA7>; 541 bias-disable; 542 drive-strength-microamp = <1000>; 543 }; 544 }; 545 546 mmc0_default_pins: mmc0-default-pins { 547 pins-cmd-dat { 548 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 549 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 550 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 551 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 552 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 553 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 554 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 555 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 556 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 557 input-enable; 558 drive-strength = <8>; 559 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 560 }; 561 562 pins-clk { 563 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 564 drive-strength = <8>; 565 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 566 }; 567 568 pins-rst { 569 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 570 drive-strength = <8>; 571 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 572 }; 573 }; 574 575 mmc0_uhs_pins: mmc0-uhs-pins { 576 pins-cmd-dat { 577 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 578 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 579 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 580 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 581 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 582 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 583 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 584 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 585 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 586 input-enable; 587 drive-strength = <10>; 588 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 589 }; 590 591 pins-clk { 592 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 593 drive-strength = <10>; 594 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 595 }; 596 597 pins-rst { 598 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 599 drive-strength = <8>; 600 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 601 }; 602 603 pins-ds { 604 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 605 drive-strength = <10>; 606 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 607 }; 608 }; 609 610 mmc1_default_pins: mmc1-default-pins { 611 pins-cmd-dat { 612 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 613 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 614 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 615 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 616 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 617 input-enable; 618 drive-strength = <8>; 619 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 620 }; 621 622 pins-clk { 623 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 624 drive-strength = <8>; 625 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 626 }; 627 628 pins-insert { 629 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 630 input-enable; 631 bias-pull-up; 632 }; 633 }; 634 635 mmc1_uhs_pins: mmc1-uhs-pins { 636 pins-cmd-dat { 637 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 638 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 639 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 640 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 641 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 642 input-enable; 643 drive-strength = <8>; 644 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 645 }; 646 647 pins-clk { 648 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 649 input-enable; 650 drive-strength = <8>; 651 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 652 }; 653 }; 654 655 pcie_pins: pcie-default-pins { 656 pins-pcie-wake { 657 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 658 bias-pull-up; 659 }; 660 661 pins-pcie-pereset { 662 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 663 }; 664 665 pins-pcie-clkreq { 666 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 667 bias-pull-up; 668 }; 669 670 pins-wifi-kill { 671 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 672 output-high; 673 }; 674 }; 675 676 pp3300_wlan_pins: pp3300-wlan-pins { 677 pins-pcie-en-pp3300-wlan { 678 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 679 output-high; 680 }; 681 }; 682 683 spi1_pins: spi1-default-pins { 684 pins-cs-mosi-clk { 685 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 686 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 687 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 688 bias-disable; 689 }; 690 691 pins-miso { 692 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 693 bias-pull-down; 694 }; 695 }; 696 697 spi5_pins: spi5-default-pins { 698 pins-bus { 699 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 700 <PINMUX_GPIO37__FUNC_GPIO37>, 701 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 702 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 703 bias-disable; 704 }; 705 }; 706 707 trackpad_pins: trackpad-default-pins { 708 pins-int-n { 709 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 710 input-enable; 711 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 712 }; 713 }; 714 715 touchscreen_pins: touchscreen-default-pins { 716 pins-irq { 717 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 718 input-enable; 719 bias-pull-up; 720 }; 721 722 pins-reset { 723 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 724 output-high; 725 }; 726 727 pins-report-sw { 728 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 729 output-low; 730 }; 731 }; 732}; 733 734&pmic { 735 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 736}; 737 738&spi1 { 739 status = "okay"; 740 741 mediatek,pad-select = <0>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&spi1_pins>; 744 745 cros_ec: ec@0 { 746 compatible = "google,cros-ec-spi"; 747 reg = <0>; 748 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 749 spi-max-frequency = <3000000>; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&cros_ec_int>; 752 753 #address-cells = <1>; 754 #size-cells = <0>; 755 756 base_detection: cbas { 757 compatible = "google,cros-cbas"; 758 }; 759 760 cros_ec_pwm: pwm { 761 compatible = "google,cros-ec-pwm"; 762 #pwm-cells = <1>; 763 764 status = "disabled"; 765 }; 766 767 i2c_tunnel: i2c-tunnel { 768 compatible = "google,cros-ec-i2c-tunnel"; 769 google,remote-bus = <0>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 }; 773 774 mt6360_ldo3_reg: regulator@0 { 775 compatible = "google,cros-ec-regulator"; 776 reg = <0>; 777 regulator-min-microvolt = <1800000>; 778 regulator-max-microvolt = <3300000>; 779 }; 780 781 mt6360_ldo5_reg: regulator@1 { 782 compatible = "google,cros-ec-regulator"; 783 reg = <1>; 784 regulator-min-microvolt = <3300000>; 785 regulator-max-microvolt = <3300000>; 786 }; 787 788 typec { 789 compatible = "google,cros-ec-typec"; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 usb_c0: connector@0 { 794 compatible = "usb-c-connector"; 795 reg = <0>; 796 label = "left"; 797 power-role = "dual"; 798 data-role = "host"; 799 try-power-role = "source"; 800 }; 801 802 usb_c1: connector@1 { 803 compatible = "usb-c-connector"; 804 reg = <1>; 805 label = "right"; 806 power-role = "dual"; 807 data-role = "host"; 808 try-power-role = "source"; 809 }; 810 }; 811 }; 812}; 813 814&spi5 { 815 status = "okay"; 816 817 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 818 mediatek,pad-select = <0>; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&spi5_pins>; 821 822 cr50@0 { 823 compatible = "google,cr50"; 824 reg = <0>; 825 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 826 spi-max-frequency = <1000000>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&cr50_int>; 829 }; 830}; 831 832&spmi { 833 #address-cells = <2>; 834 #size-cells = <0>; 835 836 mt6315_6: pmic@6 { 837 compatible = "mediatek,mt6315-regulator"; 838 reg = <0x6 SPMI_USID>; 839 840 regulators { 841 mt6315_6_vbuck1: vbuck1 { 842 regulator-compatible = "vbuck1"; 843 regulator-name = "Vbcpu"; 844 regulator-min-microvolt = <300000>; 845 regulator-max-microvolt = <1193750>; 846 regulator-enable-ramp-delay = <256>; 847 regulator-allowed-modes = <0 1 2>; 848 regulator-always-on; 849 }; 850 851 mt6315_6_vbuck3: vbuck3 { 852 regulator-compatible = "vbuck3"; 853 regulator-name = "Vlcpu"; 854 regulator-min-microvolt = <300000>; 855 regulator-max-microvolt = <1193750>; 856 regulator-enable-ramp-delay = <256>; 857 regulator-allowed-modes = <0 1 2>; 858 regulator-always-on; 859 }; 860 }; 861 }; 862 863 mt6315_7: pmic@7 { 864 compatible = "mediatek,mt6315-regulator"; 865 reg = <0x7 SPMI_USID>; 866 867 regulators { 868 mt6315_7_vbuck1: vbuck1 { 869 regulator-compatible = "vbuck1"; 870 regulator-name = "Vgpu"; 871 regulator-min-microvolt = <606250>; 872 regulator-max-microvolt = <1193750>; 873 regulator-enable-ramp-delay = <256>; 874 regulator-allowed-modes = <0 1 2>; 875 }; 876 }; 877 }; 878}; 879 880&uart0 { 881 status = "okay"; 882}; 883 884&xhci { 885 status = "okay"; 886 887 wakeup-source; 888 vusb33-supply = <&pp3300_g>; 889 vbus-supply = <&pp5000_a>; 890}; 891 892#include <arm/cros-ec-keyboard.dtsi> 893#include <arm/cros-ec-sbs.dtsi> 894