1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6/dts-v1/;
7#include "mt8192.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	aliases {
12		serial0 = &uart0;
13	};
14
15	chosen {
16		stdout-path = "serial0:115200n8";
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0 0x40000000 0 0x80000000>;
22	};
23
24	/* system wide LDO 1.8V power rail */
25	pp1800_ldo_g: regulator-1v8-g {
26		compatible = "regulator-fixed";
27		regulator-name = "pp1800_ldo_g";
28		regulator-always-on;
29		regulator-boot-on;
30		regulator-min-microvolt = <1800000>;
31		regulator-max-microvolt = <1800000>;
32		vin-supply = <&pp3300_g>;
33	};
34
35	/* system wide switching 3.3V power rail */
36	pp3300_g: regulator-3v3-g {
37		compatible = "regulator-fixed";
38		regulator-name = "pp3300_g";
39		regulator-always-on;
40		regulator-boot-on;
41		regulator-min-microvolt = <3300000>;
42		regulator-max-microvolt = <3300000>;
43		vin-supply = <&ppvar_sys>;
44	};
45
46	/* system wide LDO 3.3V power rail */
47	pp3300_ldo_z: regulator-3v3-z {
48		compatible = "regulator-fixed";
49		regulator-name = "pp3300_ldo_z";
50		regulator-always-on;
51		regulator-boot-on;
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		vin-supply = <&ppvar_sys>;
55	};
56
57	/* separately switched 3.3V power rail */
58	pp3300_u: regulator-3v3-u {
59		compatible = "regulator-fixed";
60		regulator-name = "pp3300_u";
61		regulator-always-on;
62		regulator-boot-on;
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		/* enable pin wired to GPIO controlled by EC */
66		vin-supply = <&pp3300_g>;
67	};
68
69	pp3300_wlan: regulator-3v3-wlan {
70		compatible = "regulator-fixed";
71		regulator-name = "pp3300_wlan";
72		regulator-always-on;
73		regulator-boot-on;
74		regulator-min-microvolt = <3300000>;
75		regulator-max-microvolt = <3300000>;
76		pinctrl-names = "default";
77		pinctrl-0 = <&pp3300_wlan_pins>;
78		enable-active-high;
79		gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
80	};
81
82	/* system wide switching 5.0V power rail */
83	pp5000_a: regulator-5v0-a {
84		compatible = "regulator-fixed";
85		regulator-name = "pp5000_a";
86		regulator-always-on;
87		regulator-boot-on;
88		regulator-min-microvolt = <5000000>;
89		regulator-max-microvolt = <5000000>;
90		vin-supply = <&ppvar_sys>;
91	};
92
93	/* system wide semi-regulated power rail from battery or USB */
94	ppvar_sys: regulator-var-sys {
95		compatible = "regulator-fixed";
96		regulator-name = "ppvar_sys";
97		regulator-always-on;
98		regulator-boot-on;
99	};
100
101	reserved_memory: reserved-memory {
102		#address-cells = <2>;
103		#size-cells = <2>;
104		ranges;
105
106		wifi_restricted_dma_region: wifi@c0000000 {
107			compatible = "restricted-dma-pool";
108			reg = <0 0xc0000000 0 0x4000000>;
109		};
110	};
111};
112
113&i2c0 {
114	status = "okay";
115
116	clock-frequency = <400000>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&i2c0_pins>;
119
120	touchscreen: touchscreen@10 {
121		reg = <0x10>;
122		interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>;
123		pinctrl-names = "default";
124		pinctrl-0 = <&touchscreen_pins>;
125	};
126};
127
128&i2c1 {
129	status = "okay";
130
131	clock-frequency = <400000>;
132	pinctrl-names = "default";
133	pinctrl-0 = <&i2c1_pins>;
134};
135
136&i2c2 {
137	status = "okay";
138
139	clock-frequency = <400000>;
140	clock-stretch-ns = <12600>;
141	pinctrl-names = "default";
142	pinctrl-0 = <&i2c2_pins>;
143
144	trackpad@15 {
145		compatible = "elan,ekth3000";
146		reg = <0x15>;
147		interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
148		pinctrl-names = "default";
149		pinctrl-0 = <&trackpad_pins>;
150		vcc-supply = <&pp3300_u>;
151		wakeup-source;
152	};
153};
154
155&i2c3 {
156	status = "okay";
157
158	clock-frequency = <400000>;
159	pinctrl-names = "default";
160	pinctrl-0 = <&i2c3_pins>;
161};
162
163&i2c7 {
164	status = "okay";
165
166	clock-frequency = <400000>;
167	pinctrl-names = "default";
168	pinctrl-0 = <&i2c7_pins>;
169};
170
171&pcie {
172	pinctrl-names = "default";
173	pinctrl-0 = <&pcie_pins>;
174
175	pcie0: pcie@0,0 {
176		device_type = "pci";
177		reg = <0x0000 0 0 0 0>;
178		num-lanes = <1>;
179		bus-range = <0x1 0x1>;
180
181		#address-cells = <3>;
182		#size-cells = <2>;
183		ranges;
184
185		wifi: wifi@0,0 {
186			reg = <0x10000 0 0 0 0x100000>,
187			      <0x10000 0 0x100000 0 0x100000>;
188			memory-region = <&wifi_restricted_dma_region>;
189		};
190	};
191};
192
193&pio {
194	/* 220 lines */
195	gpio-line-names = "I2S_DP_LRCK",
196			  "IS_DP_BCLK",
197			  "I2S_DP_MCLK",
198			  "I2S_DP_DATAOUT",
199			  "SAR0_INT_ODL",
200			  "EC_AP_INT_ODL",
201			  "EDPBRDG_INT_ODL",
202			  "DPBRDG_INT_ODL",
203			  "DPBRDG_PWREN",
204			  "DPBRDG_RST_ODL",
205			  "I2S_HP_MCLK",
206			  "I2S_HP_BCK",
207			  "I2S_HP_LRCK",
208			  "I2S_HP_DATAIN",
209			  /*
210			   * AP_FLASH_WP_L is crossystem ABI. Schematics
211			   * call it AP_FLASH_WP_ODL.
212			   */
213			  "AP_FLASH_WP_L",
214			  "TRACKPAD_INT_ODL",
215			  "EC_AP_HPD_OD",
216			  "SD_CD_ODL",
217			  "HP_INT_ODL_ALC",
218			  "EN_PP1000_DPBRDG",
219			  "AP_GPIO20",
220			  "TOUCH_INT_L_1V8",
221			  "UART_BT_WAKE_ODL",
222			  "AP_GPIO23",
223			  "AP_SPI_FLASH_CS_L",
224			  "AP_SPI_FLASH_CLK",
225			  "EN_PP3300_DPBRDG_DX",
226			  "AP_SPI_FLASH_MOSI",
227			  "AP_SPI_FLASH_MISO",
228			  "I2S_HP_DATAOUT",
229			  "AP_GPIO30",
230			  "I2S_SPKR_MCLK",
231			  "I2S_SPKR_BCLK",
232			  "I2S_SPKR_LRCK",
233			  "I2S_SPKR_DATAIN",
234			  "I2S_SPKR_DATAOUT",
235			  "AP_SPI_H1_TPM_CLK",
236			  "AP_SPI_H1_TPM_CS_L",
237			  "AP_SPI_H1_TPM_MISO",
238			  "AP_SPI_H1_TPM_MOSI",
239			  "BL_PWM",
240			  "EDPBRDG_PWREN",
241			  "EDPBRDG_RST_ODL",
242			  "EN_PP3300_HUB",
243			  "HUB_RST_L",
244			  "",
245			  "",
246			  "",
247			  "",
248			  "",
249			  "",
250			  "SD_CLK",
251			  "SD_CMD",
252			  "SD_DATA3",
253			  "SD_DATA0",
254			  "SD_DATA2",
255			  "SD_DATA1",
256			  "",
257			  "",
258			  "",
259			  "",
260			  "",
261			  "",
262			  "PCIE_WAKE_ODL",
263			  "PCIE_RST_L",
264			  "PCIE_CLKREQ_ODL",
265			  "",
266			  "",
267			  "",
268			  "",
269			  "",
270			  "",
271			  "",
272			  "",
273			  "",
274			  "",
275			  "",
276			  "",
277			  "",
278			  "",
279			  "",
280			  "",
281			  "",
282			  "",
283			  "",
284			  "",
285			  "",
286			  "",
287			  "",
288			  "SPMI_SCL",
289			  "SPMI_SDA",
290			  "AP_GOOD",
291			  "UART_DBG_TX_AP_RX",
292			  "UART_AP_TX_DBG_RX",
293			  "UART_AP_TX_BT_RX",
294			  "UART_BT_TX_AP_RX",
295			  "MIPI_DPI_D0_R",
296			  "MIPI_DPI_D1_R",
297			  "MIPI_DPI_D2_R",
298			  "MIPI_DPI_D3_R",
299			  "MIPI_DPI_D4_R",
300			  "MIPI_DPI_D5_R",
301			  "MIPI_DPI_D6_R",
302			  "MIPI_DPI_D7_R",
303			  "MIPI_DPI_D8_R",
304			  "MIPI_DPI_D9_R",
305			  "MIPI_DPI_D10_R",
306			  "",
307			  "",
308			  "MIPI_DPI_DE_R",
309			  "MIPI_DPI_D11_R",
310			  "MIPI_DPI_VSYNC_R",
311			  "MIPI_DPI_CLK_R",
312			  "MIPI_DPI_HSYNC_R",
313			  "PCM_BT_DATAIN",
314			  "PCM_BT_SYNC",
315			  "PCM_BT_DATAOUT",
316			  "PCM_BT_CLK",
317			  "AP_I2C_AUDIO_SCL",
318			  "AP_I2C_AUDIO_SDA",
319			  "SCP_I2C_SCL",
320			  "SCP_I2C_SDA",
321			  "AP_I2C_WLAN_SCL",
322			  "AP_I2C_WLAN_SDA",
323			  "AP_I2C_DPBRDG_SCL",
324			  "AP_I2C_DPBRDG_SDA",
325			  "EN_PP1800_DPBRDG_DX",
326			  "EN_PP3300_EDP_DX",
327			  "EN_PP1800_EDPBRDG_DX",
328			  "EN_PP1000_EDPBRDG",
329			  "SCP_JTAG0_TDO",
330			  "SCP_JTAG0_TDI",
331			  "SCP_JTAG0_TMS",
332			  "SCP_JTAG0_TCK",
333			  "SCP_JTAG0_TRSTN",
334			  "EN_PP3000_VMC_PMU",
335			  "EN_PP3300_DISPLAY_DX",
336			  "TOUCH_RST_L_1V8",
337			  "TOUCH_REPORT_DISABLE",
338			  "",
339			  "",
340			  "AP_I2C_TRACKPAD_SCL_1V8",
341			  "AP_I2C_TRACKPAD_SDA_1V8",
342			  "EN_PP3300_WLAN",
343			  "BT_KILL_L",
344			  "WIFI_KILL_L",
345			  "SET_VMC_VOLT_AT_1V8",
346			  "EN_SPK",
347			  "AP_WARM_RST_REQ",
348			  "",
349			  "",
350			  "EN_PP3000_SD_S3",
351			  "AP_EDP_BKLTEN",
352			  "",
353			  "",
354			  "",
355			  "AP_SPI_EC_CLK",
356			  "AP_SPI_EC_CS_L",
357			  "AP_SPI_EC_MISO",
358			  "AP_SPI_EC_MOSI",
359			  "AP_I2C_EDPBRDG_SCL",
360			  "AP_I2C_EDPBRDG_SDA",
361			  "MT6315_PROC_INT",
362			  "MT6315_GPU_INT",
363			  "UART_SERVO_TX_SCP_RX",
364			  "UART_SCP_TX_SERVO_RX",
365			  "BT_RTS_AP_CTS",
366			  "AP_RTS_BT_CTS",
367			  "UART_AP_WAKE_BT_ODL",
368			  "WLAN_ALERT_ODL",
369			  "EC_IN_RW_ODL",
370			  "H1_AP_INT_ODL",
371			  "",
372			  "",
373			  "",
374			  "",
375			  "",
376			  "",
377			  "",
378			  "",
379			  "",
380			  "",
381			  "",
382			  "MSDC0_CMD",
383			  "MSDC0_DAT0",
384			  "MSDC0_DAT2",
385			  "MSDC0_DAT4",
386			  "MSDC0_DAT6",
387			  "MSDC0_DAT1",
388			  "MSDC0_DAT5",
389			  "MSDC0_DAT7",
390			  "MSDC0_DSL",
391			  "MSDC0_CLK",
392			  "MSDC0_DAT3",
393			  "MSDC0_RST_L",
394			  "SCP_VREQ_VAO",
395			  "AUD_DAT_MOSI2",
396			  "AUD_NLE_MOSI1",
397			  "AUD_NLE_MOSI0",
398			  "AUD_DAT_MISO2",
399			  "AP_I2C_SAR_SDA",
400			  "AP_I2C_SAR_SCL",
401			  "AP_I2C_PWR_SCL",
402			  "AP_I2C_PWR_SDA",
403			  "AP_I2C_TS_SCL_1V8",
404			  "AP_I2C_TS_SDA_1V8",
405			  "SRCLKENA0",
406			  "SRCLKENA1",
407			  "AP_EC_WATCHDOG_L",
408			  "PWRAP_SPI0_MI",
409			  "PWRAP_SPI0_CSN",
410			  "PWRAP_SPI0_MO",
411			  "PWRAP_SPI0_CK",
412			  "AP_RTC_CLK32K",
413			  "AUD_CLK_MOSI",
414			  "AUD_SYNC_MOSI",
415			  "AUD_DAT_MOSI0",
416			  "AUD_DAT_MOSI1",
417			  "AUD_DAT_MISO0",
418			  "AUD_DAT_MISO1";
419
420	cr50_int: cr50-irq-default-pins {
421		pins-gsc-ap-int-odl {
422			pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
423			input-enable;
424		};
425	};
426
427	cros_ec_int: cros-ec-irq-default-pins {
428		pins-ec-ap-int-odl {
429			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
430			input-enable;
431			bias-pull-up;
432		};
433	};
434
435	i2c0_pins: i2c0-default-pins {
436		pins-bus {
437			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
438				 <PINMUX_GPIO205__FUNC_SDA0>;
439			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
440			drive-strength-microamp = <1000>;
441		};
442	};
443
444	i2c1_pins: i2c1-default-pins {
445		pins-bus {
446			pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
447				 <PINMUX_GPIO119__FUNC_SDA1>;
448			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
449			drive-strength-microamp = <1000>;
450		};
451	};
452
453	i2c2_pins: i2c2-default-pins {
454		pins-bus {
455			pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
456				 <PINMUX_GPIO142__FUNC_SDA2>;
457			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
458		};
459	};
460
461	i2c3_pins: i2c3-default-pins {
462		pins-bus {
463			pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
464				 <PINMUX_GPIO161__FUNC_SDA3>;
465			bias-disable;
466			drive-strength-microamp = <1000>;
467		};
468	};
469
470	i2c7_pins: i2c7-default-pins {
471		pins-bus {
472			pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
473				 <PINMUX_GPIO125__FUNC_SDA7>;
474			bias-disable;
475			drive-strength-microamp = <1000>;
476		};
477	};
478
479	pcie_pins: pcie-default-pins {
480		pins-pcie-wake {
481			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
482			bias-pull-up;
483		};
484
485		pins-pcie-pereset {
486			pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
487		};
488
489		pins-pcie-clkreq {
490			pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
491			bias-pull-up;
492		};
493
494		pins-wifi-kill {
495			pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
496			output-high;
497		};
498	};
499
500	pp3300_wlan_pins: pp3300-wlan-pins {
501		pins-pcie-en-pp3300-wlan {
502			pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
503			output-high;
504		};
505	};
506
507	spi1_pins: spi1-default-pins {
508		pins-cs-mosi-clk {
509			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
510				 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
511				 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
512			bias-disable;
513		};
514
515		pins-miso {
516			pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
517			bias-pull-down;
518		};
519	};
520
521	spi5_pins: spi5-default-pins {
522		pins-bus {
523			pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
524				 <PINMUX_GPIO37__FUNC_GPIO37>,
525				 <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
526				 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
527			bias-disable;
528		};
529	};
530
531	trackpad_pins: trackpad-default-pins {
532		pins-int-n {
533			pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
534			input-enable;
535			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
536		};
537	};
538
539	touchscreen_pins: touchscreen-default-pins {
540		pins-irq {
541			pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
542			input-enable;
543			bias-pull-up;
544		};
545
546		pins-reset {
547			pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
548			output-high;
549		};
550
551		pins-report-sw {
552			pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
553			output-low;
554		};
555	};
556};
557
558&spi1 {
559	status = "okay";
560
561	mediatek,pad-select = <0>;
562	pinctrl-names = "default";
563	pinctrl-0 = <&spi1_pins>;
564
565	cros_ec: ec@0 {
566		compatible = "google,cros-ec-spi";
567		reg = <0>;
568		interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
569		spi-max-frequency = <3000000>;
570		pinctrl-names = "default";
571		pinctrl-0 = <&cros_ec_int>;
572
573		#address-cells = <1>;
574		#size-cells = <0>;
575
576		base_detection: cbas {
577			compatible = "google,cros-cbas";
578		};
579
580		cros_ec_pwm: pwm {
581			compatible = "google,cros-ec-pwm";
582			#pwm-cells = <1>;
583
584			status = "disabled";
585		};
586
587		i2c_tunnel: i2c-tunnel {
588			compatible = "google,cros-ec-i2c-tunnel";
589			google,remote-bus = <0>;
590			#address-cells = <1>;
591			#size-cells = <0>;
592		};
593
594		mt6360_ldo3_reg: regulator@0 {
595			compatible = "google,cros-ec-regulator";
596			reg = <0>;
597			regulator-min-microvolt = <1800000>;
598			regulator-max-microvolt = <3300000>;
599		};
600
601		mt6360_ldo5_reg: regulator@1 {
602			compatible = "google,cros-ec-regulator";
603			reg = <1>;
604			regulator-min-microvolt = <3300000>;
605			regulator-max-microvolt = <3300000>;
606		};
607
608		typec {
609			compatible = "google,cros-ec-typec";
610			#address-cells = <1>;
611			#size-cells = <0>;
612
613			usb_c0: connector@0 {
614				compatible = "usb-c-connector";
615				reg = <0>;
616				label = "left";
617				power-role = "dual";
618				data-role = "host";
619				try-power-role = "source";
620			};
621
622			usb_c1: connector@1 {
623				compatible = "usb-c-connector";
624				reg = <1>;
625				label = "right";
626				power-role = "dual";
627				data-role = "host";
628				try-power-role = "source";
629			};
630		};
631	};
632};
633
634&spi5 {
635	status = "okay";
636
637	cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
638	mediatek,pad-select = <0>;
639	pinctrl-names = "default";
640	pinctrl-0 = <&spi5_pins>;
641
642	cr50@0 {
643		compatible = "google,cr50";
644		reg = <0>;
645		interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
646		spi-max-frequency = <1000000>;
647		pinctrl-names = "default";
648		pinctrl-0 = <&cr50_int>;
649	};
650};
651
652&uart0 {
653	status = "okay";
654};
655
656&xhci {
657	status = "okay";
658
659	wakeup-source;
660	vusb33-supply = <&pp3300_g>;
661	vbus-supply = <&pp5000_a>;
662};
663
664#include <arm/cros-ec-keyboard.dtsi>
665#include <arm/cros-ec-sbs.dtsi>
666