1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 11#include <dt-bindings/power/mt8186-power.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/reset/mt8186-resets.h> 14 15/ { 16 compatible = "mediatek,mt8186"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 39 core3 { 40 cpu = <&cpu3>; 41 }; 42 43 core4 { 44 cpu = <&cpu4>; 45 }; 46 47 core5 { 48 cpu = <&cpu5>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu6>; 55 }; 56 57 core1 { 58 cpu = <&cpu7>; 59 }; 60 }; 61 }; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x000>; 67 enable-method = "psci"; 68 clock-frequency = <2000000000>; 69 capacity-dmips-mhz = <382>; 70 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 71 next-level-cache = <&l2_0>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x100>; 79 enable-method = "psci"; 80 clock-frequency = <2000000000>; 81 capacity-dmips-mhz = <382>; 82 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 83 next-level-cache = <&l2_0>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu2: cpu@200 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a55"; 90 reg = <0x200>; 91 enable-method = "psci"; 92 clock-frequency = <2000000000>; 93 capacity-dmips-mhz = <382>; 94 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 95 next-level-cache = <&l2_0>; 96 #cooling-cells = <2>; 97 }; 98 99 cpu3: cpu@300 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x300>; 103 enable-method = "psci"; 104 clock-frequency = <2000000000>; 105 capacity-dmips-mhz = <382>; 106 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 107 next-level-cache = <&l2_0>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x400>; 115 enable-method = "psci"; 116 clock-frequency = <2000000000>; 117 capacity-dmips-mhz = <382>; 118 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 119 next-level-cache = <&l2_0>; 120 #cooling-cells = <2>; 121 }; 122 123 cpu5: cpu@500 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a55"; 126 reg = <0x500>; 127 enable-method = "psci"; 128 clock-frequency = <2000000000>; 129 capacity-dmips-mhz = <382>; 130 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 131 next-level-cache = <&l2_0>; 132 #cooling-cells = <2>; 133 }; 134 135 cpu6: cpu@600 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a76"; 138 reg = <0x600>; 139 enable-method = "psci"; 140 clock-frequency = <2050000000>; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu7: cpu@700 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a76"; 150 reg = <0x700>; 151 enable-method = "psci"; 152 clock-frequency = <2050000000>; 153 capacity-dmips-mhz = <1024>; 154 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 155 next-level-cache = <&l2_1>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 cpu_off_l: cpu-off-l { 163 compatible = "arm,idle-state"; 164 arm,psci-suspend-param = <0x00010001>; 165 local-timer-stop; 166 entry-latency-us = <50>; 167 exit-latency-us = <100>; 168 min-residency-us = <1600>; 169 }; 170 171 cpu_off_b: cpu-off-b { 172 compatible = "arm,idle-state"; 173 arm,psci-suspend-param = <0x00010001>; 174 local-timer-stop; 175 entry-latency-us = <50>; 176 exit-latency-us = <100>; 177 min-residency-us = <1400>; 178 }; 179 180 cluster_off_l: cluster-off-l { 181 compatible = "arm,idle-state"; 182 arm,psci-suspend-param = <0x01010001>; 183 local-timer-stop; 184 entry-latency-us = <100>; 185 exit-latency-us = <250>; 186 min-residency-us = <2100>; 187 }; 188 189 cluster_off_b: cluster-off-b { 190 compatible = "arm,idle-state"; 191 arm,psci-suspend-param = <0x01010001>; 192 local-timer-stop; 193 entry-latency-us = <100>; 194 exit-latency-us = <250>; 195 min-residency-us = <1900>; 196 }; 197 }; 198 199 l2_0: l2-cache0 { 200 compatible = "cache"; 201 cache-level = <2>; 202 next-level-cache = <&l3_0>; 203 }; 204 205 l2_1: l2-cache1 { 206 compatible = "cache"; 207 cache-level = <2>; 208 next-level-cache = <&l3_0>; 209 }; 210 211 l3_0: l3-cache { 212 compatible = "cache"; 213 cache-level = <3>; 214 }; 215 }; 216 217 clk13m: oscillator-13m { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <13000000>; 221 clock-output-names = "clk13m"; 222 }; 223 224 clk26m: oscillator-26m { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <26000000>; 228 clock-output-names = "clk26m"; 229 }; 230 231 clk32k: oscillator-32k { 232 compatible = "fixed-clock"; 233 #clock-cells = <0>; 234 clock-frequency = <32768>; 235 clock-output-names = "clk32k"; 236 }; 237 238 pmu-a55 { 239 compatible = "arm,cortex-a55-pmu"; 240 interrupt-parent = <&gic>; 241 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 242 }; 243 244 pmu-a76 { 245 compatible = "arm,cortex-a76-pmu"; 246 interrupt-parent = <&gic>; 247 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 248 }; 249 250 psci { 251 compatible = "arm,psci-1.0"; 252 method = "smc"; 253 }; 254 255 timer { 256 compatible = "arm,armv8-timer"; 257 interrupt-parent = <&gic>; 258 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 259 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 260 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 261 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 262 }; 263 264 soc { 265 #address-cells = <2>; 266 #size-cells = <2>; 267 compatible = "simple-bus"; 268 ranges; 269 270 gic: interrupt-controller@c000000 { 271 compatible = "arm,gic-v3"; 272 #interrupt-cells = <4>; 273 #redistributor-regions = <1>; 274 interrupt-parent = <&gic>; 275 interrupt-controller; 276 reg = <0 0x0c000000 0 0x40000>, 277 <0 0x0c040000 0 0x200000>; 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 279 280 ppi-partitions { 281 ppi_cluster0: interrupt-partition-0 { 282 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 283 }; 284 285 ppi_cluster1: interrupt-partition-1 { 286 affinity = <&cpu6 &cpu7>; 287 }; 288 }; 289 }; 290 291 mcusys: syscon@c53a000 { 292 compatible = "mediatek,mt8186-mcusys", "syscon"; 293 reg = <0 0xc53a000 0 0x1000>; 294 #clock-cells = <1>; 295 }; 296 297 topckgen: syscon@10000000 { 298 compatible = "mediatek,mt8186-topckgen", "syscon"; 299 reg = <0 0x10000000 0 0x1000>; 300 #clock-cells = <1>; 301 }; 302 303 infracfg_ao: syscon@10001000 { 304 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 305 reg = <0 0x10001000 0 0x1000>; 306 #clock-cells = <1>; 307 #reset-cells = <1>; 308 }; 309 310 pericfg: syscon@10003000 { 311 compatible = "mediatek,mt8186-pericfg", "syscon"; 312 reg = <0 0x10003000 0 0x1000>; 313 }; 314 315 pio: pinctrl@10005000 { 316 compatible = "mediatek,mt8186-pinctrl"; 317 reg = <0 0x10005000 0 0x1000>, 318 <0 0x10002000 0 0x0200>, 319 <0 0x10002200 0 0x0200>, 320 <0 0x10002400 0 0x0200>, 321 <0 0x10002600 0 0x0200>, 322 <0 0x10002a00 0 0x0200>, 323 <0 0x10002c00 0 0x0200>, 324 <0 0x1000b000 0 0x1000>; 325 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 326 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 327 gpio-controller; 328 #gpio-cells = <2>; 329 gpio-ranges = <&pio 0 0 185>; 330 interrupt-controller; 331 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 332 #interrupt-cells = <2>; 333 }; 334 335 scpsys: syscon@10006000 { 336 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 337 reg = <0 0x10006000 0 0x1000>; 338 339 /* System Power Manager */ 340 spm: power-controller { 341 compatible = "mediatek,mt8186-power-controller"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 #power-domain-cells = <1>; 345 346 /* power domain of the SoC */ 347 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 348 reg = <MT8186_POWER_DOMAIN_MFG0>; 349 clocks = <&topckgen CLK_TOP_MFG>; 350 clock-names = "mfg00"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 #power-domain-cells = <1>; 354 355 power-domain@MT8186_POWER_DOMAIN_MFG1 { 356 reg = <MT8186_POWER_DOMAIN_MFG1>; 357 mediatek,infracfg = <&infracfg_ao>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 #power-domain-cells = <1>; 361 362 power-domain@MT8186_POWER_DOMAIN_MFG2 { 363 reg = <MT8186_POWER_DOMAIN_MFG2>; 364 #power-domain-cells = <0>; 365 }; 366 367 power-domain@MT8186_POWER_DOMAIN_MFG3 { 368 reg = <MT8186_POWER_DOMAIN_MFG3>; 369 #power-domain-cells = <0>; 370 }; 371 }; 372 }; 373 374 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 375 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 376 clocks = <&topckgen CLK_TOP_SENINF>, 377 <&topckgen CLK_TOP_SENINF1>; 378 clock-names = "csirx_top0", "csirx_top1"; 379 #power-domain-cells = <0>; 380 }; 381 382 power-domain@MT8186_POWER_DOMAIN_SSUSB { 383 reg = <MT8186_POWER_DOMAIN_SSUSB>; 384 #power-domain-cells = <0>; 385 }; 386 387 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 388 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 389 #power-domain-cells = <0>; 390 }; 391 392 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 393 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 394 clocks = <&topckgen CLK_TOP_AUDIODSP>, 395 <&topckgen CLK_TOP_ADSP_BUS>; 396 clock-names = "audioadsp", "adsp_bus"; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 #power-domain-cells = <1>; 400 401 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 402 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 #power-domain-cells = <1>; 406 407 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 408 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 409 mediatek,infracfg = <&infracfg_ao>; 410 #power-domain-cells = <0>; 411 }; 412 }; 413 }; 414 415 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 416 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 417 mediatek,infracfg = <&infracfg_ao>; 418 #power-domain-cells = <0>; 419 }; 420 421 power-domain@MT8186_POWER_DOMAIN_DIS { 422 reg = <MT8186_POWER_DOMAIN_DIS>; 423 clocks = <&topckgen CLK_TOP_DISP>, 424 <&topckgen CLK_TOP_MDP>, 425 <&mmsys CLK_MM_SMI_INFRA>, 426 <&mmsys CLK_MM_SMI_COMMON>, 427 <&mmsys CLK_MM_SMI_GALS>, 428 <&mmsys CLK_MM_SMI_IOMMU>; 429 clock-names = "disp", "mdp", "smi_infra", "smi_common", 430 "smi_gals", "smi_iommu"; 431 mediatek,infracfg = <&infracfg_ao>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 #power-domain-cells = <1>; 435 436 power-domain@MT8186_POWER_DOMAIN_VDEC { 437 reg = <MT8186_POWER_DOMAIN_VDEC>; 438 clocks = <&topckgen CLK_TOP_VDEC>, 439 <&vdecsys CLK_VDEC_LARB1_CKEN>; 440 clock-names = "vdec0", "larb"; 441 mediatek,infracfg = <&infracfg_ao>; 442 #power-domain-cells = <0>; 443 }; 444 445 power-domain@MT8186_POWER_DOMAIN_CAM { 446 reg = <MT8186_POWER_DOMAIN_CAM>; 447 clocks = <&topckgen CLK_TOP_CAM>, 448 <&topckgen CLK_TOP_SENINF>, 449 <&topckgen CLK_TOP_SENINF1>, 450 <&topckgen CLK_TOP_SENINF2>, 451 <&topckgen CLK_TOP_SENINF3>, 452 <&topckgen CLK_TOP_CAMTM>, 453 <&camsys CLK_CAM2MM_GALS>; 454 clock-names = "cam-top", "cam0", "cam1", "cam2", 455 "cam3", "cam-tm", "gals"; 456 mediatek,infracfg = <&infracfg_ao>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 #power-domain-cells = <1>; 460 461 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 462 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 463 #power-domain-cells = <0>; 464 }; 465 466 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 467 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 468 #power-domain-cells = <0>; 469 }; 470 }; 471 472 power-domain@MT8186_POWER_DOMAIN_IMG { 473 reg = <MT8186_POWER_DOMAIN_IMG>; 474 clocks = <&topckgen CLK_TOP_IMG1>, 475 <&imgsys1 CLK_IMG1_GALS_IMG1>; 476 clock-names = "img-top", "gals"; 477 mediatek,infracfg = <&infracfg_ao>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 #power-domain-cells = <1>; 481 482 power-domain@MT8186_POWER_DOMAIN_IMG2 { 483 reg = <MT8186_POWER_DOMAIN_IMG2>; 484 #power-domain-cells = <0>; 485 }; 486 }; 487 488 power-domain@MT8186_POWER_DOMAIN_IPE { 489 reg = <MT8186_POWER_DOMAIN_IPE>; 490 clocks = <&topckgen CLK_TOP_IPE>, 491 <&ipesys CLK_IPE_LARB19>, 492 <&ipesys CLK_IPE_LARB20>, 493 <&ipesys CLK_IPE_SMI_SUBCOM>, 494 <&ipesys CLK_IPE_GALS_IPE>; 495 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 496 "ipe-smi", "ipe-gals"; 497 mediatek,infracfg = <&infracfg_ao>; 498 #power-domain-cells = <0>; 499 }; 500 501 power-domain@MT8186_POWER_DOMAIN_VENC { 502 reg = <MT8186_POWER_DOMAIN_VENC>; 503 clocks = <&topckgen CLK_TOP_VENC>, 504 <&vencsys CLK_VENC_CKE1_VENC>; 505 clock-names = "venc0", "larb"; 506 mediatek,infracfg = <&infracfg_ao>; 507 #power-domain-cells = <0>; 508 }; 509 510 power-domain@MT8186_POWER_DOMAIN_WPE { 511 reg = <MT8186_POWER_DOMAIN_WPE>; 512 clocks = <&topckgen CLK_TOP_WPE>, 513 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 514 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 515 clock-names = "wpe0", "larb-ck", "larb-pclk"; 516 mediatek,infracfg = <&infracfg_ao>; 517 #power-domain-cells = <0>; 518 }; 519 }; 520 }; 521 }; 522 523 watchdog: watchdog@10007000 { 524 compatible = "mediatek,mt8186-wdt", 525 "mediatek,mt6589-wdt"; 526 mediatek,disable-extrst; 527 reg = <0 0x10007000 0 0x1000>; 528 #reset-cells = <1>; 529 }; 530 531 apmixedsys: syscon@1000c000 { 532 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 533 reg = <0 0x1000c000 0 0x1000>; 534 #clock-cells = <1>; 535 }; 536 537 pwrap: pwrap@1000d000 { 538 compatible = "mediatek,mt8186-pwrap", "syscon"; 539 reg = <0 0x1000d000 0 0x1000>; 540 reg-names = "pwrap"; 541 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 542 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 543 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 544 clock-names = "spi", "wrap"; 545 }; 546 547 systimer: timer@10017000 { 548 compatible = "mediatek,mt8186-timer", 549 "mediatek,mt6765-timer"; 550 reg = <0 0x10017000 0 0x1000>; 551 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 552 clocks = <&clk13m>; 553 }; 554 555 scp: scp@10500000 { 556 compatible = "mediatek,mt8186-scp"; 557 reg = <0 0x10500000 0 0x40000>, 558 <0 0x105c0000 0 0x19080>; 559 reg-names = "sram", "cfg"; 560 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 561 }; 562 563 nor_flash: spi@11000000 { 564 compatible = "mediatek,mt8186-nor"; 565 reg = <0 0x11000000 0 0x1000>; 566 clocks = <&topckgen CLK_TOP_SPINOR>, 567 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 568 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 569 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 570 clock-names = "spi", "sf", "axi", "axi_s"; 571 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 572 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 573 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 574 status = "disabled"; 575 }; 576 577 auxadc: adc@11001000 { 578 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 579 reg = <0 0x11001000 0 0x1000>; 580 #io-channel-cells = <1>; 581 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 582 clock-names = "main"; 583 }; 584 585 uart0: serial@11002000 { 586 compatible = "mediatek,mt8186-uart", 587 "mediatek,mt6577-uart"; 588 reg = <0 0x11002000 0 0x1000>; 589 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 590 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 591 clock-names = "baud", "bus"; 592 status = "disabled"; 593 }; 594 595 uart1: serial@11003000 { 596 compatible = "mediatek,mt8186-uart", 597 "mediatek,mt6577-uart"; 598 reg = <0 0x11003000 0 0x1000>; 599 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 600 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 601 clock-names = "baud", "bus"; 602 status = "disabled"; 603 }; 604 605 i2c0: i2c@11007000 { 606 compatible = "mediatek,mt8186-i2c"; 607 reg = <0 0x11007000 0 0x1000>, 608 <0 0x10200100 0 0x100>; 609 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 610 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 611 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 612 clock-names = "main", "dma"; 613 clock-div = <1>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 status = "disabled"; 617 }; 618 619 i2c1: i2c@11008000 { 620 compatible = "mediatek,mt8186-i2c"; 621 reg = <0 0x11008000 0 0x1000>, 622 <0 0x10200200 0 0x100>; 623 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 624 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 625 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 626 clock-names = "main", "dma"; 627 clock-div = <1>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 i2c2: i2c@11009000 { 634 compatible = "mediatek,mt8186-i2c"; 635 reg = <0 0x11009000 0 0x1000>, 636 <0 0x10200300 0 0x180>; 637 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 638 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 639 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 640 clock-names = "main", "dma"; 641 clock-div = <1>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 i2c3: i2c@1100f000 { 648 compatible = "mediatek,mt8186-i2c"; 649 reg = <0 0x1100f000 0 0x1000>, 650 <0 0x10200480 0 0x100>; 651 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 652 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 653 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 654 clock-names = "main", "dma"; 655 clock-div = <1>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 status = "disabled"; 659 }; 660 661 i2c4: i2c@11011000 { 662 compatible = "mediatek,mt8186-i2c"; 663 reg = <0 0x11011000 0 0x1000>, 664 <0 0x10200580 0 0x180>; 665 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 666 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 667 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 668 clock-names = "main", "dma"; 669 clock-div = <1>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 i2c5: i2c@11016000 { 676 compatible = "mediatek,mt8186-i2c"; 677 reg = <0 0x11016000 0 0x1000>, 678 <0 0x10200700 0 0x100>; 679 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 680 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 681 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 682 clock-names = "main", "dma"; 683 clock-div = <1>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 i2c6: i2c@1100d000 { 690 compatible = "mediatek,mt8186-i2c"; 691 reg = <0 0x1100d000 0 0x1000>, 692 <0 0x10200800 0 0x100>; 693 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 694 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 695 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 696 clock-names = "main", "dma"; 697 clock-div = <1>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 i2c7: i2c@11004000 { 704 compatible = "mediatek,mt8186-i2c"; 705 reg = <0 0x11004000 0 0x1000>, 706 <0 0x10200900 0 0x180>; 707 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 708 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 709 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 710 clock-names = "main", "dma"; 711 clock-div = <1>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 status = "disabled"; 715 }; 716 717 i2c8: i2c@11005000 { 718 compatible = "mediatek,mt8186-i2c"; 719 reg = <0 0x11005000 0 0x1000>, 720 <0 0x10200A80 0 0x180>; 721 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 722 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 723 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 724 clock-names = "main", "dma"; 725 clock-div = <1>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 status = "disabled"; 729 }; 730 731 spi0: spi@1100a000 { 732 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 reg = <0 0x1100a000 0 0x1000>; 736 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 737 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 738 <&topckgen CLK_TOP_SPI>, 739 <&infracfg_ao CLK_INFRA_AO_SPI0>; 740 clock-names = "parent-clk", "sel-clk", "spi-clk"; 741 status = "disabled"; 742 }; 743 744 pwm0: pwm@1100e000 { 745 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 746 reg = <0 0x1100e000 0 0x1000>; 747 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 748 #pwm-cells = <2>; 749 clocks = <&topckgen CLK_TOP_DISP_PWM>, 750 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 751 clock-names = "main", "mm"; 752 status = "disabled"; 753 }; 754 755 spi1: spi@11010000 { 756 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 reg = <0 0x11010000 0 0x1000>; 760 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 761 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 762 <&topckgen CLK_TOP_SPI>, 763 <&infracfg_ao CLK_INFRA_AO_SPI1>; 764 clock-names = "parent-clk", "sel-clk", "spi-clk"; 765 status = "disabled"; 766 }; 767 768 spi2: spi@11012000 { 769 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 reg = <0 0x11012000 0 0x1000>; 773 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 774 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 775 <&topckgen CLK_TOP_SPI>, 776 <&infracfg_ao CLK_INFRA_AO_SPI2>; 777 clock-names = "parent-clk", "sel-clk", "spi-clk"; 778 status = "disabled"; 779 }; 780 781 spi3: spi@11013000 { 782 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 reg = <0 0x11013000 0 0x1000>; 786 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 787 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 788 <&topckgen CLK_TOP_SPI>, 789 <&infracfg_ao CLK_INFRA_AO_SPI3>; 790 clock-names = "parent-clk", "sel-clk", "spi-clk"; 791 status = "disabled"; 792 }; 793 794 spi4: spi@11014000 { 795 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 reg = <0 0x11014000 0 0x1000>; 799 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 800 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 801 <&topckgen CLK_TOP_SPI>, 802 <&infracfg_ao CLK_INFRA_AO_SPI4>; 803 clock-names = "parent-clk", "sel-clk", "spi-clk"; 804 status = "disabled"; 805 }; 806 807 spi5: spi@11015000 { 808 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 reg = <0 0x11015000 0 0x1000>; 812 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 813 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 814 <&topckgen CLK_TOP_SPI>, 815 <&infracfg_ao CLK_INFRA_AO_SPI5>; 816 clock-names = "parent-clk", "sel-clk", "spi-clk"; 817 status = "disabled"; 818 }; 819 820 imp_iic_wrap: clock-controller@11017000 { 821 compatible = "mediatek,mt8186-imp_iic_wrap"; 822 reg = <0 0x11017000 0 0x1000>; 823 #clock-cells = <1>; 824 }; 825 826 uart2: serial@11018000 { 827 compatible = "mediatek,mt8186-uart", 828 "mediatek,mt6577-uart"; 829 reg = <0 0x11018000 0 0x1000>; 830 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 831 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 832 clock-names = "baud", "bus"; 833 status = "disabled"; 834 }; 835 836 i2c9: i2c@11019000 { 837 compatible = "mediatek,mt8186-i2c"; 838 reg = <0 0x11019000 0 0x1000>, 839 <0 0x10200c00 0 0x180>; 840 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 841 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 842 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 843 clock-names = "main", "dma"; 844 clock-div = <1>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 mmc0: mmc@11230000 { 851 compatible = "mediatek,mt8186-mmc", 852 "mediatek,mt8183-mmc"; 853 reg = <0 0x11230000 0 0x1000>, 854 <0 0x11cd0000 0 0x1000>; 855 clocks = <&topckgen CLK_TOP_MSDC50_0>, 856 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 857 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 858 clock-names = "source", "hclk", "source_cg"; 859 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 860 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 861 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 862 status = "disabled"; 863 }; 864 865 mmc1: mmc@11240000 { 866 compatible = "mediatek,mt8186-mmc", 867 "mediatek,mt8183-mmc"; 868 reg = <0 0x11240000 0 0x1000>, 869 <0 0x11c90000 0 0x1000>; 870 clocks = <&topckgen CLK_TOP_MSDC30_1>, 871 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 872 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 873 clock-names = "source", "hclk", "source_cg"; 874 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 875 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 876 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 877 status = "disabled"; 878 }; 879 880 u3phy0: t-phy@11c80000 { 881 compatible = "mediatek,mt8186-tphy", 882 "mediatek,generic-tphy-v2"; 883 #address-cells = <1>; 884 #size-cells = <1>; 885 ranges = <0x0 0x0 0x11c80000 0x1000>; 886 status = "disabled"; 887 888 u2port1: usb-phy@0 { 889 reg = <0x0 0x700>; 890 clocks = <&clk26m>; 891 clock-names = "ref"; 892 #phy-cells = <1>; 893 }; 894 895 u3port1: usb-phy@700 { 896 reg = <0x700 0x900>; 897 clocks = <&clk26m>; 898 clock-names = "ref"; 899 #phy-cells = <1>; 900 }; 901 }; 902 903 u3phy1: t-phy@11ca0000 { 904 compatible = "mediatek,mt8186-tphy", 905 "mediatek,generic-tphy-v2"; 906 #address-cells = <1>; 907 #size-cells = <1>; 908 ranges = <0x0 0x0 0x11ca0000 0x1000>; 909 status = "disabled"; 910 911 u2port0: usb-phy@0 { 912 reg = <0x0 0x700>; 913 clocks = <&clk26m>; 914 clock-names = "ref"; 915 #phy-cells = <1>; 916 mediatek,discth = <0x8>; 917 }; 918 }; 919 920 efuse: efuse@11cb0000 { 921 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 922 reg = <0 0x11cb0000 0 0x1000>; 923 #address-cells = <1>; 924 #size-cells = <1>; 925 }; 926 927 mipi_tx0: dsi-phy@11cc0000 { 928 compatible = "mediatek,mt8183-mipi-tx"; 929 reg = <0 0x11cc0000 0 0x1000>; 930 clocks = <&clk26m>; 931 #clock-cells = <0>; 932 #phy-cells = <0>; 933 clock-output-names = "mipi_tx0_pll"; 934 status = "disabled"; 935 }; 936 937 mfgsys: clock-controller@13000000 { 938 compatible = "mediatek,mt8186-mfgsys"; 939 reg = <0 0x13000000 0 0x1000>; 940 #clock-cells = <1>; 941 }; 942 943 mmsys: syscon@14000000 { 944 compatible = "mediatek,mt8186-mmsys", "syscon"; 945 reg = <0 0x14000000 0 0x1000>; 946 #clock-cells = <1>; 947 #reset-cells = <1>; 948 }; 949 950 wpesys: clock-controller@14020000 { 951 compatible = "mediatek,mt8186-wpesys"; 952 reg = <0 0x14020000 0 0x1000>; 953 #clock-cells = <1>; 954 }; 955 956 imgsys1: clock-controller@15020000 { 957 compatible = "mediatek,mt8186-imgsys1"; 958 reg = <0 0x15020000 0 0x1000>; 959 #clock-cells = <1>; 960 }; 961 962 imgsys2: clock-controller@15820000 { 963 compatible = "mediatek,mt8186-imgsys2"; 964 reg = <0 0x15820000 0 0x1000>; 965 #clock-cells = <1>; 966 }; 967 968 vdecsys: clock-controller@1602f000 { 969 compatible = "mediatek,mt8186-vdecsys"; 970 reg = <0 0x1602f000 0 0x1000>; 971 #clock-cells = <1>; 972 }; 973 974 vencsys: clock-controller@17000000 { 975 compatible = "mediatek,mt8186-vencsys"; 976 reg = <0 0x17000000 0 0x1000>; 977 #clock-cells = <1>; 978 }; 979 980 camsys: clock-controller@1a000000 { 981 compatible = "mediatek,mt8186-camsys"; 982 reg = <0 0x1a000000 0 0x1000>; 983 #clock-cells = <1>; 984 }; 985 986 camsys_rawa: clock-controller@1a04f000 { 987 compatible = "mediatek,mt8186-camsys_rawa"; 988 reg = <0 0x1a04f000 0 0x1000>; 989 #clock-cells = <1>; 990 }; 991 992 camsys_rawb: clock-controller@1a06f000 { 993 compatible = "mediatek,mt8186-camsys_rawb"; 994 reg = <0 0x1a06f000 0 0x1000>; 995 #clock-cells = <1>; 996 }; 997 998 mdpsys: clock-controller@1b000000 { 999 compatible = "mediatek,mt8186-mdpsys"; 1000 reg = <0 0x1b000000 0 0x1000>; 1001 #clock-cells = <1>; 1002 }; 1003 1004 ipesys: clock-controller@1c000000 { 1005 compatible = "mediatek,mt8186-ipesys"; 1006 reg = <0 0x1c000000 0 0x1000>; 1007 #clock-cells = <1>; 1008 }; 1009 }; 1010}; 1011