1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/memory/mt8186-memory-port.h> 11#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 12#include <dt-bindings/power/mt8186-power.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/mt8186-resets.h> 15 16/ { 17 compatible = "mediatek,mt8186"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 44 core4 { 45 cpu = <&cpu4>; 46 }; 47 48 core5 { 49 cpu = <&cpu5>; 50 }; 51 }; 52 53 cluster1 { 54 core0 { 55 cpu = <&cpu6>; 56 }; 57 58 core1 { 59 cpu = <&cpu7>; 60 }; 61 }; 62 }; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x000>; 68 enable-method = "psci"; 69 clock-frequency = <2000000000>; 70 capacity-dmips-mhz = <382>; 71 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 72 next-level-cache = <&l2_0>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x100>; 80 enable-method = "psci"; 81 clock-frequency = <2000000000>; 82 capacity-dmips-mhz = <382>; 83 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 84 next-level-cache = <&l2_0>; 85 #cooling-cells = <2>; 86 }; 87 88 cpu2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a55"; 91 reg = <0x200>; 92 enable-method = "psci"; 93 clock-frequency = <2000000000>; 94 capacity-dmips-mhz = <382>; 95 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 96 next-level-cache = <&l2_0>; 97 #cooling-cells = <2>; 98 }; 99 100 cpu3: cpu@300 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a55"; 103 reg = <0x300>; 104 enable-method = "psci"; 105 clock-frequency = <2000000000>; 106 capacity-dmips-mhz = <382>; 107 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 108 next-level-cache = <&l2_0>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x400>; 116 enable-method = "psci"; 117 clock-frequency = <2000000000>; 118 capacity-dmips-mhz = <382>; 119 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 120 next-level-cache = <&l2_0>; 121 #cooling-cells = <2>; 122 }; 123 124 cpu5: cpu@500 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a55"; 127 reg = <0x500>; 128 enable-method = "psci"; 129 clock-frequency = <2000000000>; 130 capacity-dmips-mhz = <382>; 131 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 132 next-level-cache = <&l2_0>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu6: cpu@600 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a76"; 139 reg = <0x600>; 140 enable-method = "psci"; 141 clock-frequency = <2050000000>; 142 capacity-dmips-mhz = <1024>; 143 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu7: cpu@700 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a76"; 151 reg = <0x700>; 152 enable-method = "psci"; 153 clock-frequency = <2050000000>; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 156 next-level-cache = <&l2_1>; 157 #cooling-cells = <2>; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 cpu_off_l: cpu-off-l { 164 compatible = "arm,idle-state"; 165 arm,psci-suspend-param = <0x00010001>; 166 local-timer-stop; 167 entry-latency-us = <50>; 168 exit-latency-us = <100>; 169 min-residency-us = <1600>; 170 }; 171 172 cpu_off_b: cpu-off-b { 173 compatible = "arm,idle-state"; 174 arm,psci-suspend-param = <0x00010001>; 175 local-timer-stop; 176 entry-latency-us = <50>; 177 exit-latency-us = <100>; 178 min-residency-us = <1400>; 179 }; 180 181 cluster_off_l: cluster-off-l { 182 compatible = "arm,idle-state"; 183 arm,psci-suspend-param = <0x01010001>; 184 local-timer-stop; 185 entry-latency-us = <100>; 186 exit-latency-us = <250>; 187 min-residency-us = <2100>; 188 }; 189 190 cluster_off_b: cluster-off-b { 191 compatible = "arm,idle-state"; 192 arm,psci-suspend-param = <0x01010001>; 193 local-timer-stop; 194 entry-latency-us = <100>; 195 exit-latency-us = <250>; 196 min-residency-us = <1900>; 197 }; 198 }; 199 200 l2_0: l2-cache0 { 201 compatible = "cache"; 202 cache-level = <2>; 203 next-level-cache = <&l3_0>; 204 }; 205 206 l2_1: l2-cache1 { 207 compatible = "cache"; 208 cache-level = <2>; 209 next-level-cache = <&l3_0>; 210 }; 211 212 l3_0: l3-cache { 213 compatible = "cache"; 214 cache-level = <3>; 215 }; 216 }; 217 218 clk13m: oscillator-13m { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <13000000>; 222 clock-output-names = "clk13m"; 223 }; 224 225 clk26m: oscillator-26m { 226 compatible = "fixed-clock"; 227 #clock-cells = <0>; 228 clock-frequency = <26000000>; 229 clock-output-names = "clk26m"; 230 }; 231 232 clk32k: oscillator-32k { 233 compatible = "fixed-clock"; 234 #clock-cells = <0>; 235 clock-frequency = <32768>; 236 clock-output-names = "clk32k"; 237 }; 238 239 pmu-a55 { 240 compatible = "arm,cortex-a55-pmu"; 241 interrupt-parent = <&gic>; 242 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 243 }; 244 245 pmu-a76 { 246 compatible = "arm,cortex-a76-pmu"; 247 interrupt-parent = <&gic>; 248 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 249 }; 250 251 psci { 252 compatible = "arm,psci-1.0"; 253 method = "smc"; 254 }; 255 256 timer { 257 compatible = "arm,armv8-timer"; 258 interrupt-parent = <&gic>; 259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 260 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 261 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 262 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 263 }; 264 265 soc { 266 #address-cells = <2>; 267 #size-cells = <2>; 268 compatible = "simple-bus"; 269 ranges; 270 271 gic: interrupt-controller@c000000 { 272 compatible = "arm,gic-v3"; 273 #interrupt-cells = <4>; 274 #redistributor-regions = <1>; 275 interrupt-parent = <&gic>; 276 interrupt-controller; 277 reg = <0 0x0c000000 0 0x40000>, 278 <0 0x0c040000 0 0x200000>; 279 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 280 281 ppi-partitions { 282 ppi_cluster0: interrupt-partition-0 { 283 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 284 }; 285 286 ppi_cluster1: interrupt-partition-1 { 287 affinity = <&cpu6 &cpu7>; 288 }; 289 }; 290 }; 291 292 mcusys: syscon@c53a000 { 293 compatible = "mediatek,mt8186-mcusys", "syscon"; 294 reg = <0 0xc53a000 0 0x1000>; 295 #clock-cells = <1>; 296 }; 297 298 topckgen: syscon@10000000 { 299 compatible = "mediatek,mt8186-topckgen", "syscon"; 300 reg = <0 0x10000000 0 0x1000>; 301 #clock-cells = <1>; 302 }; 303 304 infracfg_ao: syscon@10001000 { 305 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 306 reg = <0 0x10001000 0 0x1000>; 307 #clock-cells = <1>; 308 #reset-cells = <1>; 309 }; 310 311 pericfg: syscon@10003000 { 312 compatible = "mediatek,mt8186-pericfg", "syscon"; 313 reg = <0 0x10003000 0 0x1000>; 314 }; 315 316 pio: pinctrl@10005000 { 317 compatible = "mediatek,mt8186-pinctrl"; 318 reg = <0 0x10005000 0 0x1000>, 319 <0 0x10002000 0 0x0200>, 320 <0 0x10002200 0 0x0200>, 321 <0 0x10002400 0 0x0200>, 322 <0 0x10002600 0 0x0200>, 323 <0 0x10002a00 0 0x0200>, 324 <0 0x10002c00 0 0x0200>, 325 <0 0x1000b000 0 0x1000>; 326 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 327 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 328 gpio-controller; 329 #gpio-cells = <2>; 330 gpio-ranges = <&pio 0 0 185>; 331 interrupt-controller; 332 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 333 #interrupt-cells = <2>; 334 }; 335 336 scpsys: syscon@10006000 { 337 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 338 reg = <0 0x10006000 0 0x1000>; 339 340 /* System Power Manager */ 341 spm: power-controller { 342 compatible = "mediatek,mt8186-power-controller"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 #power-domain-cells = <1>; 346 347 /* power domain of the SoC */ 348 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 349 reg = <MT8186_POWER_DOMAIN_MFG0>; 350 clocks = <&topckgen CLK_TOP_MFG>; 351 clock-names = "mfg00"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 #power-domain-cells = <1>; 355 356 power-domain@MT8186_POWER_DOMAIN_MFG1 { 357 reg = <MT8186_POWER_DOMAIN_MFG1>; 358 mediatek,infracfg = <&infracfg_ao>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 #power-domain-cells = <1>; 362 363 power-domain@MT8186_POWER_DOMAIN_MFG2 { 364 reg = <MT8186_POWER_DOMAIN_MFG2>; 365 #power-domain-cells = <0>; 366 }; 367 368 power-domain@MT8186_POWER_DOMAIN_MFG3 { 369 reg = <MT8186_POWER_DOMAIN_MFG3>; 370 #power-domain-cells = <0>; 371 }; 372 }; 373 }; 374 375 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 376 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 377 clocks = <&topckgen CLK_TOP_SENINF>, 378 <&topckgen CLK_TOP_SENINF1>; 379 clock-names = "csirx_top0", "csirx_top1"; 380 #power-domain-cells = <0>; 381 }; 382 383 power-domain@MT8186_POWER_DOMAIN_SSUSB { 384 reg = <MT8186_POWER_DOMAIN_SSUSB>; 385 #power-domain-cells = <0>; 386 }; 387 388 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 389 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 390 #power-domain-cells = <0>; 391 }; 392 393 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 394 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 395 clocks = <&topckgen CLK_TOP_AUDIODSP>, 396 <&topckgen CLK_TOP_ADSP_BUS>; 397 clock-names = "audioadsp", "adsp_bus"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 #power-domain-cells = <1>; 401 402 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 403 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 #power-domain-cells = <1>; 407 408 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 409 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 410 mediatek,infracfg = <&infracfg_ao>; 411 #power-domain-cells = <0>; 412 }; 413 }; 414 }; 415 416 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 417 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 418 mediatek,infracfg = <&infracfg_ao>; 419 #power-domain-cells = <0>; 420 }; 421 422 power-domain@MT8186_POWER_DOMAIN_DIS { 423 reg = <MT8186_POWER_DOMAIN_DIS>; 424 clocks = <&topckgen CLK_TOP_DISP>, 425 <&topckgen CLK_TOP_MDP>, 426 <&mmsys CLK_MM_SMI_INFRA>, 427 <&mmsys CLK_MM_SMI_COMMON>, 428 <&mmsys CLK_MM_SMI_GALS>, 429 <&mmsys CLK_MM_SMI_IOMMU>; 430 clock-names = "disp", "mdp", "smi_infra", "smi_common", 431 "smi_gals", "smi_iommu"; 432 mediatek,infracfg = <&infracfg_ao>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 #power-domain-cells = <1>; 436 437 power-domain@MT8186_POWER_DOMAIN_VDEC { 438 reg = <MT8186_POWER_DOMAIN_VDEC>; 439 clocks = <&topckgen CLK_TOP_VDEC>, 440 <&vdecsys CLK_VDEC_LARB1_CKEN>; 441 clock-names = "vdec0", "larb"; 442 mediatek,infracfg = <&infracfg_ao>; 443 #power-domain-cells = <0>; 444 }; 445 446 power-domain@MT8186_POWER_DOMAIN_CAM { 447 reg = <MT8186_POWER_DOMAIN_CAM>; 448 clocks = <&topckgen CLK_TOP_CAM>, 449 <&topckgen CLK_TOP_SENINF>, 450 <&topckgen CLK_TOP_SENINF1>, 451 <&topckgen CLK_TOP_SENINF2>, 452 <&topckgen CLK_TOP_SENINF3>, 453 <&topckgen CLK_TOP_CAMTM>, 454 <&camsys CLK_CAM2MM_GALS>; 455 clock-names = "cam-top", "cam0", "cam1", "cam2", 456 "cam3", "cam-tm", "gals"; 457 mediatek,infracfg = <&infracfg_ao>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 #power-domain-cells = <1>; 461 462 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 463 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 464 #power-domain-cells = <0>; 465 }; 466 467 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 468 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 469 #power-domain-cells = <0>; 470 }; 471 }; 472 473 power-domain@MT8186_POWER_DOMAIN_IMG { 474 reg = <MT8186_POWER_DOMAIN_IMG>; 475 clocks = <&topckgen CLK_TOP_IMG1>, 476 <&imgsys1 CLK_IMG1_GALS_IMG1>; 477 clock-names = "img-top", "gals"; 478 mediatek,infracfg = <&infracfg_ao>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 #power-domain-cells = <1>; 482 483 power-domain@MT8186_POWER_DOMAIN_IMG2 { 484 reg = <MT8186_POWER_DOMAIN_IMG2>; 485 #power-domain-cells = <0>; 486 }; 487 }; 488 489 power-domain@MT8186_POWER_DOMAIN_IPE { 490 reg = <MT8186_POWER_DOMAIN_IPE>; 491 clocks = <&topckgen CLK_TOP_IPE>, 492 <&ipesys CLK_IPE_LARB19>, 493 <&ipesys CLK_IPE_LARB20>, 494 <&ipesys CLK_IPE_SMI_SUBCOM>, 495 <&ipesys CLK_IPE_GALS_IPE>; 496 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 497 "ipe-smi", "ipe-gals"; 498 mediatek,infracfg = <&infracfg_ao>; 499 #power-domain-cells = <0>; 500 }; 501 502 power-domain@MT8186_POWER_DOMAIN_VENC { 503 reg = <MT8186_POWER_DOMAIN_VENC>; 504 clocks = <&topckgen CLK_TOP_VENC>, 505 <&vencsys CLK_VENC_CKE1_VENC>; 506 clock-names = "venc0", "larb"; 507 mediatek,infracfg = <&infracfg_ao>; 508 #power-domain-cells = <0>; 509 }; 510 511 power-domain@MT8186_POWER_DOMAIN_WPE { 512 reg = <MT8186_POWER_DOMAIN_WPE>; 513 clocks = <&topckgen CLK_TOP_WPE>, 514 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 515 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 516 clock-names = "wpe0", "larb-ck", "larb-pclk"; 517 mediatek,infracfg = <&infracfg_ao>; 518 #power-domain-cells = <0>; 519 }; 520 }; 521 }; 522 }; 523 524 watchdog: watchdog@10007000 { 525 compatible = "mediatek,mt8186-wdt", 526 "mediatek,mt6589-wdt"; 527 mediatek,disable-extrst; 528 reg = <0 0x10007000 0 0x1000>; 529 #reset-cells = <1>; 530 }; 531 532 apmixedsys: syscon@1000c000 { 533 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 534 reg = <0 0x1000c000 0 0x1000>; 535 #clock-cells = <1>; 536 }; 537 538 pwrap: pwrap@1000d000 { 539 compatible = "mediatek,mt8186-pwrap", "syscon"; 540 reg = <0 0x1000d000 0 0x1000>; 541 reg-names = "pwrap"; 542 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 543 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 544 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 545 clock-names = "spi", "wrap"; 546 }; 547 548 systimer: timer@10017000 { 549 compatible = "mediatek,mt8186-timer", 550 "mediatek,mt6765-timer"; 551 reg = <0 0x10017000 0 0x1000>; 552 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 553 clocks = <&clk13m>; 554 }; 555 556 scp: scp@10500000 { 557 compatible = "mediatek,mt8186-scp"; 558 reg = <0 0x10500000 0 0x40000>, 559 <0 0x105c0000 0 0x19080>; 560 reg-names = "sram", "cfg"; 561 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 562 }; 563 564 nor_flash: spi@11000000 { 565 compatible = "mediatek,mt8186-nor"; 566 reg = <0 0x11000000 0 0x1000>; 567 clocks = <&topckgen CLK_TOP_SPINOR>, 568 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 569 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 570 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 571 clock-names = "spi", "sf", "axi", "axi_s"; 572 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 573 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 574 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 575 status = "disabled"; 576 }; 577 578 auxadc: adc@11001000 { 579 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 580 reg = <0 0x11001000 0 0x1000>; 581 #io-channel-cells = <1>; 582 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 583 clock-names = "main"; 584 }; 585 586 uart0: serial@11002000 { 587 compatible = "mediatek,mt8186-uart", 588 "mediatek,mt6577-uart"; 589 reg = <0 0x11002000 0 0x1000>; 590 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 591 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 592 clock-names = "baud", "bus"; 593 status = "disabled"; 594 }; 595 596 uart1: serial@11003000 { 597 compatible = "mediatek,mt8186-uart", 598 "mediatek,mt6577-uart"; 599 reg = <0 0x11003000 0 0x1000>; 600 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 601 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 602 clock-names = "baud", "bus"; 603 status = "disabled"; 604 }; 605 606 i2c0: i2c@11007000 { 607 compatible = "mediatek,mt8186-i2c"; 608 reg = <0 0x11007000 0 0x1000>, 609 <0 0x10200100 0 0x100>; 610 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 611 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 612 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 613 clock-names = "main", "dma"; 614 clock-div = <1>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 i2c1: i2c@11008000 { 621 compatible = "mediatek,mt8186-i2c"; 622 reg = <0 0x11008000 0 0x1000>, 623 <0 0x10200200 0 0x100>; 624 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 625 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 626 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 627 clock-names = "main", "dma"; 628 clock-div = <1>; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 status = "disabled"; 632 }; 633 634 i2c2: i2c@11009000 { 635 compatible = "mediatek,mt8186-i2c"; 636 reg = <0 0x11009000 0 0x1000>, 637 <0 0x10200300 0 0x180>; 638 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 639 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 640 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 641 clock-names = "main", "dma"; 642 clock-div = <1>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 i2c3: i2c@1100f000 { 649 compatible = "mediatek,mt8186-i2c"; 650 reg = <0 0x1100f000 0 0x1000>, 651 <0 0x10200480 0 0x100>; 652 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 653 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 654 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 655 clock-names = "main", "dma"; 656 clock-div = <1>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 i2c4: i2c@11011000 { 663 compatible = "mediatek,mt8186-i2c"; 664 reg = <0 0x11011000 0 0x1000>, 665 <0 0x10200580 0 0x180>; 666 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 667 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 668 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 669 clock-names = "main", "dma"; 670 clock-div = <1>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 status = "disabled"; 674 }; 675 676 i2c5: i2c@11016000 { 677 compatible = "mediatek,mt8186-i2c"; 678 reg = <0 0x11016000 0 0x1000>, 679 <0 0x10200700 0 0x100>; 680 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 681 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 682 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 683 clock-names = "main", "dma"; 684 clock-div = <1>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 status = "disabled"; 688 }; 689 690 i2c6: i2c@1100d000 { 691 compatible = "mediatek,mt8186-i2c"; 692 reg = <0 0x1100d000 0 0x1000>, 693 <0 0x10200800 0 0x100>; 694 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 695 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 696 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 697 clock-names = "main", "dma"; 698 clock-div = <1>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 status = "disabled"; 702 }; 703 704 i2c7: i2c@11004000 { 705 compatible = "mediatek,mt8186-i2c"; 706 reg = <0 0x11004000 0 0x1000>, 707 <0 0x10200900 0 0x180>; 708 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 709 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 710 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 711 clock-names = "main", "dma"; 712 clock-div = <1>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 status = "disabled"; 716 }; 717 718 i2c8: i2c@11005000 { 719 compatible = "mediatek,mt8186-i2c"; 720 reg = <0 0x11005000 0 0x1000>, 721 <0 0x10200A80 0 0x180>; 722 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 723 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 724 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 725 clock-names = "main", "dma"; 726 clock-div = <1>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 }; 731 732 spi0: spi@1100a000 { 733 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 reg = <0 0x1100a000 0 0x1000>; 737 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 738 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 739 <&topckgen CLK_TOP_SPI>, 740 <&infracfg_ao CLK_INFRA_AO_SPI0>; 741 clock-names = "parent-clk", "sel-clk", "spi-clk"; 742 status = "disabled"; 743 }; 744 745 pwm0: pwm@1100e000 { 746 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 747 reg = <0 0x1100e000 0 0x1000>; 748 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 749 #pwm-cells = <2>; 750 clocks = <&topckgen CLK_TOP_DISP_PWM>, 751 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 752 clock-names = "main", "mm"; 753 status = "disabled"; 754 }; 755 756 spi1: spi@11010000 { 757 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 reg = <0 0x11010000 0 0x1000>; 761 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 762 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 763 <&topckgen CLK_TOP_SPI>, 764 <&infracfg_ao CLK_INFRA_AO_SPI1>; 765 clock-names = "parent-clk", "sel-clk", "spi-clk"; 766 status = "disabled"; 767 }; 768 769 spi2: spi@11012000 { 770 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 reg = <0 0x11012000 0 0x1000>; 774 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 775 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 776 <&topckgen CLK_TOP_SPI>, 777 <&infracfg_ao CLK_INFRA_AO_SPI2>; 778 clock-names = "parent-clk", "sel-clk", "spi-clk"; 779 status = "disabled"; 780 }; 781 782 spi3: spi@11013000 { 783 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 reg = <0 0x11013000 0 0x1000>; 787 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 788 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 789 <&topckgen CLK_TOP_SPI>, 790 <&infracfg_ao CLK_INFRA_AO_SPI3>; 791 clock-names = "parent-clk", "sel-clk", "spi-clk"; 792 status = "disabled"; 793 }; 794 795 spi4: spi@11014000 { 796 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 reg = <0 0x11014000 0 0x1000>; 800 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 801 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 802 <&topckgen CLK_TOP_SPI>, 803 <&infracfg_ao CLK_INFRA_AO_SPI4>; 804 clock-names = "parent-clk", "sel-clk", "spi-clk"; 805 status = "disabled"; 806 }; 807 808 spi5: spi@11015000 { 809 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 reg = <0 0x11015000 0 0x1000>; 813 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 814 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 815 <&topckgen CLK_TOP_SPI>, 816 <&infracfg_ao CLK_INFRA_AO_SPI5>; 817 clock-names = "parent-clk", "sel-clk", "spi-clk"; 818 status = "disabled"; 819 }; 820 821 imp_iic_wrap: clock-controller@11017000 { 822 compatible = "mediatek,mt8186-imp_iic_wrap"; 823 reg = <0 0x11017000 0 0x1000>; 824 #clock-cells = <1>; 825 }; 826 827 uart2: serial@11018000 { 828 compatible = "mediatek,mt8186-uart", 829 "mediatek,mt6577-uart"; 830 reg = <0 0x11018000 0 0x1000>; 831 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 832 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 833 clock-names = "baud", "bus"; 834 status = "disabled"; 835 }; 836 837 i2c9: i2c@11019000 { 838 compatible = "mediatek,mt8186-i2c"; 839 reg = <0 0x11019000 0 0x1000>, 840 <0 0x10200c00 0 0x180>; 841 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 842 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 843 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 844 clock-names = "main", "dma"; 845 clock-div = <1>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 status = "disabled"; 849 }; 850 851 mmc0: mmc@11230000 { 852 compatible = "mediatek,mt8186-mmc", 853 "mediatek,mt8183-mmc"; 854 reg = <0 0x11230000 0 0x1000>, 855 <0 0x11cd0000 0 0x1000>; 856 clocks = <&topckgen CLK_TOP_MSDC50_0>, 857 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 858 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 859 clock-names = "source", "hclk", "source_cg"; 860 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 861 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 862 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 863 status = "disabled"; 864 }; 865 866 mmc1: mmc@11240000 { 867 compatible = "mediatek,mt8186-mmc", 868 "mediatek,mt8183-mmc"; 869 reg = <0 0x11240000 0 0x1000>, 870 <0 0x11c90000 0 0x1000>; 871 clocks = <&topckgen CLK_TOP_MSDC30_1>, 872 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 873 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 874 clock-names = "source", "hclk", "source_cg"; 875 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 876 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 877 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 878 status = "disabled"; 879 }; 880 881 u3phy0: t-phy@11c80000 { 882 compatible = "mediatek,mt8186-tphy", 883 "mediatek,generic-tphy-v2"; 884 #address-cells = <1>; 885 #size-cells = <1>; 886 ranges = <0x0 0x0 0x11c80000 0x1000>; 887 status = "disabled"; 888 889 u2port1: usb-phy@0 { 890 reg = <0x0 0x700>; 891 clocks = <&clk26m>; 892 clock-names = "ref"; 893 #phy-cells = <1>; 894 }; 895 896 u3port1: usb-phy@700 { 897 reg = <0x700 0x900>; 898 clocks = <&clk26m>; 899 clock-names = "ref"; 900 #phy-cells = <1>; 901 }; 902 }; 903 904 u3phy1: t-phy@11ca0000 { 905 compatible = "mediatek,mt8186-tphy", 906 "mediatek,generic-tphy-v2"; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 ranges = <0x0 0x0 0x11ca0000 0x1000>; 910 status = "disabled"; 911 912 u2port0: usb-phy@0 { 913 reg = <0x0 0x700>; 914 clocks = <&clk26m>; 915 clock-names = "ref"; 916 #phy-cells = <1>; 917 mediatek,discth = <0x8>; 918 }; 919 }; 920 921 efuse: efuse@11cb0000 { 922 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 923 reg = <0 0x11cb0000 0 0x1000>; 924 #address-cells = <1>; 925 #size-cells = <1>; 926 }; 927 928 mipi_tx0: dsi-phy@11cc0000 { 929 compatible = "mediatek,mt8183-mipi-tx"; 930 reg = <0 0x11cc0000 0 0x1000>; 931 clocks = <&clk26m>; 932 #clock-cells = <0>; 933 #phy-cells = <0>; 934 clock-output-names = "mipi_tx0_pll"; 935 status = "disabled"; 936 }; 937 938 mfgsys: clock-controller@13000000 { 939 compatible = "mediatek,mt8186-mfgsys"; 940 reg = <0 0x13000000 0 0x1000>; 941 #clock-cells = <1>; 942 }; 943 944 mmsys: syscon@14000000 { 945 compatible = "mediatek,mt8186-mmsys", "syscon"; 946 reg = <0 0x14000000 0 0x1000>; 947 #clock-cells = <1>; 948 #reset-cells = <1>; 949 }; 950 951 smi_common: smi@14002000 { 952 compatible = "mediatek,mt8186-smi-common"; 953 reg = <0 0x14002000 0 0x1000>; 954 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 955 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 956 clock-names = "apb", "smi", "gals0", "gals1"; 957 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 958 }; 959 960 larb0: smi@14003000 { 961 compatible = "mediatek,mt8186-smi-larb"; 962 reg = <0 0x14003000 0 0x1000>; 963 clocks = <&mmsys CLK_MM_SMI_COMMON>, 964 <&mmsys CLK_MM_SMI_COMMON>; 965 clock-names = "apb", "smi"; 966 mediatek,larb-id = <0>; 967 mediatek,smi = <&smi_common>; 968 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 969 }; 970 971 larb1: smi@14004000 { 972 compatible = "mediatek,mt8186-smi-larb"; 973 reg = <0 0x14004000 0 0x1000>; 974 clocks = <&mmsys CLK_MM_SMI_COMMON>, 975 <&mmsys CLK_MM_SMI_COMMON>; 976 clock-names = "apb", "smi"; 977 mediatek,larb-id = <1>; 978 mediatek,smi = <&smi_common>; 979 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 980 }; 981 982 dsi0: dsi@14013000 { 983 compatible = "mediatek,mt8186-dsi"; 984 reg = <0 0x14013000 0 0x1000>; 985 clocks = <&mmsys CLK_MM_DSI0>, 986 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 987 <&mipi_tx0>; 988 clock-names = "engine", "digital", "hs"; 989 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 990 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 991 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 992 phys = <&mipi_tx0>; 993 phy-names = "dphy"; 994 status = "disabled"; 995 996 port { 997 dsi_out: endpoint { }; 998 }; 999 }; 1000 1001 iommu_mm: iommu@14016000 { 1002 compatible = "mediatek,mt8186-iommu-mm"; 1003 reg = <0 0x14016000 0 0x1000>; 1004 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1005 clock-names = "bclk"; 1006 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1007 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1008 &larb7 &larb8 &larb9 &larb11 1009 &larb13 &larb14 &larb16 &larb17 1010 &larb19 &larb20>; 1011 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1012 #iommu-cells = <1>; 1013 }; 1014 1015 wpesys: clock-controller@14020000 { 1016 compatible = "mediatek,mt8186-wpesys"; 1017 reg = <0 0x14020000 0 0x1000>; 1018 #clock-cells = <1>; 1019 }; 1020 1021 larb8: smi@14023000 { 1022 compatible = "mediatek,mt8186-smi-larb"; 1023 reg = <0 0x14023000 0 0x1000>; 1024 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1025 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1026 clock-names = "apb", "smi"; 1027 mediatek,larb-id = <8>; 1028 mediatek,smi = <&smi_common>; 1029 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1030 }; 1031 1032 imgsys1: clock-controller@15020000 { 1033 compatible = "mediatek,mt8186-imgsys1"; 1034 reg = <0 0x15020000 0 0x1000>; 1035 #clock-cells = <1>; 1036 }; 1037 1038 larb9: smi@1502e000 { 1039 compatible = "mediatek,mt8186-smi-larb"; 1040 reg = <0 0x1502e000 0 0x1000>; 1041 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1042 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1043 clock-names = "apb", "smi"; 1044 mediatek,larb-id = <9>; 1045 mediatek,smi = <&smi_common>; 1046 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1047 }; 1048 1049 imgsys2: clock-controller@15820000 { 1050 compatible = "mediatek,mt8186-imgsys2"; 1051 reg = <0 0x15820000 0 0x1000>; 1052 #clock-cells = <1>; 1053 }; 1054 1055 larb11: smi@1582e000 { 1056 compatible = "mediatek,mt8186-smi-larb"; 1057 reg = <0 0x1582e000 0 0x1000>; 1058 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1059 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1060 clock-names = "apb", "smi"; 1061 mediatek,larb-id = <11>; 1062 mediatek,smi = <&smi_common>; 1063 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1064 }; 1065 1066 larb4: smi@1602e000 { 1067 compatible = "mediatek,mt8186-smi-larb"; 1068 reg = <0 0x1602e000 0 0x1000>; 1069 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1070 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1071 clock-names = "apb", "smi"; 1072 mediatek,larb-id = <4>; 1073 mediatek,smi = <&smi_common>; 1074 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1075 }; 1076 1077 vdecsys: clock-controller@1602f000 { 1078 compatible = "mediatek,mt8186-vdecsys"; 1079 reg = <0 0x1602f000 0 0x1000>; 1080 #clock-cells = <1>; 1081 }; 1082 1083 vencsys: clock-controller@17000000 { 1084 compatible = "mediatek,mt8186-vencsys"; 1085 reg = <0 0x17000000 0 0x1000>; 1086 #clock-cells = <1>; 1087 }; 1088 1089 larb7: smi@17010000 { 1090 compatible = "mediatek,mt8186-smi-larb"; 1091 reg = <0 0x17010000 0 0x1000>; 1092 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1093 <&vencsys CLK_VENC_CKE1_VENC>; 1094 clock-names = "apb", "smi"; 1095 mediatek,larb-id = <7>; 1096 mediatek,smi = <&smi_common>; 1097 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1098 }; 1099 1100 camsys: clock-controller@1a000000 { 1101 compatible = "mediatek,mt8186-camsys"; 1102 reg = <0 0x1a000000 0 0x1000>; 1103 #clock-cells = <1>; 1104 }; 1105 1106 larb13: smi@1a001000 { 1107 compatible = "mediatek,mt8186-smi-larb"; 1108 reg = <0 0x1a001000 0 0x1000>; 1109 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1110 clock-names = "apb", "smi"; 1111 mediatek,larb-id = <13>; 1112 mediatek,smi = <&smi_common>; 1113 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1114 }; 1115 1116 larb14: smi@1a002000 { 1117 compatible = "mediatek,mt8186-smi-larb"; 1118 reg = <0 0x1a002000 0 0x1000>; 1119 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1120 clock-names = "apb", "smi"; 1121 mediatek,larb-id = <14>; 1122 mediatek,smi = <&smi_common>; 1123 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1124 }; 1125 1126 larb16: smi@1a00f000 { 1127 compatible = "mediatek,mt8186-smi-larb"; 1128 reg = <0 0x1a00f000 0 0x1000>; 1129 clocks = <&camsys CLK_CAM_LARB14>, 1130 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1131 clock-names = "apb", "smi"; 1132 mediatek,larb-id = <16>; 1133 mediatek,smi = <&smi_common>; 1134 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1135 }; 1136 1137 larb17: smi@1a010000 { 1138 compatible = "mediatek,mt8186-smi-larb"; 1139 reg = <0 0x1a010000 0 0x1000>; 1140 clocks = <&camsys CLK_CAM_LARB13>, 1141 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1142 clock-names = "apb", "smi"; 1143 mediatek,larb-id = <17>; 1144 mediatek,smi = <&smi_common>; 1145 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1146 }; 1147 1148 camsys_rawa: clock-controller@1a04f000 { 1149 compatible = "mediatek,mt8186-camsys_rawa"; 1150 reg = <0 0x1a04f000 0 0x1000>; 1151 #clock-cells = <1>; 1152 }; 1153 1154 camsys_rawb: clock-controller@1a06f000 { 1155 compatible = "mediatek,mt8186-camsys_rawb"; 1156 reg = <0 0x1a06f000 0 0x1000>; 1157 #clock-cells = <1>; 1158 }; 1159 1160 mdpsys: clock-controller@1b000000 { 1161 compatible = "mediatek,mt8186-mdpsys"; 1162 reg = <0 0x1b000000 0 0x1000>; 1163 #clock-cells = <1>; 1164 }; 1165 1166 larb2: smi@1b002000 { 1167 compatible = "mediatek,mt8186-smi-larb"; 1168 reg = <0 0x1b002000 0 0x1000>; 1169 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1170 clock-names = "apb", "smi"; 1171 mediatek,larb-id = <2>; 1172 mediatek,smi = <&smi_common>; 1173 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1174 }; 1175 1176 ipesys: clock-controller@1c000000 { 1177 compatible = "mediatek,mt8186-ipesys"; 1178 reg = <0 0x1c000000 0 0x1000>; 1179 #clock-cells = <1>; 1180 }; 1181 1182 larb20: smi@1c00f000 { 1183 compatible = "mediatek,mt8186-smi-larb"; 1184 reg = <0 0x1c00f000 0 0x1000>; 1185 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1186 clock-names = "apb", "smi"; 1187 mediatek,larb-id = <20>; 1188 mediatek,smi = <&smi_common>; 1189 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1190 }; 1191 1192 larb19: smi@1c10f000 { 1193 compatible = "mediatek,mt8186-smi-larb"; 1194 reg = <0 0x1c10f000 0 0x1000>; 1195 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1196 clock-names = "apb", "smi"; 1197 mediatek,larb-id = <19>; 1198 mediatek,smi = <&smi_common>; 1199 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1200 }; 1201 }; 1202}; 1203