1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/memory/mt8186-memory-port.h> 11#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 12#include <dt-bindings/power/mt8186-power.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/mt8186-resets.h> 15 16/ { 17 compatible = "mediatek,mt8186"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 44 core4 { 45 cpu = <&cpu4>; 46 }; 47 48 core5 { 49 cpu = <&cpu5>; 50 }; 51 }; 52 53 cluster1 { 54 core0 { 55 cpu = <&cpu6>; 56 }; 57 58 core1 { 59 cpu = <&cpu7>; 60 }; 61 }; 62 }; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x000>; 68 enable-method = "psci"; 69 clock-frequency = <2000000000>; 70 capacity-dmips-mhz = <382>; 71 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 72 next-level-cache = <&l2_0>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x100>; 80 enable-method = "psci"; 81 clock-frequency = <2000000000>; 82 capacity-dmips-mhz = <382>; 83 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 84 next-level-cache = <&l2_0>; 85 #cooling-cells = <2>; 86 }; 87 88 cpu2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a55"; 91 reg = <0x200>; 92 enable-method = "psci"; 93 clock-frequency = <2000000000>; 94 capacity-dmips-mhz = <382>; 95 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 96 next-level-cache = <&l2_0>; 97 #cooling-cells = <2>; 98 }; 99 100 cpu3: cpu@300 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a55"; 103 reg = <0x300>; 104 enable-method = "psci"; 105 clock-frequency = <2000000000>; 106 capacity-dmips-mhz = <382>; 107 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 108 next-level-cache = <&l2_0>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x400>; 116 enable-method = "psci"; 117 clock-frequency = <2000000000>; 118 capacity-dmips-mhz = <382>; 119 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 120 next-level-cache = <&l2_0>; 121 #cooling-cells = <2>; 122 }; 123 124 cpu5: cpu@500 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a55"; 127 reg = <0x500>; 128 enable-method = "psci"; 129 clock-frequency = <2000000000>; 130 capacity-dmips-mhz = <382>; 131 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 132 next-level-cache = <&l2_0>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu6: cpu@600 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a76"; 139 reg = <0x600>; 140 enable-method = "psci"; 141 clock-frequency = <2050000000>; 142 capacity-dmips-mhz = <1024>; 143 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu7: cpu@700 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a76"; 151 reg = <0x700>; 152 enable-method = "psci"; 153 clock-frequency = <2050000000>; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 156 next-level-cache = <&l2_1>; 157 #cooling-cells = <2>; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 cpu_off_l: cpu-off-l { 164 compatible = "arm,idle-state"; 165 arm,psci-suspend-param = <0x00010001>; 166 local-timer-stop; 167 entry-latency-us = <50>; 168 exit-latency-us = <100>; 169 min-residency-us = <1600>; 170 }; 171 172 cpu_off_b: cpu-off-b { 173 compatible = "arm,idle-state"; 174 arm,psci-suspend-param = <0x00010001>; 175 local-timer-stop; 176 entry-latency-us = <50>; 177 exit-latency-us = <100>; 178 min-residency-us = <1400>; 179 }; 180 181 cluster_off_l: cluster-off-l { 182 compatible = "arm,idle-state"; 183 arm,psci-suspend-param = <0x01010001>; 184 local-timer-stop; 185 entry-latency-us = <100>; 186 exit-latency-us = <250>; 187 min-residency-us = <2100>; 188 }; 189 190 cluster_off_b: cluster-off-b { 191 compatible = "arm,idle-state"; 192 arm,psci-suspend-param = <0x01010001>; 193 local-timer-stop; 194 entry-latency-us = <100>; 195 exit-latency-us = <250>; 196 min-residency-us = <1900>; 197 }; 198 }; 199 200 l2_0: l2-cache0 { 201 compatible = "cache"; 202 cache-level = <2>; 203 next-level-cache = <&l3_0>; 204 }; 205 206 l2_1: l2-cache1 { 207 compatible = "cache"; 208 cache-level = <2>; 209 next-level-cache = <&l3_0>; 210 }; 211 212 l3_0: l3-cache { 213 compatible = "cache"; 214 cache-level = <3>; 215 }; 216 }; 217 218 clk13m: fixed-factor-clock-13m { 219 compatible = "fixed-factor-clock"; 220 #clock-cells = <0>; 221 clocks = <&clk26m>; 222 clock-div = <2>; 223 clock-mult = <1>; 224 clock-output-names = "clk13m"; 225 }; 226 227 clk26m: oscillator-26m { 228 compatible = "fixed-clock"; 229 #clock-cells = <0>; 230 clock-frequency = <26000000>; 231 clock-output-names = "clk26m"; 232 }; 233 234 clk32k: oscillator-32k { 235 compatible = "fixed-clock"; 236 #clock-cells = <0>; 237 clock-frequency = <32768>; 238 clock-output-names = "clk32k"; 239 }; 240 241 pmu-a55 { 242 compatible = "arm,cortex-a55-pmu"; 243 interrupt-parent = <&gic>; 244 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 245 }; 246 247 pmu-a76 { 248 compatible = "arm,cortex-a76-pmu"; 249 interrupt-parent = <&gic>; 250 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 251 }; 252 253 psci { 254 compatible = "arm,psci-1.0"; 255 method = "smc"; 256 }; 257 258 timer { 259 compatible = "arm,armv8-timer"; 260 interrupt-parent = <&gic>; 261 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 262 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 263 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 264 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 265 }; 266 267 soc { 268 #address-cells = <2>; 269 #size-cells = <2>; 270 compatible = "simple-bus"; 271 ranges; 272 273 gic: interrupt-controller@c000000 { 274 compatible = "arm,gic-v3"; 275 #interrupt-cells = <4>; 276 #redistributor-regions = <1>; 277 interrupt-parent = <&gic>; 278 interrupt-controller; 279 reg = <0 0x0c000000 0 0x40000>, 280 <0 0x0c040000 0 0x200000>; 281 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 282 283 ppi-partitions { 284 ppi_cluster0: interrupt-partition-0 { 285 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 286 }; 287 288 ppi_cluster1: interrupt-partition-1 { 289 affinity = <&cpu6 &cpu7>; 290 }; 291 }; 292 }; 293 294 mcusys: syscon@c53a000 { 295 compatible = "mediatek,mt8186-mcusys", "syscon"; 296 reg = <0 0xc53a000 0 0x1000>; 297 #clock-cells = <1>; 298 }; 299 300 topckgen: syscon@10000000 { 301 compatible = "mediatek,mt8186-topckgen", "syscon"; 302 reg = <0 0x10000000 0 0x1000>; 303 #clock-cells = <1>; 304 }; 305 306 infracfg_ao: syscon@10001000 { 307 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 308 reg = <0 0x10001000 0 0x1000>; 309 #clock-cells = <1>; 310 #reset-cells = <1>; 311 }; 312 313 pericfg: syscon@10003000 { 314 compatible = "mediatek,mt8186-pericfg", "syscon"; 315 reg = <0 0x10003000 0 0x1000>; 316 }; 317 318 pio: pinctrl@10005000 { 319 compatible = "mediatek,mt8186-pinctrl"; 320 reg = <0 0x10005000 0 0x1000>, 321 <0 0x10002000 0 0x0200>, 322 <0 0x10002200 0 0x0200>, 323 <0 0x10002400 0 0x0200>, 324 <0 0x10002600 0 0x0200>, 325 <0 0x10002a00 0 0x0200>, 326 <0 0x10002c00 0 0x0200>, 327 <0 0x1000b000 0 0x1000>; 328 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 329 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 330 gpio-controller; 331 #gpio-cells = <2>; 332 gpio-ranges = <&pio 0 0 185>; 333 interrupt-controller; 334 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 335 #interrupt-cells = <2>; 336 }; 337 338 scpsys: syscon@10006000 { 339 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 340 reg = <0 0x10006000 0 0x1000>; 341 342 /* System Power Manager */ 343 spm: power-controller { 344 compatible = "mediatek,mt8186-power-controller"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 #power-domain-cells = <1>; 348 349 /* power domain of the SoC */ 350 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 351 reg = <MT8186_POWER_DOMAIN_MFG0>; 352 clocks = <&topckgen CLK_TOP_MFG>; 353 clock-names = "mfg00"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 #power-domain-cells = <1>; 357 358 power-domain@MT8186_POWER_DOMAIN_MFG1 { 359 reg = <MT8186_POWER_DOMAIN_MFG1>; 360 mediatek,infracfg = <&infracfg_ao>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 #power-domain-cells = <1>; 364 365 power-domain@MT8186_POWER_DOMAIN_MFG2 { 366 reg = <MT8186_POWER_DOMAIN_MFG2>; 367 #power-domain-cells = <0>; 368 }; 369 370 power-domain@MT8186_POWER_DOMAIN_MFG3 { 371 reg = <MT8186_POWER_DOMAIN_MFG3>; 372 #power-domain-cells = <0>; 373 }; 374 }; 375 }; 376 377 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 378 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 379 clocks = <&topckgen CLK_TOP_SENINF>, 380 <&topckgen CLK_TOP_SENINF1>; 381 clock-names = "csirx_top0", "csirx_top1"; 382 #power-domain-cells = <0>; 383 }; 384 385 power-domain@MT8186_POWER_DOMAIN_SSUSB { 386 reg = <MT8186_POWER_DOMAIN_SSUSB>; 387 #power-domain-cells = <0>; 388 }; 389 390 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 391 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 392 #power-domain-cells = <0>; 393 }; 394 395 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 396 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 397 clocks = <&topckgen CLK_TOP_AUDIODSP>, 398 <&topckgen CLK_TOP_ADSP_BUS>; 399 clock-names = "audioadsp", "adsp_bus"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 #power-domain-cells = <1>; 403 404 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 405 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 #power-domain-cells = <1>; 409 410 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 411 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 412 mediatek,infracfg = <&infracfg_ao>; 413 #power-domain-cells = <0>; 414 }; 415 }; 416 }; 417 418 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 419 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 420 mediatek,infracfg = <&infracfg_ao>; 421 #power-domain-cells = <0>; 422 }; 423 424 power-domain@MT8186_POWER_DOMAIN_DIS { 425 reg = <MT8186_POWER_DOMAIN_DIS>; 426 clocks = <&topckgen CLK_TOP_DISP>, 427 <&topckgen CLK_TOP_MDP>, 428 <&mmsys CLK_MM_SMI_INFRA>, 429 <&mmsys CLK_MM_SMI_COMMON>, 430 <&mmsys CLK_MM_SMI_GALS>, 431 <&mmsys CLK_MM_SMI_IOMMU>; 432 clock-names = "disp", "mdp", "smi_infra", "smi_common", 433 "smi_gals", "smi_iommu"; 434 mediatek,infracfg = <&infracfg_ao>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 #power-domain-cells = <1>; 438 439 power-domain@MT8186_POWER_DOMAIN_VDEC { 440 reg = <MT8186_POWER_DOMAIN_VDEC>; 441 clocks = <&topckgen CLK_TOP_VDEC>, 442 <&vdecsys CLK_VDEC_LARB1_CKEN>; 443 clock-names = "vdec0", "larb"; 444 mediatek,infracfg = <&infracfg_ao>; 445 #power-domain-cells = <0>; 446 }; 447 448 power-domain@MT8186_POWER_DOMAIN_CAM { 449 reg = <MT8186_POWER_DOMAIN_CAM>; 450 clocks = <&topckgen CLK_TOP_CAM>, 451 <&topckgen CLK_TOP_SENINF>, 452 <&topckgen CLK_TOP_SENINF1>, 453 <&topckgen CLK_TOP_SENINF2>, 454 <&topckgen CLK_TOP_SENINF3>, 455 <&topckgen CLK_TOP_CAMTM>, 456 <&camsys CLK_CAM2MM_GALS>; 457 clock-names = "cam-top", "cam0", "cam1", "cam2", 458 "cam3", "cam-tm", "gals"; 459 mediatek,infracfg = <&infracfg_ao>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 #power-domain-cells = <1>; 463 464 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 465 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 466 #power-domain-cells = <0>; 467 }; 468 469 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 470 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 471 #power-domain-cells = <0>; 472 }; 473 }; 474 475 power-domain@MT8186_POWER_DOMAIN_IMG { 476 reg = <MT8186_POWER_DOMAIN_IMG>; 477 clocks = <&topckgen CLK_TOP_IMG1>, 478 <&imgsys1 CLK_IMG1_GALS_IMG1>; 479 clock-names = "img-top", "gals"; 480 mediatek,infracfg = <&infracfg_ao>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 #power-domain-cells = <1>; 484 485 power-domain@MT8186_POWER_DOMAIN_IMG2 { 486 reg = <MT8186_POWER_DOMAIN_IMG2>; 487 #power-domain-cells = <0>; 488 }; 489 }; 490 491 power-domain@MT8186_POWER_DOMAIN_IPE { 492 reg = <MT8186_POWER_DOMAIN_IPE>; 493 clocks = <&topckgen CLK_TOP_IPE>, 494 <&ipesys CLK_IPE_LARB19>, 495 <&ipesys CLK_IPE_LARB20>, 496 <&ipesys CLK_IPE_SMI_SUBCOM>, 497 <&ipesys CLK_IPE_GALS_IPE>; 498 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 499 "ipe-smi", "ipe-gals"; 500 mediatek,infracfg = <&infracfg_ao>; 501 #power-domain-cells = <0>; 502 }; 503 504 power-domain@MT8186_POWER_DOMAIN_VENC { 505 reg = <MT8186_POWER_DOMAIN_VENC>; 506 clocks = <&topckgen CLK_TOP_VENC>, 507 <&vencsys CLK_VENC_CKE1_VENC>; 508 clock-names = "venc0", "larb"; 509 mediatek,infracfg = <&infracfg_ao>; 510 #power-domain-cells = <0>; 511 }; 512 513 power-domain@MT8186_POWER_DOMAIN_WPE { 514 reg = <MT8186_POWER_DOMAIN_WPE>; 515 clocks = <&topckgen CLK_TOP_WPE>, 516 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 517 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 518 clock-names = "wpe0", "larb-ck", "larb-pclk"; 519 mediatek,infracfg = <&infracfg_ao>; 520 #power-domain-cells = <0>; 521 }; 522 }; 523 }; 524 }; 525 526 watchdog: watchdog@10007000 { 527 compatible = "mediatek,mt8186-wdt", 528 "mediatek,mt6589-wdt"; 529 mediatek,disable-extrst; 530 reg = <0 0x10007000 0 0x1000>; 531 #reset-cells = <1>; 532 }; 533 534 apmixedsys: syscon@1000c000 { 535 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 536 reg = <0 0x1000c000 0 0x1000>; 537 #clock-cells = <1>; 538 }; 539 540 pwrap: pwrap@1000d000 { 541 compatible = "mediatek,mt8186-pwrap", "syscon"; 542 reg = <0 0x1000d000 0 0x1000>; 543 reg-names = "pwrap"; 544 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 545 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 546 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 547 clock-names = "spi", "wrap"; 548 }; 549 550 systimer: timer@10017000 { 551 compatible = "mediatek,mt8186-timer", 552 "mediatek,mt6765-timer"; 553 reg = <0 0x10017000 0 0x1000>; 554 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 555 clocks = <&clk13m>; 556 }; 557 558 scp: scp@10500000 { 559 compatible = "mediatek,mt8186-scp"; 560 reg = <0 0x10500000 0 0x40000>, 561 <0 0x105c0000 0 0x19080>; 562 reg-names = "sram", "cfg"; 563 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 564 }; 565 566 nor_flash: spi@11000000 { 567 compatible = "mediatek,mt8186-nor"; 568 reg = <0 0x11000000 0 0x1000>; 569 clocks = <&topckgen CLK_TOP_SPINOR>, 570 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 571 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 572 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 573 clock-names = "spi", "sf", "axi", "axi_s"; 574 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 575 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 576 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 577 status = "disabled"; 578 }; 579 580 auxadc: adc@11001000 { 581 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 582 reg = <0 0x11001000 0 0x1000>; 583 #io-channel-cells = <1>; 584 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 585 clock-names = "main"; 586 }; 587 588 uart0: serial@11002000 { 589 compatible = "mediatek,mt8186-uart", 590 "mediatek,mt6577-uart"; 591 reg = <0 0x11002000 0 0x1000>; 592 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 593 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 594 clock-names = "baud", "bus"; 595 status = "disabled"; 596 }; 597 598 uart1: serial@11003000 { 599 compatible = "mediatek,mt8186-uart", 600 "mediatek,mt6577-uart"; 601 reg = <0 0x11003000 0 0x1000>; 602 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 603 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 604 clock-names = "baud", "bus"; 605 status = "disabled"; 606 }; 607 608 i2c0: i2c@11007000 { 609 compatible = "mediatek,mt8186-i2c"; 610 reg = <0 0x11007000 0 0x1000>, 611 <0 0x10200100 0 0x100>; 612 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 613 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 614 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 615 clock-names = "main", "dma"; 616 clock-div = <1>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 status = "disabled"; 620 }; 621 622 i2c1: i2c@11008000 { 623 compatible = "mediatek,mt8186-i2c"; 624 reg = <0 0x11008000 0 0x1000>, 625 <0 0x10200200 0 0x100>; 626 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 627 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 628 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 629 clock-names = "main", "dma"; 630 clock-div = <1>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 i2c2: i2c@11009000 { 637 compatible = "mediatek,mt8186-i2c"; 638 reg = <0 0x11009000 0 0x1000>, 639 <0 0x10200300 0 0x180>; 640 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 641 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 642 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 643 clock-names = "main", "dma"; 644 clock-div = <1>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 i2c3: i2c@1100f000 { 651 compatible = "mediatek,mt8186-i2c"; 652 reg = <0 0x1100f000 0 0x1000>, 653 <0 0x10200480 0 0x100>; 654 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 655 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 656 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 657 clock-names = "main", "dma"; 658 clock-div = <1>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 i2c4: i2c@11011000 { 665 compatible = "mediatek,mt8186-i2c"; 666 reg = <0 0x11011000 0 0x1000>, 667 <0 0x10200580 0 0x180>; 668 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 669 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 670 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 671 clock-names = "main", "dma"; 672 clock-div = <1>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 status = "disabled"; 676 }; 677 678 i2c5: i2c@11016000 { 679 compatible = "mediatek,mt8186-i2c"; 680 reg = <0 0x11016000 0 0x1000>, 681 <0 0x10200700 0 0x100>; 682 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 683 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 684 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 685 clock-names = "main", "dma"; 686 clock-div = <1>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 i2c6: i2c@1100d000 { 693 compatible = "mediatek,mt8186-i2c"; 694 reg = <0 0x1100d000 0 0x1000>, 695 <0 0x10200800 0 0x100>; 696 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 697 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 698 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 699 clock-names = "main", "dma"; 700 clock-div = <1>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 status = "disabled"; 704 }; 705 706 i2c7: i2c@11004000 { 707 compatible = "mediatek,mt8186-i2c"; 708 reg = <0 0x11004000 0 0x1000>, 709 <0 0x10200900 0 0x180>; 710 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 711 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 712 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 713 clock-names = "main", "dma"; 714 clock-div = <1>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 status = "disabled"; 718 }; 719 720 i2c8: i2c@11005000 { 721 compatible = "mediatek,mt8186-i2c"; 722 reg = <0 0x11005000 0 0x1000>, 723 <0 0x10200A80 0 0x180>; 724 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 725 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 726 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 727 clock-names = "main", "dma"; 728 clock-div = <1>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 spi0: spi@1100a000 { 735 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 reg = <0 0x1100a000 0 0x1000>; 739 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 740 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 741 <&topckgen CLK_TOP_SPI>, 742 <&infracfg_ao CLK_INFRA_AO_SPI0>; 743 clock-names = "parent-clk", "sel-clk", "spi-clk"; 744 status = "disabled"; 745 }; 746 747 pwm0: pwm@1100e000 { 748 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 749 reg = <0 0x1100e000 0 0x1000>; 750 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 751 #pwm-cells = <2>; 752 clocks = <&topckgen CLK_TOP_DISP_PWM>, 753 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 754 clock-names = "main", "mm"; 755 status = "disabled"; 756 }; 757 758 spi1: spi@11010000 { 759 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 reg = <0 0x11010000 0 0x1000>; 763 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 764 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 765 <&topckgen CLK_TOP_SPI>, 766 <&infracfg_ao CLK_INFRA_AO_SPI1>; 767 clock-names = "parent-clk", "sel-clk", "spi-clk"; 768 status = "disabled"; 769 }; 770 771 spi2: spi@11012000 { 772 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 reg = <0 0x11012000 0 0x1000>; 776 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 777 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 778 <&topckgen CLK_TOP_SPI>, 779 <&infracfg_ao CLK_INFRA_AO_SPI2>; 780 clock-names = "parent-clk", "sel-clk", "spi-clk"; 781 status = "disabled"; 782 }; 783 784 spi3: spi@11013000 { 785 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 reg = <0 0x11013000 0 0x1000>; 789 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 790 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 791 <&topckgen CLK_TOP_SPI>, 792 <&infracfg_ao CLK_INFRA_AO_SPI3>; 793 clock-names = "parent-clk", "sel-clk", "spi-clk"; 794 status = "disabled"; 795 }; 796 797 spi4: spi@11014000 { 798 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 reg = <0 0x11014000 0 0x1000>; 802 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 803 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 804 <&topckgen CLK_TOP_SPI>, 805 <&infracfg_ao CLK_INFRA_AO_SPI4>; 806 clock-names = "parent-clk", "sel-clk", "spi-clk"; 807 status = "disabled"; 808 }; 809 810 spi5: spi@11015000 { 811 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 reg = <0 0x11015000 0 0x1000>; 815 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 816 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 817 <&topckgen CLK_TOP_SPI>, 818 <&infracfg_ao CLK_INFRA_AO_SPI5>; 819 clock-names = "parent-clk", "sel-clk", "spi-clk"; 820 status = "disabled"; 821 }; 822 823 imp_iic_wrap: clock-controller@11017000 { 824 compatible = "mediatek,mt8186-imp_iic_wrap"; 825 reg = <0 0x11017000 0 0x1000>; 826 #clock-cells = <1>; 827 }; 828 829 uart2: serial@11018000 { 830 compatible = "mediatek,mt8186-uart", 831 "mediatek,mt6577-uart"; 832 reg = <0 0x11018000 0 0x1000>; 833 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 834 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 835 clock-names = "baud", "bus"; 836 status = "disabled"; 837 }; 838 839 i2c9: i2c@11019000 { 840 compatible = "mediatek,mt8186-i2c"; 841 reg = <0 0x11019000 0 0x1000>, 842 <0 0x10200c00 0 0x180>; 843 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 844 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 845 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 846 clock-names = "main", "dma"; 847 clock-div = <1>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 status = "disabled"; 851 }; 852 853 mmc0: mmc@11230000 { 854 compatible = "mediatek,mt8186-mmc", 855 "mediatek,mt8183-mmc"; 856 reg = <0 0x11230000 0 0x1000>, 857 <0 0x11cd0000 0 0x1000>; 858 clocks = <&topckgen CLK_TOP_MSDC50_0>, 859 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 860 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 861 clock-names = "source", "hclk", "source_cg"; 862 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 863 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 864 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 865 status = "disabled"; 866 }; 867 868 mmc1: mmc@11240000 { 869 compatible = "mediatek,mt8186-mmc", 870 "mediatek,mt8183-mmc"; 871 reg = <0 0x11240000 0 0x1000>, 872 <0 0x11c90000 0 0x1000>; 873 clocks = <&topckgen CLK_TOP_MSDC30_1>, 874 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 875 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 876 clock-names = "source", "hclk", "source_cg"; 877 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 878 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 879 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 880 status = "disabled"; 881 }; 882 883 u3phy0: t-phy@11c80000 { 884 compatible = "mediatek,mt8186-tphy", 885 "mediatek,generic-tphy-v2"; 886 #address-cells = <1>; 887 #size-cells = <1>; 888 ranges = <0x0 0x0 0x11c80000 0x1000>; 889 status = "disabled"; 890 891 u2port1: usb-phy@0 { 892 reg = <0x0 0x700>; 893 clocks = <&clk26m>; 894 clock-names = "ref"; 895 #phy-cells = <1>; 896 }; 897 898 u3port1: usb-phy@700 { 899 reg = <0x700 0x900>; 900 clocks = <&clk26m>; 901 clock-names = "ref"; 902 #phy-cells = <1>; 903 }; 904 }; 905 906 u3phy1: t-phy@11ca0000 { 907 compatible = "mediatek,mt8186-tphy", 908 "mediatek,generic-tphy-v2"; 909 #address-cells = <1>; 910 #size-cells = <1>; 911 ranges = <0x0 0x0 0x11ca0000 0x1000>; 912 status = "disabled"; 913 914 u2port0: usb-phy@0 { 915 reg = <0x0 0x700>; 916 clocks = <&clk26m>; 917 clock-names = "ref"; 918 #phy-cells = <1>; 919 mediatek,discth = <0x8>; 920 }; 921 }; 922 923 efuse: efuse@11cb0000 { 924 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 925 reg = <0 0x11cb0000 0 0x1000>; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 }; 929 930 mipi_tx0: dsi-phy@11cc0000 { 931 compatible = "mediatek,mt8183-mipi-tx"; 932 reg = <0 0x11cc0000 0 0x1000>; 933 clocks = <&clk26m>; 934 #clock-cells = <0>; 935 #phy-cells = <0>; 936 clock-output-names = "mipi_tx0_pll"; 937 status = "disabled"; 938 }; 939 940 mfgsys: clock-controller@13000000 { 941 compatible = "mediatek,mt8186-mfgsys"; 942 reg = <0 0x13000000 0 0x1000>; 943 #clock-cells = <1>; 944 }; 945 946 mmsys: syscon@14000000 { 947 compatible = "mediatek,mt8186-mmsys", "syscon"; 948 reg = <0 0x14000000 0 0x1000>; 949 #clock-cells = <1>; 950 #reset-cells = <1>; 951 }; 952 953 smi_common: smi@14002000 { 954 compatible = "mediatek,mt8186-smi-common"; 955 reg = <0 0x14002000 0 0x1000>; 956 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 957 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 958 clock-names = "apb", "smi", "gals0", "gals1"; 959 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 960 }; 961 962 larb0: smi@14003000 { 963 compatible = "mediatek,mt8186-smi-larb"; 964 reg = <0 0x14003000 0 0x1000>; 965 clocks = <&mmsys CLK_MM_SMI_COMMON>, 966 <&mmsys CLK_MM_SMI_COMMON>; 967 clock-names = "apb", "smi"; 968 mediatek,larb-id = <0>; 969 mediatek,smi = <&smi_common>; 970 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 971 }; 972 973 larb1: smi@14004000 { 974 compatible = "mediatek,mt8186-smi-larb"; 975 reg = <0 0x14004000 0 0x1000>; 976 clocks = <&mmsys CLK_MM_SMI_COMMON>, 977 <&mmsys CLK_MM_SMI_COMMON>; 978 clock-names = "apb", "smi"; 979 mediatek,larb-id = <1>; 980 mediatek,smi = <&smi_common>; 981 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 982 }; 983 984 dsi0: dsi@14013000 { 985 compatible = "mediatek,mt8186-dsi"; 986 reg = <0 0x14013000 0 0x1000>; 987 clocks = <&mmsys CLK_MM_DSI0>, 988 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 989 <&mipi_tx0>; 990 clock-names = "engine", "digital", "hs"; 991 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 992 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 993 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 994 phys = <&mipi_tx0>; 995 phy-names = "dphy"; 996 status = "disabled"; 997 998 port { 999 dsi_out: endpoint { }; 1000 }; 1001 }; 1002 1003 iommu_mm: iommu@14016000 { 1004 compatible = "mediatek,mt8186-iommu-mm"; 1005 reg = <0 0x14016000 0 0x1000>; 1006 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1007 clock-names = "bclk"; 1008 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1009 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1010 &larb7 &larb8 &larb9 &larb11 1011 &larb13 &larb14 &larb16 &larb17 1012 &larb19 &larb20>; 1013 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1014 #iommu-cells = <1>; 1015 }; 1016 1017 wpesys: clock-controller@14020000 { 1018 compatible = "mediatek,mt8186-wpesys"; 1019 reg = <0 0x14020000 0 0x1000>; 1020 #clock-cells = <1>; 1021 }; 1022 1023 larb8: smi@14023000 { 1024 compatible = "mediatek,mt8186-smi-larb"; 1025 reg = <0 0x14023000 0 0x1000>; 1026 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1027 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1028 clock-names = "apb", "smi"; 1029 mediatek,larb-id = <8>; 1030 mediatek,smi = <&smi_common>; 1031 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1032 }; 1033 1034 imgsys1: clock-controller@15020000 { 1035 compatible = "mediatek,mt8186-imgsys1"; 1036 reg = <0 0x15020000 0 0x1000>; 1037 #clock-cells = <1>; 1038 }; 1039 1040 larb9: smi@1502e000 { 1041 compatible = "mediatek,mt8186-smi-larb"; 1042 reg = <0 0x1502e000 0 0x1000>; 1043 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1044 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1045 clock-names = "apb", "smi"; 1046 mediatek,larb-id = <9>; 1047 mediatek,smi = <&smi_common>; 1048 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1049 }; 1050 1051 imgsys2: clock-controller@15820000 { 1052 compatible = "mediatek,mt8186-imgsys2"; 1053 reg = <0 0x15820000 0 0x1000>; 1054 #clock-cells = <1>; 1055 }; 1056 1057 larb11: smi@1582e000 { 1058 compatible = "mediatek,mt8186-smi-larb"; 1059 reg = <0 0x1582e000 0 0x1000>; 1060 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1061 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1062 clock-names = "apb", "smi"; 1063 mediatek,larb-id = <11>; 1064 mediatek,smi = <&smi_common>; 1065 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1066 }; 1067 1068 larb4: smi@1602e000 { 1069 compatible = "mediatek,mt8186-smi-larb"; 1070 reg = <0 0x1602e000 0 0x1000>; 1071 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1072 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1073 clock-names = "apb", "smi"; 1074 mediatek,larb-id = <4>; 1075 mediatek,smi = <&smi_common>; 1076 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1077 }; 1078 1079 vdecsys: clock-controller@1602f000 { 1080 compatible = "mediatek,mt8186-vdecsys"; 1081 reg = <0 0x1602f000 0 0x1000>; 1082 #clock-cells = <1>; 1083 }; 1084 1085 vencsys: clock-controller@17000000 { 1086 compatible = "mediatek,mt8186-vencsys"; 1087 reg = <0 0x17000000 0 0x1000>; 1088 #clock-cells = <1>; 1089 }; 1090 1091 larb7: smi@17010000 { 1092 compatible = "mediatek,mt8186-smi-larb"; 1093 reg = <0 0x17010000 0 0x1000>; 1094 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1095 <&vencsys CLK_VENC_CKE1_VENC>; 1096 clock-names = "apb", "smi"; 1097 mediatek,larb-id = <7>; 1098 mediatek,smi = <&smi_common>; 1099 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1100 }; 1101 1102 camsys: clock-controller@1a000000 { 1103 compatible = "mediatek,mt8186-camsys"; 1104 reg = <0 0x1a000000 0 0x1000>; 1105 #clock-cells = <1>; 1106 }; 1107 1108 larb13: smi@1a001000 { 1109 compatible = "mediatek,mt8186-smi-larb"; 1110 reg = <0 0x1a001000 0 0x1000>; 1111 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1112 clock-names = "apb", "smi"; 1113 mediatek,larb-id = <13>; 1114 mediatek,smi = <&smi_common>; 1115 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1116 }; 1117 1118 larb14: smi@1a002000 { 1119 compatible = "mediatek,mt8186-smi-larb"; 1120 reg = <0 0x1a002000 0 0x1000>; 1121 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1122 clock-names = "apb", "smi"; 1123 mediatek,larb-id = <14>; 1124 mediatek,smi = <&smi_common>; 1125 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1126 }; 1127 1128 larb16: smi@1a00f000 { 1129 compatible = "mediatek,mt8186-smi-larb"; 1130 reg = <0 0x1a00f000 0 0x1000>; 1131 clocks = <&camsys CLK_CAM_LARB14>, 1132 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1133 clock-names = "apb", "smi"; 1134 mediatek,larb-id = <16>; 1135 mediatek,smi = <&smi_common>; 1136 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1137 }; 1138 1139 larb17: smi@1a010000 { 1140 compatible = "mediatek,mt8186-smi-larb"; 1141 reg = <0 0x1a010000 0 0x1000>; 1142 clocks = <&camsys CLK_CAM_LARB13>, 1143 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1144 clock-names = "apb", "smi"; 1145 mediatek,larb-id = <17>; 1146 mediatek,smi = <&smi_common>; 1147 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1148 }; 1149 1150 camsys_rawa: clock-controller@1a04f000 { 1151 compatible = "mediatek,mt8186-camsys_rawa"; 1152 reg = <0 0x1a04f000 0 0x1000>; 1153 #clock-cells = <1>; 1154 }; 1155 1156 camsys_rawb: clock-controller@1a06f000 { 1157 compatible = "mediatek,mt8186-camsys_rawb"; 1158 reg = <0 0x1a06f000 0 0x1000>; 1159 #clock-cells = <1>; 1160 }; 1161 1162 mdpsys: clock-controller@1b000000 { 1163 compatible = "mediatek,mt8186-mdpsys"; 1164 reg = <0 0x1b000000 0 0x1000>; 1165 #clock-cells = <1>; 1166 }; 1167 1168 larb2: smi@1b002000 { 1169 compatible = "mediatek,mt8186-smi-larb"; 1170 reg = <0 0x1b002000 0 0x1000>; 1171 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1172 clock-names = "apb", "smi"; 1173 mediatek,larb-id = <2>; 1174 mediatek,smi = <&smi_common>; 1175 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1176 }; 1177 1178 ipesys: clock-controller@1c000000 { 1179 compatible = "mediatek,mt8186-ipesys"; 1180 reg = <0 0x1c000000 0 0x1000>; 1181 #clock-cells = <1>; 1182 }; 1183 1184 larb20: smi@1c00f000 { 1185 compatible = "mediatek,mt8186-smi-larb"; 1186 reg = <0 0x1c00f000 0 0x1000>; 1187 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1188 clock-names = "apb", "smi"; 1189 mediatek,larb-id = <20>; 1190 mediatek,smi = <&smi_common>; 1191 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1192 }; 1193 1194 larb19: smi@1c10f000 { 1195 compatible = "mediatek,mt8186-smi-larb"; 1196 reg = <0 0x1c10f000 0 0x1000>; 1197 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1198 clock-names = "apb", "smi"; 1199 mediatek,larb-id = <19>; 1200 mediatek,smi = <&smi_common>; 1201 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1202 }; 1203 }; 1204}; 1205