1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/memory/mt8186-memory-port.h> 11#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 12#include <dt-bindings/power/mt8186-power.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/mt8186-resets.h> 15 16/ { 17 compatible = "mediatek,mt8186"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 44 core4 { 45 cpu = <&cpu4>; 46 }; 47 48 core5 { 49 cpu = <&cpu5>; 50 }; 51 }; 52 53 cluster1 { 54 core0 { 55 cpu = <&cpu6>; 56 }; 57 58 core1 { 59 cpu = <&cpu7>; 60 }; 61 }; 62 }; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x000>; 68 enable-method = "psci"; 69 clock-frequency = <2000000000>; 70 capacity-dmips-mhz = <382>; 71 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 72 i-cache-size = <32768>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <128>; 75 d-cache-size = <32768>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&l2_0>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a55"; 85 reg = <0x100>; 86 enable-method = "psci"; 87 clock-frequency = <2000000000>; 88 capacity-dmips-mhz = <382>; 89 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 90 i-cache-size = <32768>; 91 i-cache-line-size = <64>; 92 i-cache-sets = <128>; 93 d-cache-size = <32768>; 94 d-cache-line-size = <64>; 95 d-cache-sets = <128>; 96 next-level-cache = <&l2_0>; 97 #cooling-cells = <2>; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a55"; 103 reg = <0x200>; 104 enable-method = "psci"; 105 clock-frequency = <2000000000>; 106 capacity-dmips-mhz = <382>; 107 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 108 i-cache-size = <32768>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <128>; 111 d-cache-size = <32768>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&l2_0>; 115 #cooling-cells = <2>; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x300>; 122 enable-method = "psci"; 123 clock-frequency = <2000000000>; 124 capacity-dmips-mhz = <382>; 125 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 126 i-cache-size = <32768>; 127 i-cache-line-size = <64>; 128 i-cache-sets = <128>; 129 d-cache-size = <32768>; 130 d-cache-line-size = <64>; 131 d-cache-sets = <128>; 132 next-level-cache = <&l2_0>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu4: cpu@400 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a55"; 139 reg = <0x400>; 140 enable-method = "psci"; 141 clock-frequency = <2000000000>; 142 capacity-dmips-mhz = <382>; 143 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 144 i-cache-size = <32768>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <128>; 147 d-cache-size = <32768>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <128>; 150 next-level-cache = <&l2_0>; 151 #cooling-cells = <2>; 152 }; 153 154 cpu5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a55"; 157 reg = <0x500>; 158 enable-method = "psci"; 159 clock-frequency = <2000000000>; 160 capacity-dmips-mhz = <382>; 161 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 162 i-cache-size = <32768>; 163 i-cache-line-size = <64>; 164 i-cache-sets = <128>; 165 d-cache-size = <32768>; 166 d-cache-line-size = <64>; 167 d-cache-sets = <128>; 168 next-level-cache = <&l2_0>; 169 #cooling-cells = <2>; 170 }; 171 172 cpu6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a76"; 175 reg = <0x600>; 176 enable-method = "psci"; 177 clock-frequency = <2050000000>; 178 capacity-dmips-mhz = <1024>; 179 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 180 i-cache-size = <65536>; 181 i-cache-line-size = <64>; 182 i-cache-sets = <256>; 183 d-cache-size = <65536>; 184 d-cache-line-size = <64>; 185 d-cache-sets = <256>; 186 next-level-cache = <&l2_1>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu7: cpu@700 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x700>; 194 enable-method = "psci"; 195 clock-frequency = <2050000000>; 196 capacity-dmips-mhz = <1024>; 197 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_1>; 205 #cooling-cells = <2>; 206 }; 207 208 idle-states { 209 entry-method = "psci"; 210 211 cpu_off_l: cpu-off-l { 212 compatible = "arm,idle-state"; 213 arm,psci-suspend-param = <0x00010001>; 214 local-timer-stop; 215 entry-latency-us = <50>; 216 exit-latency-us = <100>; 217 min-residency-us = <1600>; 218 }; 219 220 cpu_off_b: cpu-off-b { 221 compatible = "arm,idle-state"; 222 arm,psci-suspend-param = <0x00010001>; 223 local-timer-stop; 224 entry-latency-us = <50>; 225 exit-latency-us = <100>; 226 min-residency-us = <1400>; 227 }; 228 229 cluster_off_l: cluster-off-l { 230 compatible = "arm,idle-state"; 231 arm,psci-suspend-param = <0x01010001>; 232 local-timer-stop; 233 entry-latency-us = <100>; 234 exit-latency-us = <250>; 235 min-residency-us = <2100>; 236 }; 237 238 cluster_off_b: cluster-off-b { 239 compatible = "arm,idle-state"; 240 arm,psci-suspend-param = <0x01010001>; 241 local-timer-stop; 242 entry-latency-us = <100>; 243 exit-latency-us = <250>; 244 min-residency-us = <1900>; 245 }; 246 }; 247 248 l2_0: l2-cache0 { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-size = <131072>; 252 cache-line-size = <64>; 253 cache-sets = <512>; 254 next-level-cache = <&l3_0>; 255 }; 256 257 l2_1: l2-cache1 { 258 compatible = "cache"; 259 cache-level = <2>; 260 cache-size = <262144>; 261 cache-line-size = <64>; 262 cache-sets = <512>; 263 next-level-cache = <&l3_0>; 264 }; 265 266 l3_0: l3-cache { 267 compatible = "cache"; 268 cache-level = <3>; 269 cache-size = <1048576>; 270 cache-line-size = <64>; 271 cache-sets = <1024>; 272 cache-unified; 273 }; 274 }; 275 276 clk13m: fixed-factor-clock-13m { 277 compatible = "fixed-factor-clock"; 278 #clock-cells = <0>; 279 clocks = <&clk26m>; 280 clock-div = <2>; 281 clock-mult = <1>; 282 clock-output-names = "clk13m"; 283 }; 284 285 clk26m: oscillator-26m { 286 compatible = "fixed-clock"; 287 #clock-cells = <0>; 288 clock-frequency = <26000000>; 289 clock-output-names = "clk26m"; 290 }; 291 292 clk32k: oscillator-32k { 293 compatible = "fixed-clock"; 294 #clock-cells = <0>; 295 clock-frequency = <32768>; 296 clock-output-names = "clk32k"; 297 }; 298 299 pmu-a55 { 300 compatible = "arm,cortex-a55-pmu"; 301 interrupt-parent = <&gic>; 302 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 303 }; 304 305 pmu-a76 { 306 compatible = "arm,cortex-a76-pmu"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 309 }; 310 311 psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 }; 315 316 timer { 317 compatible = "arm,armv8-timer"; 318 interrupt-parent = <&gic>; 319 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 320 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 321 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 322 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 323 }; 324 325 soc { 326 #address-cells = <2>; 327 #size-cells = <2>; 328 compatible = "simple-bus"; 329 ranges; 330 331 gic: interrupt-controller@c000000 { 332 compatible = "arm,gic-v3"; 333 #interrupt-cells = <4>; 334 #redistributor-regions = <1>; 335 interrupt-parent = <&gic>; 336 interrupt-controller; 337 reg = <0 0x0c000000 0 0x40000>, 338 <0 0x0c040000 0 0x200000>; 339 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 340 341 ppi-partitions { 342 ppi_cluster0: interrupt-partition-0 { 343 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 344 }; 345 346 ppi_cluster1: interrupt-partition-1 { 347 affinity = <&cpu6 &cpu7>; 348 }; 349 }; 350 }; 351 352 mcusys: syscon@c53a000 { 353 compatible = "mediatek,mt8186-mcusys", "syscon"; 354 reg = <0 0xc53a000 0 0x1000>; 355 #clock-cells = <1>; 356 }; 357 358 topckgen: syscon@10000000 { 359 compatible = "mediatek,mt8186-topckgen", "syscon"; 360 reg = <0 0x10000000 0 0x1000>; 361 #clock-cells = <1>; 362 }; 363 364 infracfg_ao: syscon@10001000 { 365 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 366 reg = <0 0x10001000 0 0x1000>; 367 #clock-cells = <1>; 368 #reset-cells = <1>; 369 }; 370 371 pericfg: syscon@10003000 { 372 compatible = "mediatek,mt8186-pericfg", "syscon"; 373 reg = <0 0x10003000 0 0x1000>; 374 }; 375 376 pio: pinctrl@10005000 { 377 compatible = "mediatek,mt8186-pinctrl"; 378 reg = <0 0x10005000 0 0x1000>, 379 <0 0x10002000 0 0x0200>, 380 <0 0x10002200 0 0x0200>, 381 <0 0x10002400 0 0x0200>, 382 <0 0x10002600 0 0x0200>, 383 <0 0x10002a00 0 0x0200>, 384 <0 0x10002c00 0 0x0200>, 385 <0 0x1000b000 0 0x1000>; 386 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 387 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 388 gpio-controller; 389 #gpio-cells = <2>; 390 gpio-ranges = <&pio 0 0 185>; 391 interrupt-controller; 392 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 393 #interrupt-cells = <2>; 394 }; 395 396 scpsys: syscon@10006000 { 397 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 398 reg = <0 0x10006000 0 0x1000>; 399 400 /* System Power Manager */ 401 spm: power-controller { 402 compatible = "mediatek,mt8186-power-controller"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 #power-domain-cells = <1>; 406 407 /* power domain of the SoC */ 408 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 409 reg = <MT8186_POWER_DOMAIN_MFG0>; 410 clocks = <&topckgen CLK_TOP_MFG>; 411 clock-names = "mfg00"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 #power-domain-cells = <1>; 415 416 power-domain@MT8186_POWER_DOMAIN_MFG1 { 417 reg = <MT8186_POWER_DOMAIN_MFG1>; 418 mediatek,infracfg = <&infracfg_ao>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 #power-domain-cells = <1>; 422 423 power-domain@MT8186_POWER_DOMAIN_MFG2 { 424 reg = <MT8186_POWER_DOMAIN_MFG2>; 425 #power-domain-cells = <0>; 426 }; 427 428 power-domain@MT8186_POWER_DOMAIN_MFG3 { 429 reg = <MT8186_POWER_DOMAIN_MFG3>; 430 #power-domain-cells = <0>; 431 }; 432 }; 433 }; 434 435 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 436 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 437 clocks = <&topckgen CLK_TOP_SENINF>, 438 <&topckgen CLK_TOP_SENINF1>; 439 clock-names = "csirx_top0", "csirx_top1"; 440 #power-domain-cells = <0>; 441 }; 442 443 power-domain@MT8186_POWER_DOMAIN_SSUSB { 444 reg = <MT8186_POWER_DOMAIN_SSUSB>; 445 #power-domain-cells = <0>; 446 }; 447 448 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 449 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 450 #power-domain-cells = <0>; 451 }; 452 453 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 454 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 455 clocks = <&topckgen CLK_TOP_AUDIODSP>, 456 <&topckgen CLK_TOP_ADSP_BUS>; 457 clock-names = "audioadsp", "adsp_bus"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 #power-domain-cells = <1>; 461 462 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 463 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 #power-domain-cells = <1>; 467 468 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 469 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 470 mediatek,infracfg = <&infracfg_ao>; 471 #power-domain-cells = <0>; 472 }; 473 }; 474 }; 475 476 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 477 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 478 mediatek,infracfg = <&infracfg_ao>; 479 #power-domain-cells = <0>; 480 }; 481 482 power-domain@MT8186_POWER_DOMAIN_DIS { 483 reg = <MT8186_POWER_DOMAIN_DIS>; 484 clocks = <&topckgen CLK_TOP_DISP>, 485 <&topckgen CLK_TOP_MDP>, 486 <&mmsys CLK_MM_SMI_INFRA>, 487 <&mmsys CLK_MM_SMI_COMMON>, 488 <&mmsys CLK_MM_SMI_GALS>, 489 <&mmsys CLK_MM_SMI_IOMMU>; 490 clock-names = "disp", "mdp", "smi_infra", "smi_common", 491 "smi_gals", "smi_iommu"; 492 mediatek,infracfg = <&infracfg_ao>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 #power-domain-cells = <1>; 496 497 power-domain@MT8186_POWER_DOMAIN_VDEC { 498 reg = <MT8186_POWER_DOMAIN_VDEC>; 499 clocks = <&topckgen CLK_TOP_VDEC>, 500 <&vdecsys CLK_VDEC_LARB1_CKEN>; 501 clock-names = "vdec0", "larb"; 502 mediatek,infracfg = <&infracfg_ao>; 503 #power-domain-cells = <0>; 504 }; 505 506 power-domain@MT8186_POWER_DOMAIN_CAM { 507 reg = <MT8186_POWER_DOMAIN_CAM>; 508 clocks = <&topckgen CLK_TOP_CAM>, 509 <&topckgen CLK_TOP_SENINF>, 510 <&topckgen CLK_TOP_SENINF1>, 511 <&topckgen CLK_TOP_SENINF2>, 512 <&topckgen CLK_TOP_SENINF3>, 513 <&topckgen CLK_TOP_CAMTM>, 514 <&camsys CLK_CAM2MM_GALS>; 515 clock-names = "cam-top", "cam0", "cam1", "cam2", 516 "cam3", "cam-tm", "gals"; 517 mediatek,infracfg = <&infracfg_ao>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 #power-domain-cells = <1>; 521 522 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 523 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 524 #power-domain-cells = <0>; 525 }; 526 527 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 528 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 529 #power-domain-cells = <0>; 530 }; 531 }; 532 533 power-domain@MT8186_POWER_DOMAIN_IMG { 534 reg = <MT8186_POWER_DOMAIN_IMG>; 535 clocks = <&topckgen CLK_TOP_IMG1>, 536 <&imgsys1 CLK_IMG1_GALS_IMG1>; 537 clock-names = "img-top", "gals"; 538 mediatek,infracfg = <&infracfg_ao>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 #power-domain-cells = <1>; 542 543 power-domain@MT8186_POWER_DOMAIN_IMG2 { 544 reg = <MT8186_POWER_DOMAIN_IMG2>; 545 #power-domain-cells = <0>; 546 }; 547 }; 548 549 power-domain@MT8186_POWER_DOMAIN_IPE { 550 reg = <MT8186_POWER_DOMAIN_IPE>; 551 clocks = <&topckgen CLK_TOP_IPE>, 552 <&ipesys CLK_IPE_LARB19>, 553 <&ipesys CLK_IPE_LARB20>, 554 <&ipesys CLK_IPE_SMI_SUBCOM>, 555 <&ipesys CLK_IPE_GALS_IPE>; 556 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 557 "ipe-smi", "ipe-gals"; 558 mediatek,infracfg = <&infracfg_ao>; 559 #power-domain-cells = <0>; 560 }; 561 562 power-domain@MT8186_POWER_DOMAIN_VENC { 563 reg = <MT8186_POWER_DOMAIN_VENC>; 564 clocks = <&topckgen CLK_TOP_VENC>, 565 <&vencsys CLK_VENC_CKE1_VENC>; 566 clock-names = "venc0", "larb"; 567 mediatek,infracfg = <&infracfg_ao>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8186_POWER_DOMAIN_WPE { 572 reg = <MT8186_POWER_DOMAIN_WPE>; 573 clocks = <&topckgen CLK_TOP_WPE>, 574 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 575 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 576 clock-names = "wpe0", "larb-ck", "larb-pclk"; 577 mediatek,infracfg = <&infracfg_ao>; 578 #power-domain-cells = <0>; 579 }; 580 }; 581 }; 582 }; 583 584 watchdog: watchdog@10007000 { 585 compatible = "mediatek,mt8186-wdt", 586 "mediatek,mt6589-wdt"; 587 mediatek,disable-extrst; 588 reg = <0 0x10007000 0 0x1000>; 589 #reset-cells = <1>; 590 }; 591 592 apmixedsys: syscon@1000c000 { 593 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 594 reg = <0 0x1000c000 0 0x1000>; 595 #clock-cells = <1>; 596 }; 597 598 pwrap: pwrap@1000d000 { 599 compatible = "mediatek,mt8186-pwrap", "syscon"; 600 reg = <0 0x1000d000 0 0x1000>; 601 reg-names = "pwrap"; 602 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 603 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 604 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 605 clock-names = "spi", "wrap"; 606 }; 607 608 systimer: timer@10017000 { 609 compatible = "mediatek,mt8186-timer", 610 "mediatek,mt6765-timer"; 611 reg = <0 0x10017000 0 0x1000>; 612 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 613 clocks = <&clk13m>; 614 }; 615 616 scp: scp@10500000 { 617 compatible = "mediatek,mt8186-scp"; 618 reg = <0 0x10500000 0 0x40000>, 619 <0 0x105c0000 0 0x19080>; 620 reg-names = "sram", "cfg"; 621 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 622 }; 623 624 nor_flash: spi@11000000 { 625 compatible = "mediatek,mt8186-nor"; 626 reg = <0 0x11000000 0 0x1000>; 627 clocks = <&topckgen CLK_TOP_SPINOR>, 628 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 629 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 630 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 631 clock-names = "spi", "sf", "axi", "axi_s"; 632 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 633 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 634 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 635 status = "disabled"; 636 }; 637 638 auxadc: adc@11001000 { 639 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 640 reg = <0 0x11001000 0 0x1000>; 641 #io-channel-cells = <1>; 642 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 643 clock-names = "main"; 644 }; 645 646 uart0: serial@11002000 { 647 compatible = "mediatek,mt8186-uart", 648 "mediatek,mt6577-uart"; 649 reg = <0 0x11002000 0 0x1000>; 650 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 651 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 652 clock-names = "baud", "bus"; 653 status = "disabled"; 654 }; 655 656 uart1: serial@11003000 { 657 compatible = "mediatek,mt8186-uart", 658 "mediatek,mt6577-uart"; 659 reg = <0 0x11003000 0 0x1000>; 660 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 661 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 662 clock-names = "baud", "bus"; 663 status = "disabled"; 664 }; 665 666 i2c0: i2c@11007000 { 667 compatible = "mediatek,mt8186-i2c"; 668 reg = <0 0x11007000 0 0x1000>, 669 <0 0x10200100 0 0x100>; 670 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 671 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 672 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 673 clock-names = "main", "dma"; 674 clock-div = <1>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 status = "disabled"; 678 }; 679 680 i2c1: i2c@11008000 { 681 compatible = "mediatek,mt8186-i2c"; 682 reg = <0 0x11008000 0 0x1000>, 683 <0 0x10200200 0 0x100>; 684 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 685 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 686 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 687 clock-names = "main", "dma"; 688 clock-div = <1>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 i2c2: i2c@11009000 { 695 compatible = "mediatek,mt8186-i2c"; 696 reg = <0 0x11009000 0 0x1000>, 697 <0 0x10200300 0 0x180>; 698 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 699 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 700 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 701 clock-names = "main", "dma"; 702 clock-div = <1>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 status = "disabled"; 706 }; 707 708 i2c3: i2c@1100f000 { 709 compatible = "mediatek,mt8186-i2c"; 710 reg = <0 0x1100f000 0 0x1000>, 711 <0 0x10200480 0 0x100>; 712 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 713 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 714 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 715 clock-names = "main", "dma"; 716 clock-div = <1>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 i2c4: i2c@11011000 { 723 compatible = "mediatek,mt8186-i2c"; 724 reg = <0 0x11011000 0 0x1000>, 725 <0 0x10200580 0 0x180>; 726 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 727 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 728 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 729 clock-names = "main", "dma"; 730 clock-div = <1>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 i2c5: i2c@11016000 { 737 compatible = "mediatek,mt8186-i2c"; 738 reg = <0 0x11016000 0 0x1000>, 739 <0 0x10200700 0 0x100>; 740 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 741 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 742 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 743 clock-names = "main", "dma"; 744 clock-div = <1>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 i2c6: i2c@1100d000 { 751 compatible = "mediatek,mt8186-i2c"; 752 reg = <0 0x1100d000 0 0x1000>, 753 <0 0x10200800 0 0x100>; 754 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 755 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 756 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 757 clock-names = "main", "dma"; 758 clock-div = <1>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 i2c7: i2c@11004000 { 765 compatible = "mediatek,mt8186-i2c"; 766 reg = <0 0x11004000 0 0x1000>, 767 <0 0x10200900 0 0x180>; 768 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 769 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 770 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 771 clock-names = "main", "dma"; 772 clock-div = <1>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 i2c8: i2c@11005000 { 779 compatible = "mediatek,mt8186-i2c"; 780 reg = <0 0x11005000 0 0x1000>, 781 <0 0x10200A80 0 0x180>; 782 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 783 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 784 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 785 clock-names = "main", "dma"; 786 clock-div = <1>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi0: spi@1100a000 { 793 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 reg = <0 0x1100a000 0 0x1000>; 797 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 798 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 799 <&topckgen CLK_TOP_SPI>, 800 <&infracfg_ao CLK_INFRA_AO_SPI0>; 801 clock-names = "parent-clk", "sel-clk", "spi-clk"; 802 status = "disabled"; 803 }; 804 805 pwm0: pwm@1100e000 { 806 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 807 reg = <0 0x1100e000 0 0x1000>; 808 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 809 #pwm-cells = <2>; 810 clocks = <&topckgen CLK_TOP_DISP_PWM>, 811 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 812 clock-names = "main", "mm"; 813 status = "disabled"; 814 }; 815 816 spi1: spi@11010000 { 817 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 reg = <0 0x11010000 0 0x1000>; 821 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 822 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 823 <&topckgen CLK_TOP_SPI>, 824 <&infracfg_ao CLK_INFRA_AO_SPI1>; 825 clock-names = "parent-clk", "sel-clk", "spi-clk"; 826 status = "disabled"; 827 }; 828 829 spi2: spi@11012000 { 830 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 reg = <0 0x11012000 0 0x1000>; 834 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 835 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 836 <&topckgen CLK_TOP_SPI>, 837 <&infracfg_ao CLK_INFRA_AO_SPI2>; 838 clock-names = "parent-clk", "sel-clk", "spi-clk"; 839 status = "disabled"; 840 }; 841 842 spi3: spi@11013000 { 843 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 reg = <0 0x11013000 0 0x1000>; 847 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 848 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 849 <&topckgen CLK_TOP_SPI>, 850 <&infracfg_ao CLK_INFRA_AO_SPI3>; 851 clock-names = "parent-clk", "sel-clk", "spi-clk"; 852 status = "disabled"; 853 }; 854 855 spi4: spi@11014000 { 856 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 reg = <0 0x11014000 0 0x1000>; 860 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 861 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 862 <&topckgen CLK_TOP_SPI>, 863 <&infracfg_ao CLK_INFRA_AO_SPI4>; 864 clock-names = "parent-clk", "sel-clk", "spi-clk"; 865 status = "disabled"; 866 }; 867 868 spi5: spi@11015000 { 869 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 reg = <0 0x11015000 0 0x1000>; 873 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 874 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 875 <&topckgen CLK_TOP_SPI>, 876 <&infracfg_ao CLK_INFRA_AO_SPI5>; 877 clock-names = "parent-clk", "sel-clk", "spi-clk"; 878 status = "disabled"; 879 }; 880 881 imp_iic_wrap: clock-controller@11017000 { 882 compatible = "mediatek,mt8186-imp_iic_wrap"; 883 reg = <0 0x11017000 0 0x1000>; 884 #clock-cells = <1>; 885 }; 886 887 uart2: serial@11018000 { 888 compatible = "mediatek,mt8186-uart", 889 "mediatek,mt6577-uart"; 890 reg = <0 0x11018000 0 0x1000>; 891 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 892 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 893 clock-names = "baud", "bus"; 894 status = "disabled"; 895 }; 896 897 i2c9: i2c@11019000 { 898 compatible = "mediatek,mt8186-i2c"; 899 reg = <0 0x11019000 0 0x1000>, 900 <0 0x10200c00 0 0x180>; 901 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 902 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 903 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 904 clock-names = "main", "dma"; 905 clock-div = <1>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 status = "disabled"; 909 }; 910 911 mmc0: mmc@11230000 { 912 compatible = "mediatek,mt8186-mmc", 913 "mediatek,mt8183-mmc"; 914 reg = <0 0x11230000 0 0x1000>, 915 <0 0x11cd0000 0 0x1000>; 916 clocks = <&topckgen CLK_TOP_MSDC50_0>, 917 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 918 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 919 clock-names = "source", "hclk", "source_cg"; 920 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 921 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 922 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 923 status = "disabled"; 924 }; 925 926 mmc1: mmc@11240000 { 927 compatible = "mediatek,mt8186-mmc", 928 "mediatek,mt8183-mmc"; 929 reg = <0 0x11240000 0 0x1000>, 930 <0 0x11c90000 0 0x1000>; 931 clocks = <&topckgen CLK_TOP_MSDC30_1>, 932 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 933 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 934 clock-names = "source", "hclk", "source_cg"; 935 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 936 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 937 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 938 status = "disabled"; 939 }; 940 941 u3phy0: t-phy@11c80000 { 942 compatible = "mediatek,mt8186-tphy", 943 "mediatek,generic-tphy-v2"; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 ranges = <0x0 0x0 0x11c80000 0x1000>; 947 status = "disabled"; 948 949 u2port1: usb-phy@0 { 950 reg = <0x0 0x700>; 951 clocks = <&clk26m>; 952 clock-names = "ref"; 953 #phy-cells = <1>; 954 }; 955 956 u3port1: usb-phy@700 { 957 reg = <0x700 0x900>; 958 clocks = <&clk26m>; 959 clock-names = "ref"; 960 #phy-cells = <1>; 961 }; 962 }; 963 964 u3phy1: t-phy@11ca0000 { 965 compatible = "mediatek,mt8186-tphy", 966 "mediatek,generic-tphy-v2"; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 ranges = <0x0 0x0 0x11ca0000 0x1000>; 970 status = "disabled"; 971 972 u2port0: usb-phy@0 { 973 reg = <0x0 0x700>; 974 clocks = <&clk26m>; 975 clock-names = "ref"; 976 #phy-cells = <1>; 977 mediatek,discth = <0x8>; 978 }; 979 }; 980 981 efuse: efuse@11cb0000 { 982 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 983 reg = <0 0x11cb0000 0 0x1000>; 984 #address-cells = <1>; 985 #size-cells = <1>; 986 }; 987 988 mipi_tx0: dsi-phy@11cc0000 { 989 compatible = "mediatek,mt8183-mipi-tx"; 990 reg = <0 0x11cc0000 0 0x1000>; 991 clocks = <&clk26m>; 992 #clock-cells = <0>; 993 #phy-cells = <0>; 994 clock-output-names = "mipi_tx0_pll"; 995 status = "disabled"; 996 }; 997 998 mfgsys: clock-controller@13000000 { 999 compatible = "mediatek,mt8186-mfgsys"; 1000 reg = <0 0x13000000 0 0x1000>; 1001 #clock-cells = <1>; 1002 }; 1003 1004 mmsys: syscon@14000000 { 1005 compatible = "mediatek,mt8186-mmsys", "syscon"; 1006 reg = <0 0x14000000 0 0x1000>; 1007 #clock-cells = <1>; 1008 #reset-cells = <1>; 1009 }; 1010 1011 smi_common: smi@14002000 { 1012 compatible = "mediatek,mt8186-smi-common"; 1013 reg = <0 0x14002000 0 0x1000>; 1014 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1015 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1016 clock-names = "apb", "smi", "gals0", "gals1"; 1017 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1018 }; 1019 1020 larb0: smi@14003000 { 1021 compatible = "mediatek,mt8186-smi-larb"; 1022 reg = <0 0x14003000 0 0x1000>; 1023 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1024 <&mmsys CLK_MM_SMI_COMMON>; 1025 clock-names = "apb", "smi"; 1026 mediatek,larb-id = <0>; 1027 mediatek,smi = <&smi_common>; 1028 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1029 }; 1030 1031 larb1: smi@14004000 { 1032 compatible = "mediatek,mt8186-smi-larb"; 1033 reg = <0 0x14004000 0 0x1000>; 1034 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1035 <&mmsys CLK_MM_SMI_COMMON>; 1036 clock-names = "apb", "smi"; 1037 mediatek,larb-id = <1>; 1038 mediatek,smi = <&smi_common>; 1039 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1040 }; 1041 1042 dsi0: dsi@14013000 { 1043 compatible = "mediatek,mt8186-dsi"; 1044 reg = <0 0x14013000 0 0x1000>; 1045 clocks = <&mmsys CLK_MM_DSI0>, 1046 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1047 <&mipi_tx0>; 1048 clock-names = "engine", "digital", "hs"; 1049 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1050 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1051 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1052 phys = <&mipi_tx0>; 1053 phy-names = "dphy"; 1054 status = "disabled"; 1055 1056 port { 1057 dsi_out: endpoint { }; 1058 }; 1059 }; 1060 1061 iommu_mm: iommu@14016000 { 1062 compatible = "mediatek,mt8186-iommu-mm"; 1063 reg = <0 0x14016000 0 0x1000>; 1064 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1065 clock-names = "bclk"; 1066 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1067 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1068 &larb7 &larb8 &larb9 &larb11 1069 &larb13 &larb14 &larb16 &larb17 1070 &larb19 &larb20>; 1071 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1072 #iommu-cells = <1>; 1073 }; 1074 1075 wpesys: clock-controller@14020000 { 1076 compatible = "mediatek,mt8186-wpesys"; 1077 reg = <0 0x14020000 0 0x1000>; 1078 #clock-cells = <1>; 1079 }; 1080 1081 larb8: smi@14023000 { 1082 compatible = "mediatek,mt8186-smi-larb"; 1083 reg = <0 0x14023000 0 0x1000>; 1084 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1085 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1086 clock-names = "apb", "smi"; 1087 mediatek,larb-id = <8>; 1088 mediatek,smi = <&smi_common>; 1089 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1090 }; 1091 1092 imgsys1: clock-controller@15020000 { 1093 compatible = "mediatek,mt8186-imgsys1"; 1094 reg = <0 0x15020000 0 0x1000>; 1095 #clock-cells = <1>; 1096 }; 1097 1098 larb9: smi@1502e000 { 1099 compatible = "mediatek,mt8186-smi-larb"; 1100 reg = <0 0x1502e000 0 0x1000>; 1101 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1102 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1103 clock-names = "apb", "smi"; 1104 mediatek,larb-id = <9>; 1105 mediatek,smi = <&smi_common>; 1106 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1107 }; 1108 1109 imgsys2: clock-controller@15820000 { 1110 compatible = "mediatek,mt8186-imgsys2"; 1111 reg = <0 0x15820000 0 0x1000>; 1112 #clock-cells = <1>; 1113 }; 1114 1115 larb11: smi@1582e000 { 1116 compatible = "mediatek,mt8186-smi-larb"; 1117 reg = <0 0x1582e000 0 0x1000>; 1118 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1119 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1120 clock-names = "apb", "smi"; 1121 mediatek,larb-id = <11>; 1122 mediatek,smi = <&smi_common>; 1123 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1124 }; 1125 1126 larb4: smi@1602e000 { 1127 compatible = "mediatek,mt8186-smi-larb"; 1128 reg = <0 0x1602e000 0 0x1000>; 1129 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1130 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1131 clock-names = "apb", "smi"; 1132 mediatek,larb-id = <4>; 1133 mediatek,smi = <&smi_common>; 1134 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1135 }; 1136 1137 vdecsys: clock-controller@1602f000 { 1138 compatible = "mediatek,mt8186-vdecsys"; 1139 reg = <0 0x1602f000 0 0x1000>; 1140 #clock-cells = <1>; 1141 }; 1142 1143 vencsys: clock-controller@17000000 { 1144 compatible = "mediatek,mt8186-vencsys"; 1145 reg = <0 0x17000000 0 0x1000>; 1146 #clock-cells = <1>; 1147 }; 1148 1149 larb7: smi@17010000 { 1150 compatible = "mediatek,mt8186-smi-larb"; 1151 reg = <0 0x17010000 0 0x1000>; 1152 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1153 <&vencsys CLK_VENC_CKE1_VENC>; 1154 clock-names = "apb", "smi"; 1155 mediatek,larb-id = <7>; 1156 mediatek,smi = <&smi_common>; 1157 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1158 }; 1159 1160 camsys: clock-controller@1a000000 { 1161 compatible = "mediatek,mt8186-camsys"; 1162 reg = <0 0x1a000000 0 0x1000>; 1163 #clock-cells = <1>; 1164 }; 1165 1166 larb13: smi@1a001000 { 1167 compatible = "mediatek,mt8186-smi-larb"; 1168 reg = <0 0x1a001000 0 0x1000>; 1169 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1170 clock-names = "apb", "smi"; 1171 mediatek,larb-id = <13>; 1172 mediatek,smi = <&smi_common>; 1173 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1174 }; 1175 1176 larb14: smi@1a002000 { 1177 compatible = "mediatek,mt8186-smi-larb"; 1178 reg = <0 0x1a002000 0 0x1000>; 1179 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1180 clock-names = "apb", "smi"; 1181 mediatek,larb-id = <14>; 1182 mediatek,smi = <&smi_common>; 1183 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1184 }; 1185 1186 larb16: smi@1a00f000 { 1187 compatible = "mediatek,mt8186-smi-larb"; 1188 reg = <0 0x1a00f000 0 0x1000>; 1189 clocks = <&camsys CLK_CAM_LARB14>, 1190 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1191 clock-names = "apb", "smi"; 1192 mediatek,larb-id = <16>; 1193 mediatek,smi = <&smi_common>; 1194 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1195 }; 1196 1197 larb17: smi@1a010000 { 1198 compatible = "mediatek,mt8186-smi-larb"; 1199 reg = <0 0x1a010000 0 0x1000>; 1200 clocks = <&camsys CLK_CAM_LARB13>, 1201 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1202 clock-names = "apb", "smi"; 1203 mediatek,larb-id = <17>; 1204 mediatek,smi = <&smi_common>; 1205 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1206 }; 1207 1208 camsys_rawa: clock-controller@1a04f000 { 1209 compatible = "mediatek,mt8186-camsys_rawa"; 1210 reg = <0 0x1a04f000 0 0x1000>; 1211 #clock-cells = <1>; 1212 }; 1213 1214 camsys_rawb: clock-controller@1a06f000 { 1215 compatible = "mediatek,mt8186-camsys_rawb"; 1216 reg = <0 0x1a06f000 0 0x1000>; 1217 #clock-cells = <1>; 1218 }; 1219 1220 mdpsys: clock-controller@1b000000 { 1221 compatible = "mediatek,mt8186-mdpsys"; 1222 reg = <0 0x1b000000 0 0x1000>; 1223 #clock-cells = <1>; 1224 }; 1225 1226 larb2: smi@1b002000 { 1227 compatible = "mediatek,mt8186-smi-larb"; 1228 reg = <0 0x1b002000 0 0x1000>; 1229 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1230 clock-names = "apb", "smi"; 1231 mediatek,larb-id = <2>; 1232 mediatek,smi = <&smi_common>; 1233 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1234 }; 1235 1236 ipesys: clock-controller@1c000000 { 1237 compatible = "mediatek,mt8186-ipesys"; 1238 reg = <0 0x1c000000 0 0x1000>; 1239 #clock-cells = <1>; 1240 }; 1241 1242 larb20: smi@1c00f000 { 1243 compatible = "mediatek,mt8186-smi-larb"; 1244 reg = <0 0x1c00f000 0 0x1000>; 1245 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1246 clock-names = "apb", "smi"; 1247 mediatek,larb-id = <20>; 1248 mediatek,smi = <&smi_common>; 1249 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1250 }; 1251 1252 larb19: smi@1c10f000 { 1253 compatible = "mediatek,mt8186-smi-larb"; 1254 reg = <0 0x1c10f000 0 0x1000>; 1255 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1256 clock-names = "apb", "smi"; 1257 mediatek,larb-id = <19>; 1258 mediatek,smi = <&smi_common>; 1259 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1260 }; 1261 }; 1262}; 1263