1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cci: cci { 284 compatible = "mediatek,mt8183-cci"; 285 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 clock-names = "cci", "intermediate"; 288 operating-points-v2 = <&cci_opp>; 289 }; 290 291 cpus { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&cpu0>; 299 }; 300 core1 { 301 cpu = <&cpu1>; 302 }; 303 core2 { 304 cpu = <&cpu2>; 305 }; 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 }; 310 311 cluster1 { 312 core0 { 313 cpu = <&cpu4>; 314 }; 315 core1 { 316 cpu = <&cpu5>; 317 }; 318 core2 { 319 cpu = <&cpu6>; 320 }; 321 core3 { 322 cpu = <&cpu7>; 323 }; 324 }; 325 }; 326 327 cpu0: cpu@0 { 328 device_type = "cpu"; 329 compatible = "arm,cortex-a53"; 330 reg = <0x000>; 331 enable-method = "psci"; 332 capacity-dmips-mhz = <741>; 333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 336 clock-names = "cpu", "intermediate"; 337 operating-points-v2 = <&cluster0_opp>; 338 dynamic-power-coefficient = <84>; 339 #cooling-cells = <2>; 340 }; 341 342 cpu1: cpu@1 { 343 device_type = "cpu"; 344 compatible = "arm,cortex-a53"; 345 reg = <0x001>; 346 enable-method = "psci"; 347 capacity-dmips-mhz = <741>; 348 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 349 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 350 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 351 clock-names = "cpu", "intermediate"; 352 operating-points-v2 = <&cluster0_opp>; 353 dynamic-power-coefficient = <84>; 354 #cooling-cells = <2>; 355 }; 356 357 cpu2: cpu@2 { 358 device_type = "cpu"; 359 compatible = "arm,cortex-a53"; 360 reg = <0x002>; 361 enable-method = "psci"; 362 capacity-dmips-mhz = <741>; 363 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 364 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 365 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 366 clock-names = "cpu", "intermediate"; 367 operating-points-v2 = <&cluster0_opp>; 368 dynamic-power-coefficient = <84>; 369 #cooling-cells = <2>; 370 }; 371 372 cpu3: cpu@3 { 373 device_type = "cpu"; 374 compatible = "arm,cortex-a53"; 375 reg = <0x003>; 376 enable-method = "psci"; 377 capacity-dmips-mhz = <741>; 378 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 379 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 380 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 381 clock-names = "cpu", "intermediate"; 382 operating-points-v2 = <&cluster0_opp>; 383 dynamic-power-coefficient = <84>; 384 #cooling-cells = <2>; 385 }; 386 387 cpu4: cpu@100 { 388 device_type = "cpu"; 389 compatible = "arm,cortex-a73"; 390 reg = <0x100>; 391 enable-method = "psci"; 392 capacity-dmips-mhz = <1024>; 393 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 394 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 395 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 396 clock-names = "cpu", "intermediate"; 397 operating-points-v2 = <&cluster1_opp>; 398 dynamic-power-coefficient = <211>; 399 #cooling-cells = <2>; 400 }; 401 402 cpu5: cpu@101 { 403 device_type = "cpu"; 404 compatible = "arm,cortex-a73"; 405 reg = <0x101>; 406 enable-method = "psci"; 407 capacity-dmips-mhz = <1024>; 408 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 409 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 410 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 411 clock-names = "cpu", "intermediate"; 412 operating-points-v2 = <&cluster1_opp>; 413 dynamic-power-coefficient = <211>; 414 #cooling-cells = <2>; 415 }; 416 417 cpu6: cpu@102 { 418 device_type = "cpu"; 419 compatible = "arm,cortex-a73"; 420 reg = <0x102>; 421 enable-method = "psci"; 422 capacity-dmips-mhz = <1024>; 423 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 424 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 425 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 426 clock-names = "cpu", "intermediate"; 427 operating-points-v2 = <&cluster1_opp>; 428 dynamic-power-coefficient = <211>; 429 #cooling-cells = <2>; 430 }; 431 432 cpu7: cpu@103 { 433 device_type = "cpu"; 434 compatible = "arm,cortex-a73"; 435 reg = <0x103>; 436 enable-method = "psci"; 437 capacity-dmips-mhz = <1024>; 438 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 439 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 440 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 441 clock-names = "cpu", "intermediate"; 442 operating-points-v2 = <&cluster1_opp>; 443 dynamic-power-coefficient = <211>; 444 #cooling-cells = <2>; 445 }; 446 447 idle-states { 448 entry-method = "psci"; 449 450 CPU_SLEEP: cpu-sleep { 451 compatible = "arm,idle-state"; 452 local-timer-stop; 453 arm,psci-suspend-param = <0x00010001>; 454 entry-latency-us = <200>; 455 exit-latency-us = <200>; 456 min-residency-us = <800>; 457 }; 458 459 CLUSTER_SLEEP0: cluster-sleep-0 { 460 compatible = "arm,idle-state"; 461 local-timer-stop; 462 arm,psci-suspend-param = <0x01010001>; 463 entry-latency-us = <250>; 464 exit-latency-us = <400>; 465 min-residency-us = <1000>; 466 }; 467 CLUSTER_SLEEP1: cluster-sleep-1 { 468 compatible = "arm,idle-state"; 469 local-timer-stop; 470 arm,psci-suspend-param = <0x01010001>; 471 entry-latency-us = <250>; 472 exit-latency-us = <400>; 473 min-residency-us = <1300>; 474 }; 475 }; 476 }; 477 478 gpu_opp_table: opp-table-0 { 479 compatible = "operating-points-v2"; 480 opp-shared; 481 482 opp-300000000 { 483 opp-hz = /bits/ 64 <300000000>; 484 opp-microvolt = <625000>, <850000>; 485 }; 486 487 opp-320000000 { 488 opp-hz = /bits/ 64 <320000000>; 489 opp-microvolt = <631250>, <850000>; 490 }; 491 492 opp-340000000 { 493 opp-hz = /bits/ 64 <340000000>; 494 opp-microvolt = <637500>, <850000>; 495 }; 496 497 opp-360000000 { 498 opp-hz = /bits/ 64 <360000000>; 499 opp-microvolt = <643750>, <850000>; 500 }; 501 502 opp-380000000 { 503 opp-hz = /bits/ 64 <380000000>; 504 opp-microvolt = <650000>, <850000>; 505 }; 506 507 opp-400000000 { 508 opp-hz = /bits/ 64 <400000000>; 509 opp-microvolt = <656250>, <850000>; 510 }; 511 512 opp-420000000 { 513 opp-hz = /bits/ 64 <420000000>; 514 opp-microvolt = <662500>, <850000>; 515 }; 516 517 opp-460000000 { 518 opp-hz = /bits/ 64 <460000000>; 519 opp-microvolt = <675000>, <850000>; 520 }; 521 522 opp-500000000 { 523 opp-hz = /bits/ 64 <500000000>; 524 opp-microvolt = <687500>, <850000>; 525 }; 526 527 opp-540000000 { 528 opp-hz = /bits/ 64 <540000000>; 529 opp-microvolt = <700000>, <850000>; 530 }; 531 532 opp-580000000 { 533 opp-hz = /bits/ 64 <580000000>; 534 opp-microvolt = <712500>, <850000>; 535 }; 536 537 opp-620000000 { 538 opp-hz = /bits/ 64 <620000000>; 539 opp-microvolt = <725000>, <850000>; 540 }; 541 542 opp-653000000 { 543 opp-hz = /bits/ 64 <653000000>; 544 opp-microvolt = <743750>, <850000>; 545 }; 546 547 opp-698000000 { 548 opp-hz = /bits/ 64 <698000000>; 549 opp-microvolt = <768750>, <868750>; 550 }; 551 552 opp-743000000 { 553 opp-hz = /bits/ 64 <743000000>; 554 opp-microvolt = <793750>, <893750>; 555 }; 556 557 opp-800000000 { 558 opp-hz = /bits/ 64 <800000000>; 559 opp-microvolt = <825000>, <925000>; 560 }; 561 }; 562 563 pmu-a53 { 564 compatible = "arm,cortex-a53-pmu"; 565 interrupt-parent = <&gic>; 566 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 567 }; 568 569 pmu-a73 { 570 compatible = "arm,cortex-a73-pmu"; 571 interrupt-parent = <&gic>; 572 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 573 }; 574 575 psci { 576 compatible = "arm,psci-1.0"; 577 method = "smc"; 578 }; 579 580 clk26m: oscillator { 581 compatible = "fixed-clock"; 582 #clock-cells = <0>; 583 clock-frequency = <26000000>; 584 clock-output-names = "clk26m"; 585 }; 586 587 timer { 588 compatible = "arm,armv8-timer"; 589 interrupt-parent = <&gic>; 590 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 591 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 592 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 593 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 594 }; 595 596 soc { 597 #address-cells = <2>; 598 #size-cells = <2>; 599 compatible = "simple-bus"; 600 ranges; 601 602 soc_data: soc_data@8000000 { 603 compatible = "mediatek,mt8183-efuse", 604 "mediatek,efuse"; 605 reg = <0 0x08000000 0 0x0010>; 606 #address-cells = <1>; 607 #size-cells = <1>; 608 status = "disabled"; 609 }; 610 611 gic: interrupt-controller@c000000 { 612 compatible = "arm,gic-v3"; 613 #interrupt-cells = <4>; 614 interrupt-parent = <&gic>; 615 interrupt-controller; 616 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 617 <0 0x0c100000 0 0x200000>, /* GICR */ 618 <0 0x0c400000 0 0x2000>, /* GICC */ 619 <0 0x0c410000 0 0x1000>, /* GICH */ 620 <0 0x0c420000 0 0x2000>; /* GICV */ 621 622 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 623 ppi-partitions { 624 ppi_cluster0: interrupt-partition-0 { 625 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 626 }; 627 ppi_cluster1: interrupt-partition-1 { 628 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 629 }; 630 }; 631 }; 632 633 mcucfg: syscon@c530000 { 634 compatible = "mediatek,mt8183-mcucfg", "syscon"; 635 reg = <0 0x0c530000 0 0x1000>; 636 #clock-cells = <1>; 637 }; 638 639 sysirq: interrupt-controller@c530a80 { 640 compatible = "mediatek,mt8183-sysirq", 641 "mediatek,mt6577-sysirq"; 642 interrupt-controller; 643 #interrupt-cells = <3>; 644 interrupt-parent = <&gic>; 645 reg = <0 0x0c530a80 0 0x50>; 646 }; 647 648 cpu_debug0: cpu-debug@d410000 { 649 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 650 reg = <0x0 0xd410000 0x0 0x1000>; 651 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 652 clock-names = "apb_pclk"; 653 cpu = <&cpu0>; 654 }; 655 656 cpu_debug1: cpu-debug@d510000 { 657 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 658 reg = <0x0 0xd510000 0x0 0x1000>; 659 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 660 clock-names = "apb_pclk"; 661 cpu = <&cpu1>; 662 }; 663 664 cpu_debug2: cpu-debug@d610000 { 665 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 666 reg = <0x0 0xd610000 0x0 0x1000>; 667 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 668 clock-names = "apb_pclk"; 669 cpu = <&cpu2>; 670 }; 671 672 cpu_debug3: cpu-debug@d710000 { 673 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 674 reg = <0x0 0xd710000 0x0 0x1000>; 675 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 676 clock-names = "apb_pclk"; 677 cpu = <&cpu3>; 678 }; 679 680 cpu_debug4: cpu-debug@d810000 { 681 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 682 reg = <0x0 0xd810000 0x0 0x1000>; 683 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 684 clock-names = "apb_pclk"; 685 cpu = <&cpu4>; 686 }; 687 688 cpu_debug5: cpu-debug@d910000 { 689 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 690 reg = <0x0 0xd910000 0x0 0x1000>; 691 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 692 clock-names = "apb_pclk"; 693 cpu = <&cpu5>; 694 }; 695 696 cpu_debug6: cpu-debug@da10000 { 697 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 698 reg = <0x0 0xda10000 0x0 0x1000>; 699 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 700 clock-names = "apb_pclk"; 701 cpu = <&cpu6>; 702 }; 703 704 cpu_debug7: cpu-debug@db10000 { 705 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 706 reg = <0x0 0xdb10000 0x0 0x1000>; 707 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 708 clock-names = "apb_pclk"; 709 cpu = <&cpu7>; 710 }; 711 712 topckgen: syscon@10000000 { 713 compatible = "mediatek,mt8183-topckgen", "syscon"; 714 reg = <0 0x10000000 0 0x1000>; 715 #clock-cells = <1>; 716 }; 717 718 infracfg: syscon@10001000 { 719 compatible = "mediatek,mt8183-infracfg", "syscon"; 720 reg = <0 0x10001000 0 0x1000>; 721 #clock-cells = <1>; 722 #reset-cells = <1>; 723 }; 724 725 pericfg: syscon@10003000 { 726 compatible = "mediatek,mt8183-pericfg", "syscon"; 727 reg = <0 0x10003000 0 0x1000>; 728 #clock-cells = <1>; 729 }; 730 731 pio: pinctrl@10005000 { 732 compatible = "mediatek,mt8183-pinctrl"; 733 reg = <0 0x10005000 0 0x1000>, 734 <0 0x11f20000 0 0x1000>, 735 <0 0x11e80000 0 0x1000>, 736 <0 0x11e70000 0 0x1000>, 737 <0 0x11e90000 0 0x1000>, 738 <0 0x11d30000 0 0x1000>, 739 <0 0x11d20000 0 0x1000>, 740 <0 0x11c50000 0 0x1000>, 741 <0 0x11f30000 0 0x1000>, 742 <0 0x1000b000 0 0x1000>; 743 reg-names = "iocfg0", "iocfg1", "iocfg2", 744 "iocfg3", "iocfg4", "iocfg5", 745 "iocfg6", "iocfg7", "iocfg8", 746 "eint"; 747 gpio-controller; 748 #gpio-cells = <2>; 749 gpio-ranges = <&pio 0 0 192>; 750 interrupt-controller; 751 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 752 #interrupt-cells = <2>; 753 }; 754 755 scpsys: syscon@10006000 { 756 compatible = "syscon", "simple-mfd"; 757 reg = <0 0x10006000 0 0x1000>; 758 #power-domain-cells = <1>; 759 760 /* System Power Manager */ 761 spm: power-controller { 762 compatible = "mediatek,mt8183-power-controller"; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 #power-domain-cells = <1>; 766 767 /* power domain of the SoC */ 768 power-domain@MT8183_POWER_DOMAIN_AUDIO { 769 reg = <MT8183_POWER_DOMAIN_AUDIO>; 770 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 771 <&infracfg CLK_INFRA_AUDIO>, 772 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 773 clock-names = "audio", "audio1", "audio2"; 774 #power-domain-cells = <0>; 775 }; 776 777 power-domain@MT8183_POWER_DOMAIN_CONN { 778 reg = <MT8183_POWER_DOMAIN_CONN>; 779 mediatek,infracfg = <&infracfg>; 780 #power-domain-cells = <0>; 781 }; 782 783 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 784 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 785 clocks = <&topckgen CLK_TOP_MUX_MFG>; 786 clock-names = "mfg"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 #power-domain-cells = <1>; 790 791 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 792 reg = <MT8183_POWER_DOMAIN_MFG>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 #power-domain-cells = <1>; 796 797 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 798 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 799 #power-domain-cells = <0>; 800 }; 801 802 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 803 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 804 #power-domain-cells = <0>; 805 }; 806 807 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 808 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 809 mediatek,infracfg = <&infracfg>; 810 #power-domain-cells = <0>; 811 }; 812 }; 813 }; 814 815 power-domain@MT8183_POWER_DOMAIN_DISP { 816 reg = <MT8183_POWER_DOMAIN_DISP>; 817 clocks = <&topckgen CLK_TOP_MUX_MM>, 818 <&mmsys CLK_MM_SMI_COMMON>, 819 <&mmsys CLK_MM_SMI_LARB0>, 820 <&mmsys CLK_MM_SMI_LARB1>, 821 <&mmsys CLK_MM_GALS_COMM0>, 822 <&mmsys CLK_MM_GALS_COMM1>, 823 <&mmsys CLK_MM_GALS_CCU2MM>, 824 <&mmsys CLK_MM_GALS_IPU12MM>, 825 <&mmsys CLK_MM_GALS_IMG2MM>, 826 <&mmsys CLK_MM_GALS_CAM2MM>, 827 <&mmsys CLK_MM_GALS_IPU2MM>; 828 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 829 "mm-4", "mm-5", "mm-6", "mm-7", 830 "mm-8", "mm-9"; 831 mediatek,infracfg = <&infracfg>; 832 mediatek,smi = <&smi_common>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 #power-domain-cells = <1>; 836 837 power-domain@MT8183_POWER_DOMAIN_CAM { 838 reg = <MT8183_POWER_DOMAIN_CAM>; 839 clocks = <&topckgen CLK_TOP_MUX_CAM>, 840 <&camsys CLK_CAM_LARB6>, 841 <&camsys CLK_CAM_LARB3>, 842 <&camsys CLK_CAM_SENINF>, 843 <&camsys CLK_CAM_CAMSV0>, 844 <&camsys CLK_CAM_CAMSV1>, 845 <&camsys CLK_CAM_CAMSV2>, 846 <&camsys CLK_CAM_CCU>; 847 clock-names = "cam", "cam-0", "cam-1", 848 "cam-2", "cam-3", "cam-4", 849 "cam-5", "cam-6"; 850 mediatek,infracfg = <&infracfg>; 851 mediatek,smi = <&smi_common>; 852 #power-domain-cells = <0>; 853 }; 854 855 power-domain@MT8183_POWER_DOMAIN_ISP { 856 reg = <MT8183_POWER_DOMAIN_ISP>; 857 clocks = <&topckgen CLK_TOP_MUX_IMG>, 858 <&imgsys CLK_IMG_LARB5>, 859 <&imgsys CLK_IMG_LARB2>; 860 clock-names = "isp", "isp-0", "isp-1"; 861 mediatek,infracfg = <&infracfg>; 862 mediatek,smi = <&smi_common>; 863 #power-domain-cells = <0>; 864 }; 865 866 power-domain@MT8183_POWER_DOMAIN_VDEC { 867 reg = <MT8183_POWER_DOMAIN_VDEC>; 868 mediatek,smi = <&smi_common>; 869 #power-domain-cells = <0>; 870 }; 871 872 power-domain@MT8183_POWER_DOMAIN_VENC { 873 reg = <MT8183_POWER_DOMAIN_VENC>; 874 mediatek,smi = <&smi_common>; 875 #power-domain-cells = <0>; 876 }; 877 878 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 879 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 880 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 881 <&topckgen CLK_TOP_MUX_DSP>, 882 <&ipu_conn CLK_IPU_CONN_IPU>, 883 <&ipu_conn CLK_IPU_CONN_AHB>, 884 <&ipu_conn CLK_IPU_CONN_AXI>, 885 <&ipu_conn CLK_IPU_CONN_ISP>, 886 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 887 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 888 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 889 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 890 mediatek,infracfg = <&infracfg>; 891 mediatek,smi = <&smi_common>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 #power-domain-cells = <1>; 895 896 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 897 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 898 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 899 clock-names = "vpu2"; 900 mediatek,infracfg = <&infracfg>; 901 #power-domain-cells = <0>; 902 }; 903 904 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 905 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 906 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 907 clock-names = "vpu3"; 908 mediatek,infracfg = <&infracfg>; 909 #power-domain-cells = <0>; 910 }; 911 }; 912 }; 913 }; 914 }; 915 916 watchdog: watchdog@10007000 { 917 compatible = "mediatek,mt8183-wdt"; 918 reg = <0 0x10007000 0 0x100>; 919 #reset-cells = <1>; 920 }; 921 922 apmixedsys: syscon@1000c000 { 923 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 924 reg = <0 0x1000c000 0 0x1000>; 925 #clock-cells = <1>; 926 }; 927 928 pwrap: pwrap@1000d000 { 929 compatible = "mediatek,mt8183-pwrap"; 930 reg = <0 0x1000d000 0 0x1000>; 931 reg-names = "pwrap"; 932 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 934 <&infracfg CLK_INFRA_PMIC_AP>; 935 clock-names = "spi", "wrap"; 936 }; 937 938 scp: scp@10500000 { 939 compatible = "mediatek,mt8183-scp"; 940 reg = <0 0x10500000 0 0x80000>, 941 <0 0x105c0000 0 0x19080>; 942 reg-names = "sram", "cfg"; 943 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&infracfg CLK_INFRA_SCPSYS>; 945 clock-names = "main"; 946 memory-region = <&scp_mem_reserved>; 947 status = "disabled"; 948 }; 949 950 systimer: timer@10017000 { 951 compatible = "mediatek,mt8183-timer", 952 "mediatek,mt6765-timer"; 953 reg = <0 0x10017000 0 0x1000>; 954 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&topckgen CLK_TOP_CLK13M>; 956 clock-names = "clk13m"; 957 }; 958 959 iommu: iommu@10205000 { 960 compatible = "mediatek,mt8183-m4u"; 961 reg = <0 0x10205000 0 0x1000>; 962 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 963 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 964 <&larb4>, <&larb5>, <&larb6>; 965 #iommu-cells = <1>; 966 }; 967 968 gce: mailbox@10238000 { 969 compatible = "mediatek,mt8183-gce"; 970 reg = <0 0x10238000 0 0x4000>; 971 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 972 #mbox-cells = <2>; 973 clocks = <&infracfg CLK_INFRA_GCE>; 974 clock-names = "gce"; 975 }; 976 977 auxadc: auxadc@11001000 { 978 compatible = "mediatek,mt8183-auxadc", 979 "mediatek,mt8173-auxadc"; 980 reg = <0 0x11001000 0 0x1000>; 981 clocks = <&infracfg CLK_INFRA_AUXADC>; 982 clock-names = "main"; 983 #io-channel-cells = <1>; 984 status = "disabled"; 985 }; 986 987 uart0: serial@11002000 { 988 compatible = "mediatek,mt8183-uart", 989 "mediatek,mt6577-uart"; 990 reg = <0 0x11002000 0 0x1000>; 991 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 992 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 993 clock-names = "baud", "bus"; 994 status = "disabled"; 995 }; 996 997 uart1: serial@11003000 { 998 compatible = "mediatek,mt8183-uart", 999 "mediatek,mt6577-uart"; 1000 reg = <0 0x11003000 0 0x1000>; 1001 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 1002 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 1003 clock-names = "baud", "bus"; 1004 status = "disabled"; 1005 }; 1006 1007 uart2: serial@11004000 { 1008 compatible = "mediatek,mt8183-uart", 1009 "mediatek,mt6577-uart"; 1010 reg = <0 0x11004000 0 0x1000>; 1011 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1012 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1013 clock-names = "baud", "bus"; 1014 status = "disabled"; 1015 }; 1016 1017 i2c6: i2c@11005000 { 1018 compatible = "mediatek,mt8183-i2c"; 1019 reg = <0 0x11005000 0 0x1000>, 1020 <0 0x11000600 0 0x80>; 1021 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1022 clocks = <&infracfg CLK_INFRA_I2C6>, 1023 <&infracfg CLK_INFRA_AP_DMA>; 1024 clock-names = "main", "dma"; 1025 clock-div = <1>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 i2c0: i2c@11007000 { 1032 compatible = "mediatek,mt8183-i2c"; 1033 reg = <0 0x11007000 0 0x1000>, 1034 <0 0x11000080 0 0x80>; 1035 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1036 clocks = <&infracfg CLK_INFRA_I2C0>, 1037 <&infracfg CLK_INFRA_AP_DMA>; 1038 clock-names = "main", "dma"; 1039 clock-div = <1>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c4: i2c@11008000 { 1046 compatible = "mediatek,mt8183-i2c"; 1047 reg = <0 0x11008000 0 0x1000>, 1048 <0 0x11000100 0 0x80>; 1049 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1050 clocks = <&infracfg CLK_INFRA_I2C1>, 1051 <&infracfg CLK_INFRA_AP_DMA>, 1052 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1053 clock-names = "main", "dma","arb"; 1054 clock-div = <1>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 status = "disabled"; 1058 }; 1059 1060 i2c2: i2c@11009000 { 1061 compatible = "mediatek,mt8183-i2c"; 1062 reg = <0 0x11009000 0 0x1000>, 1063 <0 0x11000280 0 0x80>; 1064 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1065 clocks = <&infracfg CLK_INFRA_I2C2>, 1066 <&infracfg CLK_INFRA_AP_DMA>, 1067 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1068 clock-names = "main", "dma", "arb"; 1069 clock-div = <1>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 spi0: spi@1100a000 { 1076 compatible = "mediatek,mt8183-spi"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 reg = <0 0x1100a000 0 0x1000>; 1080 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1081 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1082 <&topckgen CLK_TOP_MUX_SPI>, 1083 <&infracfg CLK_INFRA_SPI0>; 1084 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1085 status = "disabled"; 1086 }; 1087 1088 thermal: thermal@1100b000 { 1089 #thermal-sensor-cells = <1>; 1090 compatible = "mediatek,mt8183-thermal"; 1091 reg = <0 0x1100b000 0 0x1000>; 1092 clocks = <&infracfg CLK_INFRA_THERM>, 1093 <&infracfg CLK_INFRA_AUXADC>; 1094 clock-names = "therm", "auxadc"; 1095 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1096 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1097 mediatek,auxadc = <&auxadc>; 1098 mediatek,apmixedsys = <&apmixedsys>; 1099 nvmem-cells = <&thermal_calibration>; 1100 nvmem-cell-names = "calibration-data"; 1101 }; 1102 1103 thermal_zones: thermal-zones { 1104 cpu_thermal: cpu-thermal { 1105 polling-delay-passive = <100>; 1106 polling-delay = <500>; 1107 thermal-sensors = <&thermal 0>; 1108 sustainable-power = <5000>; 1109 1110 trips { 1111 threshold: trip-point0 { 1112 temperature = <68000>; 1113 hysteresis = <2000>; 1114 type = "passive"; 1115 }; 1116 1117 target: trip-point1 { 1118 temperature = <80000>; 1119 hysteresis = <2000>; 1120 type = "passive"; 1121 }; 1122 1123 cpu_crit: cpu-crit { 1124 temperature = <115000>; 1125 hysteresis = <2000>; 1126 type = "critical"; 1127 }; 1128 }; 1129 1130 cooling-maps { 1131 map0 { 1132 trip = <&target>; 1133 cooling-device = <&cpu0 1134 THERMAL_NO_LIMIT 1135 THERMAL_NO_LIMIT>, 1136 <&cpu1 1137 THERMAL_NO_LIMIT 1138 THERMAL_NO_LIMIT>, 1139 <&cpu2 1140 THERMAL_NO_LIMIT 1141 THERMAL_NO_LIMIT>, 1142 <&cpu3 1143 THERMAL_NO_LIMIT 1144 THERMAL_NO_LIMIT>; 1145 contribution = <3072>; 1146 }; 1147 map1 { 1148 trip = <&target>; 1149 cooling-device = <&cpu4 1150 THERMAL_NO_LIMIT 1151 THERMAL_NO_LIMIT>, 1152 <&cpu5 1153 THERMAL_NO_LIMIT 1154 THERMAL_NO_LIMIT>, 1155 <&cpu6 1156 THERMAL_NO_LIMIT 1157 THERMAL_NO_LIMIT>, 1158 <&cpu7 1159 THERMAL_NO_LIMIT 1160 THERMAL_NO_LIMIT>; 1161 contribution = <1024>; 1162 }; 1163 }; 1164 }; 1165 1166 /* The tzts1 ~ tzts6 don't need to polling */ 1167 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 1168 1169 tzts1: tzts1 { 1170 polling-delay-passive = <0>; 1171 polling-delay = <0>; 1172 thermal-sensors = <&thermal 1>; 1173 sustainable-power = <5000>; 1174 trips {}; 1175 cooling-maps {}; 1176 }; 1177 1178 tzts2: tzts2 { 1179 polling-delay-passive = <0>; 1180 polling-delay = <0>; 1181 thermal-sensors = <&thermal 2>; 1182 sustainable-power = <5000>; 1183 trips {}; 1184 cooling-maps {}; 1185 }; 1186 1187 tzts3: tzts3 { 1188 polling-delay-passive = <0>; 1189 polling-delay = <0>; 1190 thermal-sensors = <&thermal 3>; 1191 sustainable-power = <5000>; 1192 trips {}; 1193 cooling-maps {}; 1194 }; 1195 1196 tzts4: tzts4 { 1197 polling-delay-passive = <0>; 1198 polling-delay = <0>; 1199 thermal-sensors = <&thermal 4>; 1200 sustainable-power = <5000>; 1201 trips {}; 1202 cooling-maps {}; 1203 }; 1204 1205 tzts5: tzts5 { 1206 polling-delay-passive = <0>; 1207 polling-delay = <0>; 1208 thermal-sensors = <&thermal 5>; 1209 sustainable-power = <5000>; 1210 trips {}; 1211 cooling-maps {}; 1212 }; 1213 1214 tztsABB: tztsABB { 1215 polling-delay-passive = <0>; 1216 polling-delay = <0>; 1217 thermal-sensors = <&thermal 6>; 1218 sustainable-power = <5000>; 1219 trips {}; 1220 cooling-maps {}; 1221 }; 1222 }; 1223 1224 pwm0: pwm@1100e000 { 1225 compatible = "mediatek,mt8183-disp-pwm"; 1226 reg = <0 0x1100e000 0 0x1000>; 1227 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1228 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1229 #pwm-cells = <2>; 1230 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1231 <&infracfg CLK_INFRA_DISP_PWM>; 1232 clock-names = "main", "mm"; 1233 }; 1234 1235 pwm1: pwm@11006000 { 1236 compatible = "mediatek,mt8183-pwm"; 1237 reg = <0 0x11006000 0 0x1000>; 1238 #pwm-cells = <2>; 1239 clocks = <&infracfg CLK_INFRA_PWM>, 1240 <&infracfg CLK_INFRA_PWM_HCLK>, 1241 <&infracfg CLK_INFRA_PWM1>, 1242 <&infracfg CLK_INFRA_PWM2>, 1243 <&infracfg CLK_INFRA_PWM3>, 1244 <&infracfg CLK_INFRA_PWM4>; 1245 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1246 "pwm4"; 1247 }; 1248 1249 i2c3: i2c@1100f000 { 1250 compatible = "mediatek,mt8183-i2c"; 1251 reg = <0 0x1100f000 0 0x1000>, 1252 <0 0x11000400 0 0x80>; 1253 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1254 clocks = <&infracfg CLK_INFRA_I2C3>, 1255 <&infracfg CLK_INFRA_AP_DMA>; 1256 clock-names = "main", "dma"; 1257 clock-div = <1>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 spi1: spi@11010000 { 1264 compatible = "mediatek,mt8183-spi"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 reg = <0 0x11010000 0 0x1000>; 1268 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1269 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1270 <&topckgen CLK_TOP_MUX_SPI>, 1271 <&infracfg CLK_INFRA_SPI1>; 1272 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1273 status = "disabled"; 1274 }; 1275 1276 i2c1: i2c@11011000 { 1277 compatible = "mediatek,mt8183-i2c"; 1278 reg = <0 0x11011000 0 0x1000>, 1279 <0 0x11000480 0 0x80>; 1280 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1281 clocks = <&infracfg CLK_INFRA_I2C4>, 1282 <&infracfg CLK_INFRA_AP_DMA>; 1283 clock-names = "main", "dma"; 1284 clock-div = <1>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 spi2: spi@11012000 { 1291 compatible = "mediatek,mt8183-spi"; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 reg = <0 0x11012000 0 0x1000>; 1295 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1296 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1297 <&topckgen CLK_TOP_MUX_SPI>, 1298 <&infracfg CLK_INFRA_SPI2>; 1299 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1300 status = "disabled"; 1301 }; 1302 1303 spi3: spi@11013000 { 1304 compatible = "mediatek,mt8183-spi"; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 reg = <0 0x11013000 0 0x1000>; 1308 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1309 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1310 <&topckgen CLK_TOP_MUX_SPI>, 1311 <&infracfg CLK_INFRA_SPI3>; 1312 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1313 status = "disabled"; 1314 }; 1315 1316 i2c9: i2c@11014000 { 1317 compatible = "mediatek,mt8183-i2c"; 1318 reg = <0 0x11014000 0 0x1000>, 1319 <0 0x11000180 0 0x80>; 1320 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1321 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1322 <&infracfg CLK_INFRA_AP_DMA>, 1323 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1324 clock-names = "main", "dma", "arb"; 1325 clock-div = <1>; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 i2c10: i2c@11015000 { 1332 compatible = "mediatek,mt8183-i2c"; 1333 reg = <0 0x11015000 0 0x1000>, 1334 <0 0x11000300 0 0x80>; 1335 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1336 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1337 <&infracfg CLK_INFRA_AP_DMA>, 1338 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1339 clock-names = "main", "dma", "arb"; 1340 clock-div = <1>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 i2c5: i2c@11016000 { 1347 compatible = "mediatek,mt8183-i2c"; 1348 reg = <0 0x11016000 0 0x1000>, 1349 <0 0x11000500 0 0x80>; 1350 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1351 clocks = <&infracfg CLK_INFRA_I2C5>, 1352 <&infracfg CLK_INFRA_AP_DMA>, 1353 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1354 clock-names = "main", "dma", "arb"; 1355 clock-div = <1>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 i2c11: i2c@11017000 { 1362 compatible = "mediatek,mt8183-i2c"; 1363 reg = <0 0x11017000 0 0x1000>, 1364 <0 0x11000580 0 0x80>; 1365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1366 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1367 <&infracfg CLK_INFRA_AP_DMA>, 1368 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1369 clock-names = "main", "dma", "arb"; 1370 clock-div = <1>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 spi4: spi@11018000 { 1377 compatible = "mediatek,mt8183-spi"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 reg = <0 0x11018000 0 0x1000>; 1381 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1382 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1383 <&topckgen CLK_TOP_MUX_SPI>, 1384 <&infracfg CLK_INFRA_SPI4>; 1385 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1386 status = "disabled"; 1387 }; 1388 1389 spi5: spi@11019000 { 1390 compatible = "mediatek,mt8183-spi"; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 reg = <0 0x11019000 0 0x1000>; 1394 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1395 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1396 <&topckgen CLK_TOP_MUX_SPI>, 1397 <&infracfg CLK_INFRA_SPI5>; 1398 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1399 status = "disabled"; 1400 }; 1401 1402 i2c7: i2c@1101a000 { 1403 compatible = "mediatek,mt8183-i2c"; 1404 reg = <0 0x1101a000 0 0x1000>, 1405 <0 0x11000680 0 0x80>; 1406 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1407 clocks = <&infracfg CLK_INFRA_I2C7>, 1408 <&infracfg CLK_INFRA_AP_DMA>; 1409 clock-names = "main", "dma"; 1410 clock-div = <1>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 status = "disabled"; 1414 }; 1415 1416 i2c8: i2c@1101b000 { 1417 compatible = "mediatek,mt8183-i2c"; 1418 reg = <0 0x1101b000 0 0x1000>, 1419 <0 0x11000700 0 0x80>; 1420 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1421 clocks = <&infracfg CLK_INFRA_I2C8>, 1422 <&infracfg CLK_INFRA_AP_DMA>; 1423 clock-names = "main", "dma"; 1424 clock-div = <1>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 1430 ssusb: usb@11201000 { 1431 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 1432 reg = <0 0x11201000 0 0x2e00>, 1433 <0 0x11203e00 0 0x0100>; 1434 reg-names = "mac", "ippc"; 1435 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1436 phys = <&u2port0 PHY_TYPE_USB2>, 1437 <&u3port0 PHY_TYPE_USB3>; 1438 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1439 <&infracfg CLK_INFRA_USB>; 1440 clock-names = "sys_ck", "ref_ck"; 1441 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1442 #address-cells = <2>; 1443 #size-cells = <2>; 1444 ranges; 1445 status = "disabled"; 1446 1447 usb_host: usb@11200000 { 1448 compatible = "mediatek,mt8183-xhci", 1449 "mediatek,mtk-xhci"; 1450 reg = <0 0x11200000 0 0x1000>; 1451 reg-names = "mac"; 1452 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1453 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1454 <&infracfg CLK_INFRA_USB>; 1455 clock-names = "sys_ck", "ref_ck"; 1456 status = "disabled"; 1457 }; 1458 }; 1459 1460 audiosys: audio-controller@11220000 { 1461 compatible = "mediatek,mt8183-audiosys", "syscon"; 1462 reg = <0 0x11220000 0 0x1000>; 1463 #clock-cells = <1>; 1464 afe: mt8183-afe-pcm { 1465 compatible = "mediatek,mt8183-audio"; 1466 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1467 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1468 reset-names = "audiosys"; 1469 power-domains = 1470 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1471 clocks = <&audiosys CLK_AUDIO_AFE>, 1472 <&audiosys CLK_AUDIO_DAC>, 1473 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1474 <&audiosys CLK_AUDIO_ADC>, 1475 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1476 <&audiosys CLK_AUDIO_22M>, 1477 <&audiosys CLK_AUDIO_24M>, 1478 <&audiosys CLK_AUDIO_APLL_TUNER>, 1479 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1480 <&audiosys CLK_AUDIO_I2S1>, 1481 <&audiosys CLK_AUDIO_I2S2>, 1482 <&audiosys CLK_AUDIO_I2S3>, 1483 <&audiosys CLK_AUDIO_I2S4>, 1484 <&audiosys CLK_AUDIO_TDM>, 1485 <&audiosys CLK_AUDIO_TML>, 1486 <&infracfg CLK_INFRA_AUDIO>, 1487 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1488 <&topckgen CLK_TOP_MUX_AUDIO>, 1489 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1490 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1491 <&topckgen CLK_TOP_MUX_AUD_1>, 1492 <&topckgen CLK_TOP_APLL1_CK>, 1493 <&topckgen CLK_TOP_MUX_AUD_2>, 1494 <&topckgen CLK_TOP_APLL2_CK>, 1495 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1496 <&topckgen CLK_TOP_APLL1_D8>, 1497 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1498 <&topckgen CLK_TOP_APLL2_D8>, 1499 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1500 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1501 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1502 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1503 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1504 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1505 <&topckgen CLK_TOP_APLL12_DIV0>, 1506 <&topckgen CLK_TOP_APLL12_DIV1>, 1507 <&topckgen CLK_TOP_APLL12_DIV2>, 1508 <&topckgen CLK_TOP_APLL12_DIV3>, 1509 <&topckgen CLK_TOP_APLL12_DIV4>, 1510 <&topckgen CLK_TOP_APLL12_DIVB>, 1511 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1512 <&clk26m>; 1513 clock-names = "aud_afe_clk", 1514 "aud_dac_clk", 1515 "aud_dac_predis_clk", 1516 "aud_adc_clk", 1517 "aud_adc_adda6_clk", 1518 "aud_apll22m_clk", 1519 "aud_apll24m_clk", 1520 "aud_apll1_tuner_clk", 1521 "aud_apll2_tuner_clk", 1522 "aud_i2s1_bclk_sw", 1523 "aud_i2s2_bclk_sw", 1524 "aud_i2s3_bclk_sw", 1525 "aud_i2s4_bclk_sw", 1526 "aud_tdm_clk", 1527 "aud_tml_clk", 1528 "aud_infra_clk", 1529 "mtkaif_26m_clk", 1530 "top_mux_audio", 1531 "top_mux_aud_intbus", 1532 "top_syspll_d2_d4", 1533 "top_mux_aud_1", 1534 "top_apll1_ck", 1535 "top_mux_aud_2", 1536 "top_apll2_ck", 1537 "top_mux_aud_eng1", 1538 "top_apll1_d8", 1539 "top_mux_aud_eng2", 1540 "top_apll2_d8", 1541 "top_i2s0_m_sel", 1542 "top_i2s1_m_sel", 1543 "top_i2s2_m_sel", 1544 "top_i2s3_m_sel", 1545 "top_i2s4_m_sel", 1546 "top_i2s5_m_sel", 1547 "top_apll12_div0", 1548 "top_apll12_div1", 1549 "top_apll12_div2", 1550 "top_apll12_div3", 1551 "top_apll12_div4", 1552 "top_apll12_divb", 1553 /*"top_apll12_div5",*/ 1554 "top_clk26m_clk"; 1555 }; 1556 }; 1557 1558 mmc0: mmc@11230000 { 1559 compatible = "mediatek,mt8183-mmc"; 1560 reg = <0 0x11230000 0 0x1000>, 1561 <0 0x11f50000 0 0x1000>; 1562 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1563 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1564 <&infracfg CLK_INFRA_MSDC0>, 1565 <&infracfg CLK_INFRA_MSDC0_SCK>; 1566 clock-names = "source", "hclk", "source_cg"; 1567 status = "disabled"; 1568 }; 1569 1570 mmc1: mmc@11240000 { 1571 compatible = "mediatek,mt8183-mmc"; 1572 reg = <0 0x11240000 0 0x1000>, 1573 <0 0x11e10000 0 0x1000>; 1574 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1575 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1576 <&infracfg CLK_INFRA_MSDC1>, 1577 <&infracfg CLK_INFRA_MSDC1_SCK>; 1578 clock-names = "source", "hclk", "source_cg"; 1579 status = "disabled"; 1580 }; 1581 1582 mipi_tx0: dsi-phy@11e50000 { 1583 compatible = "mediatek,mt8183-mipi-tx"; 1584 reg = <0 0x11e50000 0 0x1000>; 1585 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1586 #clock-cells = <0>; 1587 #phy-cells = <0>; 1588 clock-output-names = "mipi_tx0_pll"; 1589 nvmem-cells = <&mipi_tx_calibration>; 1590 nvmem-cell-names = "calibration-data"; 1591 }; 1592 1593 efuse: efuse@11f10000 { 1594 compatible = "mediatek,mt8183-efuse", 1595 "mediatek,efuse"; 1596 reg = <0 0x11f10000 0 0x1000>; 1597 #address-cells = <1>; 1598 #size-cells = <1>; 1599 thermal_calibration: calib@180 { 1600 reg = <0x180 0xc>; 1601 }; 1602 1603 mipi_tx_calibration: calib@190 { 1604 reg = <0x190 0xc>; 1605 }; 1606 }; 1607 1608 u3phy: t-phy@11f40000 { 1609 compatible = "mediatek,mt8183-tphy", 1610 "mediatek,generic-tphy-v2"; 1611 #address-cells = <1>; 1612 #size-cells = <1>; 1613 ranges = <0 0 0x11f40000 0x1000>; 1614 status = "okay"; 1615 1616 u2port0: usb-phy@0 { 1617 reg = <0x0 0x700>; 1618 clocks = <&clk26m>; 1619 clock-names = "ref"; 1620 #phy-cells = <1>; 1621 mediatek,discth = <15>; 1622 status = "okay"; 1623 }; 1624 1625 u3port0: usb-phy@700 { 1626 reg = <0x0700 0x900>; 1627 clocks = <&clk26m>; 1628 clock-names = "ref"; 1629 #phy-cells = <1>; 1630 status = "okay"; 1631 }; 1632 }; 1633 1634 mfgcfg: syscon@13000000 { 1635 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1636 reg = <0 0x13000000 0 0x1000>; 1637 #clock-cells = <1>; 1638 }; 1639 1640 gpu: gpu@13040000 { 1641 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; 1642 reg = <0 0x13040000 0 0x4000>; 1643 interrupts = 1644 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1645 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1646 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1647 interrupt-names = "job", "mmu", "gpu"; 1648 1649 clocks = <&topckgen CLK_TOP_MFGPLL_CK>; 1650 1651 power-domains = 1652 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1653 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1654 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1655 power-domain-names = "core0", "core1", "core2"; 1656 1657 operating-points-v2 = <&gpu_opp_table>; 1658 }; 1659 1660 mmsys: syscon@14000000 { 1661 compatible = "mediatek,mt8183-mmsys", "syscon"; 1662 reg = <0 0x14000000 0 0x1000>; 1663 #clock-cells = <1>; 1664 #reset-cells = <1>; 1665 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1666 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1667 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1668 }; 1669 1670 ovl0: ovl@14008000 { 1671 compatible = "mediatek,mt8183-disp-ovl"; 1672 reg = <0 0x14008000 0 0x1000>; 1673 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1674 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1675 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1676 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1677 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1678 }; 1679 1680 ovl_2l0: ovl@14009000 { 1681 compatible = "mediatek,mt8183-disp-ovl-2l"; 1682 reg = <0 0x14009000 0 0x1000>; 1683 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1684 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1685 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1686 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1687 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1688 }; 1689 1690 ovl_2l1: ovl@1400a000 { 1691 compatible = "mediatek,mt8183-disp-ovl-2l"; 1692 reg = <0 0x1400a000 0 0x1000>; 1693 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1694 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1695 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1696 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1697 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1698 }; 1699 1700 rdma0: rdma@1400b000 { 1701 compatible = "mediatek,mt8183-disp-rdma"; 1702 reg = <0 0x1400b000 0 0x1000>; 1703 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1704 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1705 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1706 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1707 mediatek,rdma-fifo-size = <5120>; 1708 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1709 }; 1710 1711 rdma1: rdma@1400c000 { 1712 compatible = "mediatek,mt8183-disp-rdma"; 1713 reg = <0 0x1400c000 0 0x1000>; 1714 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1715 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1716 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1717 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1718 mediatek,rdma-fifo-size = <2048>; 1719 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1720 }; 1721 1722 color0: color@1400e000 { 1723 compatible = "mediatek,mt8183-disp-color", 1724 "mediatek,mt8173-disp-color"; 1725 reg = <0 0x1400e000 0 0x1000>; 1726 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1727 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1728 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1730 }; 1731 1732 ccorr0: ccorr@1400f000 { 1733 compatible = "mediatek,mt8183-disp-ccorr"; 1734 reg = <0 0x1400f000 0 0x1000>; 1735 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1736 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1737 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1738 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1739 }; 1740 1741 aal0: aal@14010000 { 1742 compatible = "mediatek,mt8183-disp-aal"; 1743 reg = <0 0x14010000 0 0x1000>; 1744 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1745 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1746 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1747 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1748 }; 1749 1750 gamma0: gamma@14011000 { 1751 compatible = "mediatek,mt8183-disp-gamma"; 1752 reg = <0 0x14011000 0 0x1000>; 1753 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1754 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1755 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1756 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1757 }; 1758 1759 dither0: dither@14012000 { 1760 compatible = "mediatek,mt8183-disp-dither"; 1761 reg = <0 0x14012000 0 0x1000>; 1762 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1763 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1764 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1765 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1766 }; 1767 1768 dsi0: dsi@14014000 { 1769 compatible = "mediatek,mt8183-dsi"; 1770 reg = <0 0x14014000 0 0x1000>; 1771 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1772 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1773 clocks = <&mmsys CLK_MM_DSI0_MM>, 1774 <&mmsys CLK_MM_DSI0_IF>, 1775 <&mipi_tx0>; 1776 clock-names = "engine", "digital", "hs"; 1777 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 1778 phys = <&mipi_tx0>; 1779 phy-names = "dphy"; 1780 }; 1781 1782 mutex: mutex@14016000 { 1783 compatible = "mediatek,mt8183-disp-mutex"; 1784 reg = <0 0x14016000 0 0x1000>; 1785 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1786 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1787 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1788 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1789 }; 1790 1791 larb0: larb@14017000 { 1792 compatible = "mediatek,mt8183-smi-larb"; 1793 reg = <0 0x14017000 0 0x1000>; 1794 mediatek,smi = <&smi_common>; 1795 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1796 <&mmsys CLK_MM_SMI_LARB0>; 1797 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1798 clock-names = "apb", "smi"; 1799 }; 1800 1801 smi_common: smi@14019000 { 1802 compatible = "mediatek,mt8183-smi-common"; 1803 reg = <0 0x14019000 0 0x1000>; 1804 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1805 <&mmsys CLK_MM_SMI_COMMON>, 1806 <&mmsys CLK_MM_GALS_COMM0>, 1807 <&mmsys CLK_MM_GALS_COMM1>; 1808 clock-names = "apb", "smi", "gals0", "gals1"; 1809 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1810 }; 1811 1812 imgsys: syscon@15020000 { 1813 compatible = "mediatek,mt8183-imgsys", "syscon"; 1814 reg = <0 0x15020000 0 0x1000>; 1815 #clock-cells = <1>; 1816 }; 1817 1818 larb5: larb@15021000 { 1819 compatible = "mediatek,mt8183-smi-larb"; 1820 reg = <0 0x15021000 0 0x1000>; 1821 mediatek,smi = <&smi_common>; 1822 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1823 <&mmsys CLK_MM_GALS_IMG2MM>; 1824 clock-names = "apb", "smi", "gals"; 1825 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1826 }; 1827 1828 larb2: larb@1502f000 { 1829 compatible = "mediatek,mt8183-smi-larb"; 1830 reg = <0 0x1502f000 0 0x1000>; 1831 mediatek,smi = <&smi_common>; 1832 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1833 <&mmsys CLK_MM_GALS_IPU2MM>; 1834 clock-names = "apb", "smi", "gals"; 1835 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1836 }; 1837 1838 vdecsys: syscon@16000000 { 1839 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1840 reg = <0 0x16000000 0 0x1000>; 1841 #clock-cells = <1>; 1842 }; 1843 1844 larb1: larb@16010000 { 1845 compatible = "mediatek,mt8183-smi-larb"; 1846 reg = <0 0x16010000 0 0x1000>; 1847 mediatek,smi = <&smi_common>; 1848 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1849 clock-names = "apb", "smi"; 1850 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1851 }; 1852 1853 vencsys: syscon@17000000 { 1854 compatible = "mediatek,mt8183-vencsys", "syscon"; 1855 reg = <0 0x17000000 0 0x1000>; 1856 #clock-cells = <1>; 1857 }; 1858 1859 larb4: larb@17010000 { 1860 compatible = "mediatek,mt8183-smi-larb"; 1861 reg = <0 0x17010000 0 0x1000>; 1862 mediatek,smi = <&smi_common>; 1863 clocks = <&vencsys CLK_VENC_LARB>, 1864 <&vencsys CLK_VENC_LARB>; 1865 clock-names = "apb", "smi"; 1866 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1867 }; 1868 1869 venc_jpg: venc_jpg@17030000 { 1870 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 1871 reg = <0 0x17030000 0 0x1000>; 1872 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 1873 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 1874 <&iommu M4U_PORT_JPGENC_BSDMA>; 1875 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1876 clocks = <&vencsys CLK_VENC_JPGENC>; 1877 clock-names = "jpgenc"; 1878 }; 1879 1880 ipu_conn: syscon@19000000 { 1881 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1882 reg = <0 0x19000000 0 0x1000>; 1883 #clock-cells = <1>; 1884 }; 1885 1886 ipu_adl: syscon@19010000 { 1887 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1888 reg = <0 0x19010000 0 0x1000>; 1889 #clock-cells = <1>; 1890 }; 1891 1892 ipu_core0: syscon@19180000 { 1893 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1894 reg = <0 0x19180000 0 0x1000>; 1895 #clock-cells = <1>; 1896 }; 1897 1898 ipu_core1: syscon@19280000 { 1899 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1900 reg = <0 0x19280000 0 0x1000>; 1901 #clock-cells = <1>; 1902 }; 1903 1904 camsys: syscon@1a000000 { 1905 compatible = "mediatek,mt8183-camsys", "syscon"; 1906 reg = <0 0x1a000000 0 0x1000>; 1907 #clock-cells = <1>; 1908 }; 1909 1910 larb6: larb@1a001000 { 1911 compatible = "mediatek,mt8183-smi-larb"; 1912 reg = <0 0x1a001000 0 0x1000>; 1913 mediatek,smi = <&smi_common>; 1914 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1915 <&mmsys CLK_MM_GALS_CAM2MM>; 1916 clock-names = "apb", "smi", "gals"; 1917 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1918 }; 1919 1920 larb3: larb@1a002000 { 1921 compatible = "mediatek,mt8183-smi-larb"; 1922 reg = <0 0x1a002000 0 0x1000>; 1923 mediatek,smi = <&smi_common>; 1924 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1925 <&mmsys CLK_MM_GALS_IPU12MM>; 1926 clock-names = "apb", "smi", "gals"; 1927 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1928 }; 1929 }; 1930}; 1931