1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x000>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <741>; 87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 88 dynamic-power-coefficient = <84>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu1: cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x001>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <741>; 98 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 99 dynamic-power-coefficient = <84>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x002>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <741>; 109 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 110 dynamic-power-coefficient = <84>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu3: cpu@3 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x003>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <741>; 120 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 121 dynamic-power-coefficient = <84>; 122 #cooling-cells = <2>; 123 }; 124 125 cpu4: cpu@100 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a73"; 128 reg = <0x100>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 132 dynamic-power-coefficient = <211>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu5: cpu@101 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a73"; 139 reg = <0x101>; 140 enable-method = "psci"; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 143 dynamic-power-coefficient = <211>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@102 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a73"; 150 reg = <0x102>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <1024>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 154 dynamic-power-coefficient = <211>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu7: cpu@103 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a73"; 161 reg = <0x103>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 165 dynamic-power-coefficient = <211>; 166 #cooling-cells = <2>; 167 }; 168 169 idle-states { 170 entry-method = "psci"; 171 172 CPU_SLEEP: cpu-sleep { 173 compatible = "arm,idle-state"; 174 local-timer-stop; 175 arm,psci-suspend-param = <0x00010001>; 176 entry-latency-us = <200>; 177 exit-latency-us = <200>; 178 min-residency-us = <800>; 179 }; 180 181 CLUSTER_SLEEP0: cluster-sleep-0 { 182 compatible = "arm,idle-state"; 183 local-timer-stop; 184 arm,psci-suspend-param = <0x01010001>; 185 entry-latency-us = <250>; 186 exit-latency-us = <400>; 187 min-residency-us = <1000>; 188 }; 189 CLUSTER_SLEEP1: cluster-sleep-1 { 190 compatible = "arm,idle-state"; 191 local-timer-stop; 192 arm,psci-suspend-param = <0x01010001>; 193 entry-latency-us = <250>; 194 exit-latency-us = <400>; 195 min-residency-us = <1300>; 196 }; 197 }; 198 }; 199 200 gpu_opp_table: opp_table0 { 201 compatible = "operating-points-v2"; 202 opp-shared; 203 204 opp-300000000 { 205 opp-hz = /bits/ 64 <300000000>; 206 opp-microvolt = <625000>, <850000>; 207 }; 208 209 opp-320000000 { 210 opp-hz = /bits/ 64 <320000000>; 211 opp-microvolt = <631250>, <850000>; 212 }; 213 214 opp-340000000 { 215 opp-hz = /bits/ 64 <340000000>; 216 opp-microvolt = <637500>, <850000>; 217 }; 218 219 opp-360000000 { 220 opp-hz = /bits/ 64 <360000000>; 221 opp-microvolt = <643750>, <850000>; 222 }; 223 224 opp-380000000 { 225 opp-hz = /bits/ 64 <380000000>; 226 opp-microvolt = <650000>, <850000>; 227 }; 228 229 opp-400000000 { 230 opp-hz = /bits/ 64 <400000000>; 231 opp-microvolt = <656250>, <850000>; 232 }; 233 234 opp-420000000 { 235 opp-hz = /bits/ 64 <420000000>; 236 opp-microvolt = <662500>, <850000>; 237 }; 238 239 opp-460000000 { 240 opp-hz = /bits/ 64 <460000000>; 241 opp-microvolt = <675000>, <850000>; 242 }; 243 244 opp-500000000 { 245 opp-hz = /bits/ 64 <500000000>; 246 opp-microvolt = <687500>, <850000>; 247 }; 248 249 opp-540000000 { 250 opp-hz = /bits/ 64 <540000000>; 251 opp-microvolt = <700000>, <850000>; 252 }; 253 254 opp-580000000 { 255 opp-hz = /bits/ 64 <580000000>; 256 opp-microvolt = <712500>, <850000>; 257 }; 258 259 opp-620000000 { 260 opp-hz = /bits/ 64 <620000000>; 261 opp-microvolt = <725000>, <850000>; 262 }; 263 264 opp-653000000 { 265 opp-hz = /bits/ 64 <653000000>; 266 opp-microvolt = <743750>, <850000>; 267 }; 268 269 opp-698000000 { 270 opp-hz = /bits/ 64 <698000000>; 271 opp-microvolt = <768750>, <868750>; 272 }; 273 274 opp-743000000 { 275 opp-hz = /bits/ 64 <743000000>; 276 opp-microvolt = <793750>, <893750>; 277 }; 278 279 opp-800000000 { 280 opp-hz = /bits/ 64 <800000000>; 281 opp-microvolt = <825000>, <925000>; 282 }; 283 }; 284 285 pmu-a53 { 286 compatible = "arm,cortex-a53-pmu"; 287 interrupt-parent = <&gic>; 288 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 289 }; 290 291 pmu-a73 { 292 compatible = "arm,cortex-a73-pmu"; 293 interrupt-parent = <&gic>; 294 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 295 }; 296 297 psci { 298 compatible = "arm,psci-1.0"; 299 method = "smc"; 300 }; 301 302 clk26m: oscillator { 303 compatible = "fixed-clock"; 304 #clock-cells = <0>; 305 clock-frequency = <26000000>; 306 clock-output-names = "clk26m"; 307 }; 308 309 timer { 310 compatible = "arm,armv8-timer"; 311 interrupt-parent = <&gic>; 312 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 313 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 314 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 315 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 316 }; 317 318 soc { 319 #address-cells = <2>; 320 #size-cells = <2>; 321 compatible = "simple-bus"; 322 ranges; 323 324 soc_data: soc_data@8000000 { 325 compatible = "mediatek,mt8183-efuse", 326 "mediatek,efuse"; 327 reg = <0 0x08000000 0 0x0010>; 328 #address-cells = <1>; 329 #size-cells = <1>; 330 status = "disabled"; 331 }; 332 333 gic: interrupt-controller@c000000 { 334 compatible = "arm,gic-v3"; 335 #interrupt-cells = <4>; 336 interrupt-parent = <&gic>; 337 interrupt-controller; 338 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 339 <0 0x0c100000 0 0x200000>, /* GICR */ 340 <0 0x0c400000 0 0x2000>, /* GICC */ 341 <0 0x0c410000 0 0x1000>, /* GICH */ 342 <0 0x0c420000 0 0x2000>; /* GICV */ 343 344 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 345 ppi-partitions { 346 ppi_cluster0: interrupt-partition-0 { 347 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 348 }; 349 ppi_cluster1: interrupt-partition-1 { 350 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 351 }; 352 }; 353 }; 354 355 mcucfg: syscon@c530000 { 356 compatible = "mediatek,mt8183-mcucfg", "syscon"; 357 reg = <0 0x0c530000 0 0x1000>; 358 #clock-cells = <1>; 359 }; 360 361 sysirq: interrupt-controller@c530a80 { 362 compatible = "mediatek,mt8183-sysirq", 363 "mediatek,mt6577-sysirq"; 364 interrupt-controller; 365 #interrupt-cells = <3>; 366 interrupt-parent = <&gic>; 367 reg = <0 0x0c530a80 0 0x50>; 368 }; 369 370 topckgen: syscon@10000000 { 371 compatible = "mediatek,mt8183-topckgen", "syscon"; 372 reg = <0 0x10000000 0 0x1000>; 373 #clock-cells = <1>; 374 }; 375 376 infracfg: syscon@10001000 { 377 compatible = "mediatek,mt8183-infracfg", "syscon"; 378 reg = <0 0x10001000 0 0x1000>; 379 #clock-cells = <1>; 380 #reset-cells = <1>; 381 }; 382 383 pericfg: syscon@10003000 { 384 compatible = "mediatek,mt8183-pericfg", "syscon"; 385 reg = <0 0x10003000 0 0x1000>; 386 #clock-cells = <1>; 387 }; 388 389 pio: pinctrl@10005000 { 390 compatible = "mediatek,mt8183-pinctrl"; 391 reg = <0 0x10005000 0 0x1000>, 392 <0 0x11f20000 0 0x1000>, 393 <0 0x11e80000 0 0x1000>, 394 <0 0x11e70000 0 0x1000>, 395 <0 0x11e90000 0 0x1000>, 396 <0 0x11d30000 0 0x1000>, 397 <0 0x11d20000 0 0x1000>, 398 <0 0x11c50000 0 0x1000>, 399 <0 0x11f30000 0 0x1000>, 400 <0 0x1000b000 0 0x1000>; 401 reg-names = "iocfg0", "iocfg1", "iocfg2", 402 "iocfg3", "iocfg4", "iocfg5", 403 "iocfg6", "iocfg7", "iocfg8", 404 "eint"; 405 gpio-controller; 406 #gpio-cells = <2>; 407 gpio-ranges = <&pio 0 0 192>; 408 interrupt-controller; 409 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 410 #interrupt-cells = <2>; 411 }; 412 413 scpsys: syscon@10006000 { 414 compatible = "syscon", "simple-mfd"; 415 reg = <0 0x10006000 0 0x1000>; 416 #power-domain-cells = <1>; 417 418 /* System Power Manager */ 419 spm: power-controller { 420 compatible = "mediatek,mt8183-power-controller"; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 #power-domain-cells = <1>; 424 425 /* power domain of the SoC */ 426 power-domain@MT8183_POWER_DOMAIN_AUDIO { 427 reg = <MT8183_POWER_DOMAIN_AUDIO>; 428 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 429 <&infracfg CLK_INFRA_AUDIO>, 430 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 431 clock-names = "audio", "audio1", "audio2"; 432 #power-domain-cells = <0>; 433 }; 434 435 power-domain@MT8183_POWER_DOMAIN_CONN { 436 reg = <MT8183_POWER_DOMAIN_CONN>; 437 mediatek,infracfg = <&infracfg>; 438 #power-domain-cells = <0>; 439 }; 440 441 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 442 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 443 clocks = <&topckgen CLK_TOP_MUX_MFG>; 444 clock-names = "mfg"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 #power-domain-cells = <1>; 448 449 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 450 reg = <MT8183_POWER_DOMAIN_MFG>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 #power-domain-cells = <1>; 454 455 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 456 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 457 #power-domain-cells = <0>; 458 }; 459 460 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 461 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 462 #power-domain-cells = <0>; 463 }; 464 465 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 466 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 467 mediatek,infracfg = <&infracfg>; 468 #power-domain-cells = <0>; 469 }; 470 }; 471 }; 472 473 power-domain@MT8183_POWER_DOMAIN_DISP { 474 reg = <MT8183_POWER_DOMAIN_DISP>; 475 clocks = <&topckgen CLK_TOP_MUX_MM>, 476 <&mmsys CLK_MM_SMI_COMMON>, 477 <&mmsys CLK_MM_SMI_LARB0>, 478 <&mmsys CLK_MM_SMI_LARB1>, 479 <&mmsys CLK_MM_GALS_COMM0>, 480 <&mmsys CLK_MM_GALS_COMM1>, 481 <&mmsys CLK_MM_GALS_CCU2MM>, 482 <&mmsys CLK_MM_GALS_IPU12MM>, 483 <&mmsys CLK_MM_GALS_IMG2MM>, 484 <&mmsys CLK_MM_GALS_CAM2MM>, 485 <&mmsys CLK_MM_GALS_IPU2MM>; 486 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 487 "mm-4", "mm-5", "mm-6", "mm-7", 488 "mm-8", "mm-9"; 489 mediatek,infracfg = <&infracfg>; 490 mediatek,smi = <&smi_common>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 #power-domain-cells = <1>; 494 495 power-domain@MT8183_POWER_DOMAIN_CAM { 496 reg = <MT8183_POWER_DOMAIN_CAM>; 497 clocks = <&topckgen CLK_TOP_MUX_CAM>, 498 <&camsys CLK_CAM_LARB6>, 499 <&camsys CLK_CAM_LARB3>, 500 <&camsys CLK_CAM_SENINF>, 501 <&camsys CLK_CAM_CAMSV0>, 502 <&camsys CLK_CAM_CAMSV1>, 503 <&camsys CLK_CAM_CAMSV2>, 504 <&camsys CLK_CAM_CCU>; 505 clock-names = "cam", "cam-0", "cam-1", 506 "cam-2", "cam-3", "cam-4", 507 "cam-5", "cam-6"; 508 mediatek,infracfg = <&infracfg>; 509 mediatek,smi = <&smi_common>; 510 #power-domain-cells = <0>; 511 }; 512 513 power-domain@MT8183_POWER_DOMAIN_ISP { 514 reg = <MT8183_POWER_DOMAIN_ISP>; 515 clocks = <&topckgen CLK_TOP_MUX_IMG>, 516 <&imgsys CLK_IMG_LARB5>, 517 <&imgsys CLK_IMG_LARB2>; 518 clock-names = "isp", "isp-0", "isp-1"; 519 mediatek,infracfg = <&infracfg>; 520 mediatek,smi = <&smi_common>; 521 #power-domain-cells = <0>; 522 }; 523 524 power-domain@MT8183_POWER_DOMAIN_VDEC { 525 reg = <MT8183_POWER_DOMAIN_VDEC>; 526 mediatek,smi = <&smi_common>; 527 #power-domain-cells = <0>; 528 }; 529 530 power-domain@MT8183_POWER_DOMAIN_VENC { 531 reg = <MT8183_POWER_DOMAIN_VENC>; 532 mediatek,smi = <&smi_common>; 533 #power-domain-cells = <0>; 534 }; 535 536 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 537 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 538 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 539 <&topckgen CLK_TOP_MUX_DSP>, 540 <&ipu_conn CLK_IPU_CONN_IPU>, 541 <&ipu_conn CLK_IPU_CONN_AHB>, 542 <&ipu_conn CLK_IPU_CONN_AXI>, 543 <&ipu_conn CLK_IPU_CONN_ISP>, 544 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 545 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 546 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 547 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 548 mediatek,infracfg = <&infracfg>; 549 mediatek,smi = <&smi_common>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 #power-domain-cells = <1>; 553 554 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 555 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 556 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 557 clock-names = "vpu2"; 558 mediatek,infracfg = <&infracfg>; 559 #power-domain-cells = <0>; 560 }; 561 562 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 563 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 564 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 565 clock-names = "vpu3"; 566 mediatek,infracfg = <&infracfg>; 567 #power-domain-cells = <0>; 568 }; 569 }; 570 }; 571 }; 572 }; 573 574 watchdog: watchdog@10007000 { 575 compatible = "mediatek,mt8183-wdt"; 576 reg = <0 0x10007000 0 0x100>; 577 #reset-cells = <1>; 578 }; 579 580 apmixedsys: syscon@1000c000 { 581 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 582 reg = <0 0x1000c000 0 0x1000>; 583 #clock-cells = <1>; 584 }; 585 586 pwrap: pwrap@1000d000 { 587 compatible = "mediatek,mt8183-pwrap"; 588 reg = <0 0x1000d000 0 0x1000>; 589 reg-names = "pwrap"; 590 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 592 <&infracfg CLK_INFRA_PMIC_AP>; 593 clock-names = "spi", "wrap"; 594 }; 595 596 scp: scp@10500000 { 597 compatible = "mediatek,mt8183-scp"; 598 reg = <0 0x10500000 0 0x80000>, 599 <0 0x105c0000 0 0x19080>; 600 reg-names = "sram", "cfg"; 601 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&infracfg CLK_INFRA_SCPSYS>; 603 clock-names = "main"; 604 memory-region = <&scp_mem_reserved>; 605 status = "disabled"; 606 }; 607 608 systimer: timer@10017000 { 609 compatible = "mediatek,mt8183-timer", 610 "mediatek,mt6765-timer"; 611 reg = <0 0x10017000 0 0x1000>; 612 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&topckgen CLK_TOP_CLK13M>; 614 clock-names = "clk13m"; 615 }; 616 617 iommu: iommu@10205000 { 618 compatible = "mediatek,mt8183-m4u"; 619 reg = <0 0x10205000 0 0x1000>; 620 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 621 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 622 &larb4 &larb5 &larb6>; 623 #iommu-cells = <1>; 624 }; 625 626 gce: mailbox@10238000 { 627 compatible = "mediatek,mt8183-gce"; 628 reg = <0 0x10238000 0 0x4000>; 629 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 630 #mbox-cells = <2>; 631 clocks = <&infracfg CLK_INFRA_GCE>; 632 clock-names = "gce"; 633 }; 634 635 auxadc: auxadc@11001000 { 636 compatible = "mediatek,mt8183-auxadc", 637 "mediatek,mt8173-auxadc"; 638 reg = <0 0x11001000 0 0x1000>; 639 clocks = <&infracfg CLK_INFRA_AUXADC>; 640 clock-names = "main"; 641 #io-channel-cells = <1>; 642 status = "disabled"; 643 }; 644 645 uart0: serial@11002000 { 646 compatible = "mediatek,mt8183-uart", 647 "mediatek,mt6577-uart"; 648 reg = <0 0x11002000 0 0x1000>; 649 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 650 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 651 clock-names = "baud", "bus"; 652 status = "disabled"; 653 }; 654 655 uart1: serial@11003000 { 656 compatible = "mediatek,mt8183-uart", 657 "mediatek,mt6577-uart"; 658 reg = <0 0x11003000 0 0x1000>; 659 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 660 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 661 clock-names = "baud", "bus"; 662 status = "disabled"; 663 }; 664 665 uart2: serial@11004000 { 666 compatible = "mediatek,mt8183-uart", 667 "mediatek,mt6577-uart"; 668 reg = <0 0x11004000 0 0x1000>; 669 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 670 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 671 clock-names = "baud", "bus"; 672 status = "disabled"; 673 }; 674 675 i2c6: i2c@11005000 { 676 compatible = "mediatek,mt8183-i2c"; 677 reg = <0 0x11005000 0 0x1000>, 678 <0 0x11000600 0 0x80>; 679 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 680 clocks = <&infracfg CLK_INFRA_I2C6>, 681 <&infracfg CLK_INFRA_AP_DMA>; 682 clock-names = "main", "dma"; 683 clock-div = <1>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 i2c0: i2c@11007000 { 690 compatible = "mediatek,mt8183-i2c"; 691 reg = <0 0x11007000 0 0x1000>, 692 <0 0x11000080 0 0x80>; 693 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 694 clocks = <&infracfg CLK_INFRA_I2C0>, 695 <&infracfg CLK_INFRA_AP_DMA>; 696 clock-names = "main", "dma"; 697 clock-div = <1>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 i2c4: i2c@11008000 { 704 compatible = "mediatek,mt8183-i2c"; 705 reg = <0 0x11008000 0 0x1000>, 706 <0 0x11000100 0 0x80>; 707 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 708 clocks = <&infracfg CLK_INFRA_I2C1>, 709 <&infracfg CLK_INFRA_AP_DMA>, 710 <&infracfg CLK_INFRA_I2C1_ARBITER>; 711 clock-names = "main", "dma","arb"; 712 clock-div = <1>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 status = "disabled"; 716 }; 717 718 i2c2: i2c@11009000 { 719 compatible = "mediatek,mt8183-i2c"; 720 reg = <0 0x11009000 0 0x1000>, 721 <0 0x11000280 0 0x80>; 722 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 723 clocks = <&infracfg CLK_INFRA_I2C2>, 724 <&infracfg CLK_INFRA_AP_DMA>, 725 <&infracfg CLK_INFRA_I2C2_ARBITER>; 726 clock-names = "main", "dma", "arb"; 727 clock-div = <1>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 status = "disabled"; 731 }; 732 733 spi0: spi@1100a000 { 734 compatible = "mediatek,mt8183-spi"; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 reg = <0 0x1100a000 0 0x1000>; 738 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 739 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 740 <&topckgen CLK_TOP_MUX_SPI>, 741 <&infracfg CLK_INFRA_SPI0>; 742 clock-names = "parent-clk", "sel-clk", "spi-clk"; 743 status = "disabled"; 744 }; 745 746 thermal: thermal@1100b000 { 747 #thermal-sensor-cells = <1>; 748 compatible = "mediatek,mt8183-thermal"; 749 reg = <0 0x1100b000 0 0x1000>; 750 clocks = <&infracfg CLK_INFRA_THERM>, 751 <&infracfg CLK_INFRA_AUXADC>; 752 clock-names = "therm", "auxadc"; 753 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 754 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 755 mediatek,auxadc = <&auxadc>; 756 mediatek,apmixedsys = <&apmixedsys>; 757 nvmem-cells = <&thermal_calibration>; 758 nvmem-cell-names = "calibration-data"; 759 }; 760 761 thermal_zones: thermal-zones { 762 cpu_thermal: cpu_thermal { 763 polling-delay-passive = <100>; 764 polling-delay = <500>; 765 thermal-sensors = <&thermal 0>; 766 sustainable-power = <5000>; 767 768 trips { 769 threshold: trip-point0 { 770 temperature = <68000>; 771 hysteresis = <2000>; 772 type = "passive"; 773 }; 774 775 target: trip-point1 { 776 temperature = <80000>; 777 hysteresis = <2000>; 778 type = "passive"; 779 }; 780 781 cpu_crit: cpu-crit { 782 temperature = <115000>; 783 hysteresis = <2000>; 784 type = "critical"; 785 }; 786 }; 787 788 cooling-maps { 789 map0 { 790 trip = <&target>; 791 cooling-device = <&cpu0 792 THERMAL_NO_LIMIT 793 THERMAL_NO_LIMIT>, 794 <&cpu1 795 THERMAL_NO_LIMIT 796 THERMAL_NO_LIMIT>, 797 <&cpu2 798 THERMAL_NO_LIMIT 799 THERMAL_NO_LIMIT>, 800 <&cpu3 801 THERMAL_NO_LIMIT 802 THERMAL_NO_LIMIT>; 803 contribution = <3072>; 804 }; 805 map1 { 806 trip = <&target>; 807 cooling-device = <&cpu4 808 THERMAL_NO_LIMIT 809 THERMAL_NO_LIMIT>, 810 <&cpu5 811 THERMAL_NO_LIMIT 812 THERMAL_NO_LIMIT>, 813 <&cpu6 814 THERMAL_NO_LIMIT 815 THERMAL_NO_LIMIT>, 816 <&cpu7 817 THERMAL_NO_LIMIT 818 THERMAL_NO_LIMIT>; 819 contribution = <1024>; 820 }; 821 }; 822 }; 823 824 /* The tzts1 ~ tzts6 don't need to polling */ 825 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 826 827 tzts1: tzts1 { 828 polling-delay-passive = <0>; 829 polling-delay = <0>; 830 thermal-sensors = <&thermal 1>; 831 sustainable-power = <5000>; 832 trips {}; 833 cooling-maps {}; 834 }; 835 836 tzts2: tzts2 { 837 polling-delay-passive = <0>; 838 polling-delay = <0>; 839 thermal-sensors = <&thermal 2>; 840 sustainable-power = <5000>; 841 trips {}; 842 cooling-maps {}; 843 }; 844 845 tzts3: tzts3 { 846 polling-delay-passive = <0>; 847 polling-delay = <0>; 848 thermal-sensors = <&thermal 3>; 849 sustainable-power = <5000>; 850 trips {}; 851 cooling-maps {}; 852 }; 853 854 tzts4: tzts4 { 855 polling-delay-passive = <0>; 856 polling-delay = <0>; 857 thermal-sensors = <&thermal 4>; 858 sustainable-power = <5000>; 859 trips {}; 860 cooling-maps {}; 861 }; 862 863 tzts5: tzts5 { 864 polling-delay-passive = <0>; 865 polling-delay = <0>; 866 thermal-sensors = <&thermal 5>; 867 sustainable-power = <5000>; 868 trips {}; 869 cooling-maps {}; 870 }; 871 872 tztsABB: tztsABB { 873 polling-delay-passive = <0>; 874 polling-delay = <0>; 875 thermal-sensors = <&thermal 6>; 876 sustainable-power = <5000>; 877 trips {}; 878 cooling-maps {}; 879 }; 880 }; 881 882 pwm0: pwm@1100e000 { 883 compatible = "mediatek,mt8183-disp-pwm"; 884 reg = <0 0x1100e000 0 0x1000>; 885 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 886 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 887 #pwm-cells = <2>; 888 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 889 <&infracfg CLK_INFRA_DISP_PWM>; 890 clock-names = "main", "mm"; 891 }; 892 893 pwm1: pwm@11006000 { 894 compatible = "mediatek,mt8183-pwm"; 895 reg = <0 0x11006000 0 0x1000>; 896 #pwm-cells = <2>; 897 clocks = <&infracfg CLK_INFRA_PWM>, 898 <&infracfg CLK_INFRA_PWM_HCLK>, 899 <&infracfg CLK_INFRA_PWM1>, 900 <&infracfg CLK_INFRA_PWM2>, 901 <&infracfg CLK_INFRA_PWM3>, 902 <&infracfg CLK_INFRA_PWM4>; 903 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 904 "pwm4"; 905 }; 906 907 i2c3: i2c@1100f000 { 908 compatible = "mediatek,mt8183-i2c"; 909 reg = <0 0x1100f000 0 0x1000>, 910 <0 0x11000400 0 0x80>; 911 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 912 clocks = <&infracfg CLK_INFRA_I2C3>, 913 <&infracfg CLK_INFRA_AP_DMA>; 914 clock-names = "main", "dma"; 915 clock-div = <1>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 spi1: spi@11010000 { 922 compatible = "mediatek,mt8183-spi"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 reg = <0 0x11010000 0 0x1000>; 926 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 927 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 928 <&topckgen CLK_TOP_MUX_SPI>, 929 <&infracfg CLK_INFRA_SPI1>; 930 clock-names = "parent-clk", "sel-clk", "spi-clk"; 931 status = "disabled"; 932 }; 933 934 i2c1: i2c@11011000 { 935 compatible = "mediatek,mt8183-i2c"; 936 reg = <0 0x11011000 0 0x1000>, 937 <0 0x11000480 0 0x80>; 938 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 939 clocks = <&infracfg CLK_INFRA_I2C4>, 940 <&infracfg CLK_INFRA_AP_DMA>; 941 clock-names = "main", "dma"; 942 clock-div = <1>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 spi2: spi@11012000 { 949 compatible = "mediatek,mt8183-spi"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 reg = <0 0x11012000 0 0x1000>; 953 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 954 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 955 <&topckgen CLK_TOP_MUX_SPI>, 956 <&infracfg CLK_INFRA_SPI2>; 957 clock-names = "parent-clk", "sel-clk", "spi-clk"; 958 status = "disabled"; 959 }; 960 961 spi3: spi@11013000 { 962 compatible = "mediatek,mt8183-spi"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 reg = <0 0x11013000 0 0x1000>; 966 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 967 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 968 <&topckgen CLK_TOP_MUX_SPI>, 969 <&infracfg CLK_INFRA_SPI3>; 970 clock-names = "parent-clk", "sel-clk", "spi-clk"; 971 status = "disabled"; 972 }; 973 974 i2c9: i2c@11014000 { 975 compatible = "mediatek,mt8183-i2c"; 976 reg = <0 0x11014000 0 0x1000>, 977 <0 0x11000180 0 0x80>; 978 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 979 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 980 <&infracfg CLK_INFRA_AP_DMA>, 981 <&infracfg CLK_INFRA_I2C1_ARBITER>; 982 clock-names = "main", "dma", "arb"; 983 clock-div = <1>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 i2c10: i2c@11015000 { 990 compatible = "mediatek,mt8183-i2c"; 991 reg = <0 0x11015000 0 0x1000>, 992 <0 0x11000300 0 0x80>; 993 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 994 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 995 <&infracfg CLK_INFRA_AP_DMA>, 996 <&infracfg CLK_INFRA_I2C2_ARBITER>; 997 clock-names = "main", "dma", "arb"; 998 clock-div = <1>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 i2c5: i2c@11016000 { 1005 compatible = "mediatek,mt8183-i2c"; 1006 reg = <0 0x11016000 0 0x1000>, 1007 <0 0x11000500 0 0x80>; 1008 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1009 clocks = <&infracfg CLK_INFRA_I2C5>, 1010 <&infracfg CLK_INFRA_AP_DMA>, 1011 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1012 clock-names = "main", "dma", "arb"; 1013 clock-div = <1>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c11: i2c@11017000 { 1020 compatible = "mediatek,mt8183-i2c"; 1021 reg = <0 0x11017000 0 0x1000>, 1022 <0 0x11000580 0 0x80>; 1023 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1024 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1025 <&infracfg CLK_INFRA_AP_DMA>, 1026 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1027 clock-names = "main", "dma", "arb"; 1028 clock-div = <1>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 spi4: spi@11018000 { 1035 compatible = "mediatek,mt8183-spi"; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 reg = <0 0x11018000 0 0x1000>; 1039 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1040 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1041 <&topckgen CLK_TOP_MUX_SPI>, 1042 <&infracfg CLK_INFRA_SPI4>; 1043 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1044 status = "disabled"; 1045 }; 1046 1047 spi5: spi@11019000 { 1048 compatible = "mediatek,mt8183-spi"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 reg = <0 0x11019000 0 0x1000>; 1052 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1053 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1054 <&topckgen CLK_TOP_MUX_SPI>, 1055 <&infracfg CLK_INFRA_SPI5>; 1056 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1057 status = "disabled"; 1058 }; 1059 1060 i2c7: i2c@1101a000 { 1061 compatible = "mediatek,mt8183-i2c"; 1062 reg = <0 0x1101a000 0 0x1000>, 1063 <0 0x11000680 0 0x80>; 1064 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1065 clocks = <&infracfg CLK_INFRA_I2C7>, 1066 <&infracfg CLK_INFRA_AP_DMA>; 1067 clock-names = "main", "dma"; 1068 clock-div = <1>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 i2c8: i2c@1101b000 { 1075 compatible = "mediatek,mt8183-i2c"; 1076 reg = <0 0x1101b000 0 0x1000>, 1077 <0 0x11000700 0 0x80>; 1078 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1079 clocks = <&infracfg CLK_INFRA_I2C8>, 1080 <&infracfg CLK_INFRA_AP_DMA>; 1081 clock-names = "main", "dma"; 1082 clock-div = <1>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 ssusb: usb@11201000 { 1089 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 1090 reg = <0 0x11201000 0 0x2e00>, 1091 <0 0x11203e00 0 0x0100>; 1092 reg-names = "mac", "ippc"; 1093 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1094 phys = <&u2port0 PHY_TYPE_USB2>, 1095 <&u3port0 PHY_TYPE_USB3>; 1096 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1097 <&infracfg CLK_INFRA_USB>; 1098 clock-names = "sys_ck", "ref_ck"; 1099 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1100 #address-cells = <2>; 1101 #size-cells = <2>; 1102 ranges; 1103 status = "disabled"; 1104 1105 usb_host: usb@11200000 { 1106 compatible = "mediatek,mt8183-xhci", 1107 "mediatek,mtk-xhci"; 1108 reg = <0 0x11200000 0 0x1000>; 1109 reg-names = "mac"; 1110 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1111 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1112 <&infracfg CLK_INFRA_USB>; 1113 clock-names = "sys_ck", "ref_ck"; 1114 status = "disabled"; 1115 }; 1116 }; 1117 1118 audiosys: audio-controller@11220000 { 1119 compatible = "mediatek,mt8183-audiosys", "syscon"; 1120 reg = <0 0x11220000 0 0x1000>; 1121 #clock-cells = <1>; 1122 afe: mt8183-afe-pcm { 1123 compatible = "mediatek,mt8183-audio"; 1124 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1125 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1126 reset-names = "audiosys"; 1127 power-domains = 1128 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1129 clocks = <&audiosys CLK_AUDIO_AFE>, 1130 <&audiosys CLK_AUDIO_DAC>, 1131 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1132 <&audiosys CLK_AUDIO_ADC>, 1133 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1134 <&audiosys CLK_AUDIO_22M>, 1135 <&audiosys CLK_AUDIO_24M>, 1136 <&audiosys CLK_AUDIO_APLL_TUNER>, 1137 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1138 <&audiosys CLK_AUDIO_I2S1>, 1139 <&audiosys CLK_AUDIO_I2S2>, 1140 <&audiosys CLK_AUDIO_I2S3>, 1141 <&audiosys CLK_AUDIO_I2S4>, 1142 <&audiosys CLK_AUDIO_TDM>, 1143 <&audiosys CLK_AUDIO_TML>, 1144 <&infracfg CLK_INFRA_AUDIO>, 1145 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1146 <&topckgen CLK_TOP_MUX_AUDIO>, 1147 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1148 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1149 <&topckgen CLK_TOP_MUX_AUD_1>, 1150 <&topckgen CLK_TOP_APLL1_CK>, 1151 <&topckgen CLK_TOP_MUX_AUD_2>, 1152 <&topckgen CLK_TOP_APLL2_CK>, 1153 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1154 <&topckgen CLK_TOP_APLL1_D8>, 1155 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1156 <&topckgen CLK_TOP_APLL2_D8>, 1157 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1158 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1159 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1160 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1161 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1162 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1163 <&topckgen CLK_TOP_APLL12_DIV0>, 1164 <&topckgen CLK_TOP_APLL12_DIV1>, 1165 <&topckgen CLK_TOP_APLL12_DIV2>, 1166 <&topckgen CLK_TOP_APLL12_DIV3>, 1167 <&topckgen CLK_TOP_APLL12_DIV4>, 1168 <&topckgen CLK_TOP_APLL12_DIVB>, 1169 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1170 <&clk26m>; 1171 clock-names = "aud_afe_clk", 1172 "aud_dac_clk", 1173 "aud_dac_predis_clk", 1174 "aud_adc_clk", 1175 "aud_adc_adda6_clk", 1176 "aud_apll22m_clk", 1177 "aud_apll24m_clk", 1178 "aud_apll1_tuner_clk", 1179 "aud_apll2_tuner_clk", 1180 "aud_i2s1_bclk_sw", 1181 "aud_i2s2_bclk_sw", 1182 "aud_i2s3_bclk_sw", 1183 "aud_i2s4_bclk_sw", 1184 "aud_tdm_clk", 1185 "aud_tml_clk", 1186 "aud_infra_clk", 1187 "mtkaif_26m_clk", 1188 "top_mux_audio", 1189 "top_mux_aud_intbus", 1190 "top_syspll_d2_d4", 1191 "top_mux_aud_1", 1192 "top_apll1_ck", 1193 "top_mux_aud_2", 1194 "top_apll2_ck", 1195 "top_mux_aud_eng1", 1196 "top_apll1_d8", 1197 "top_mux_aud_eng2", 1198 "top_apll2_d8", 1199 "top_i2s0_m_sel", 1200 "top_i2s1_m_sel", 1201 "top_i2s2_m_sel", 1202 "top_i2s3_m_sel", 1203 "top_i2s4_m_sel", 1204 "top_i2s5_m_sel", 1205 "top_apll12_div0", 1206 "top_apll12_div1", 1207 "top_apll12_div2", 1208 "top_apll12_div3", 1209 "top_apll12_div4", 1210 "top_apll12_divb", 1211 /*"top_apll12_div5",*/ 1212 "top_clk26m_clk"; 1213 }; 1214 }; 1215 1216 mmc0: mmc@11230000 { 1217 compatible = "mediatek,mt8183-mmc"; 1218 reg = <0 0x11230000 0 0x1000>, 1219 <0 0x11f50000 0 0x1000>; 1220 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1221 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1222 <&infracfg CLK_INFRA_MSDC0>, 1223 <&infracfg CLK_INFRA_MSDC0_SCK>; 1224 clock-names = "source", "hclk", "source_cg"; 1225 status = "disabled"; 1226 }; 1227 1228 mmc1: mmc@11240000 { 1229 compatible = "mediatek,mt8183-mmc"; 1230 reg = <0 0x11240000 0 0x1000>, 1231 <0 0x11e10000 0 0x1000>; 1232 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1233 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1234 <&infracfg CLK_INFRA_MSDC1>, 1235 <&infracfg CLK_INFRA_MSDC1_SCK>; 1236 clock-names = "source", "hclk", "source_cg"; 1237 status = "disabled"; 1238 }; 1239 1240 mipi_tx0: dsi-phy@11e50000 { 1241 compatible = "mediatek,mt8183-mipi-tx"; 1242 reg = <0 0x11e50000 0 0x1000>; 1243 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1244 #clock-cells = <0>; 1245 #phy-cells = <0>; 1246 clock-output-names = "mipi_tx0_pll"; 1247 nvmem-cells = <&mipi_tx_calibration>; 1248 nvmem-cell-names = "calibration-data"; 1249 }; 1250 1251 efuse: efuse@11f10000 { 1252 compatible = "mediatek,mt8183-efuse", 1253 "mediatek,efuse"; 1254 reg = <0 0x11f10000 0 0x1000>; 1255 #address-cells = <1>; 1256 #size-cells = <1>; 1257 thermal_calibration: calib@180 { 1258 reg = <0x180 0xc>; 1259 }; 1260 1261 mipi_tx_calibration: calib@190 { 1262 reg = <0x190 0xc>; 1263 }; 1264 }; 1265 1266 u3phy: t-phy@11f40000 { 1267 compatible = "mediatek,mt8183-tphy", 1268 "mediatek,generic-tphy-v2"; 1269 #address-cells = <1>; 1270 #size-cells = <1>; 1271 ranges = <0 0 0x11f40000 0x1000>; 1272 status = "okay"; 1273 1274 u2port0: usb-phy@0 { 1275 reg = <0x0 0x700>; 1276 clocks = <&clk26m>; 1277 clock-names = "ref"; 1278 #phy-cells = <1>; 1279 mediatek,discth = <15>; 1280 status = "okay"; 1281 }; 1282 1283 u3port0: usb-phy@700 { 1284 reg = <0x0700 0x900>; 1285 clocks = <&clk26m>; 1286 clock-names = "ref"; 1287 #phy-cells = <1>; 1288 status = "okay"; 1289 }; 1290 }; 1291 1292 mfgcfg: syscon@13000000 { 1293 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1294 reg = <0 0x13000000 0 0x1000>; 1295 #clock-cells = <1>; 1296 }; 1297 1298 gpu: gpu@13040000 { 1299 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; 1300 reg = <0 0x13040000 0 0x4000>; 1301 interrupts = 1302 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1303 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1304 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1305 interrupt-names = "job", "mmu", "gpu"; 1306 1307 clocks = <&topckgen CLK_TOP_MFGPLL_CK>; 1308 1309 power-domains = 1310 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1311 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1312 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1313 power-domain-names = "core0", "core1", "core2"; 1314 1315 operating-points-v2 = <&gpu_opp_table>; 1316 }; 1317 1318 mmsys: syscon@14000000 { 1319 compatible = "mediatek,mt8183-mmsys", "syscon"; 1320 reg = <0 0x14000000 0 0x1000>; 1321 #clock-cells = <1>; 1322 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1323 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1324 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1325 }; 1326 1327 ovl0: ovl@14008000 { 1328 compatible = "mediatek,mt8183-disp-ovl"; 1329 reg = <0 0x14008000 0 0x1000>; 1330 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1331 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1332 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1333 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1334 mediatek,larb = <&larb0>; 1335 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1336 }; 1337 1338 ovl_2l0: ovl@14009000 { 1339 compatible = "mediatek,mt8183-disp-ovl-2l"; 1340 reg = <0 0x14009000 0 0x1000>; 1341 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1342 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1343 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1344 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1345 mediatek,larb = <&larb0>; 1346 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1347 }; 1348 1349 ovl_2l1: ovl@1400a000 { 1350 compatible = "mediatek,mt8183-disp-ovl-2l"; 1351 reg = <0 0x1400a000 0 0x1000>; 1352 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1353 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1354 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1355 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1356 mediatek,larb = <&larb0>; 1357 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1358 }; 1359 1360 rdma0: rdma@1400b000 { 1361 compatible = "mediatek,mt8183-disp-rdma"; 1362 reg = <0 0x1400b000 0 0x1000>; 1363 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1364 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1365 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1366 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1367 mediatek,larb = <&larb0>; 1368 mediatek,rdma-fifo-size = <5120>; 1369 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1370 }; 1371 1372 rdma1: rdma@1400c000 { 1373 compatible = "mediatek,mt8183-disp-rdma"; 1374 reg = <0 0x1400c000 0 0x1000>; 1375 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1376 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1377 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1378 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1379 mediatek,larb = <&larb0>; 1380 mediatek,rdma-fifo-size = <2048>; 1381 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1382 }; 1383 1384 color0: color@1400e000 { 1385 compatible = "mediatek,mt8183-disp-color", 1386 "mediatek,mt8173-disp-color"; 1387 reg = <0 0x1400e000 0 0x1000>; 1388 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1389 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1390 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1391 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1392 }; 1393 1394 ccorr0: ccorr@1400f000 { 1395 compatible = "mediatek,mt8183-disp-ccorr"; 1396 reg = <0 0x1400f000 0 0x1000>; 1397 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1398 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1399 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1400 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1401 }; 1402 1403 aal0: aal@14010000 { 1404 compatible = "mediatek,mt8183-disp-aal", 1405 "mediatek,mt8173-disp-aal"; 1406 reg = <0 0x14010000 0 0x1000>; 1407 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1408 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1409 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1410 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1411 }; 1412 1413 gamma0: gamma@14011000 { 1414 compatible = "mediatek,mt8183-disp-gamma"; 1415 reg = <0 0x14011000 0 0x1000>; 1416 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1417 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1418 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1419 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1420 }; 1421 1422 dither0: dither@14012000 { 1423 compatible = "mediatek,mt8183-disp-dither"; 1424 reg = <0 0x14012000 0 0x1000>; 1425 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1426 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1427 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1428 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1429 }; 1430 1431 dsi0: dsi@14014000 { 1432 compatible = "mediatek,mt8183-dsi"; 1433 reg = <0 0x14014000 0 0x1000>; 1434 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1435 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1436 mediatek,syscon-dsi = <&mmsys 0x140>; 1437 clocks = <&mmsys CLK_MM_DSI0_MM>, 1438 <&mmsys CLK_MM_DSI0_IF>, 1439 <&mipi_tx0>; 1440 clock-names = "engine", "digital", "hs"; 1441 phys = <&mipi_tx0>; 1442 phy-names = "dphy"; 1443 }; 1444 1445 mutex: mutex@14016000 { 1446 compatible = "mediatek,mt8183-disp-mutex"; 1447 reg = <0 0x14016000 0 0x1000>; 1448 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1449 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1450 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1451 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1452 }; 1453 1454 larb0: larb@14017000 { 1455 compatible = "mediatek,mt8183-smi-larb"; 1456 reg = <0 0x14017000 0 0x1000>; 1457 mediatek,smi = <&smi_common>; 1458 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1459 <&mmsys CLK_MM_SMI_LARB0>; 1460 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1461 clock-names = "apb", "smi"; 1462 }; 1463 1464 smi_common: smi@14019000 { 1465 compatible = "mediatek,mt8183-smi-common"; 1466 reg = <0 0x14019000 0 0x1000>; 1467 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1468 <&mmsys CLK_MM_SMI_COMMON>, 1469 <&mmsys CLK_MM_GALS_COMM0>, 1470 <&mmsys CLK_MM_GALS_COMM1>; 1471 clock-names = "apb", "smi", "gals0", "gals1"; 1472 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1473 }; 1474 1475 imgsys: syscon@15020000 { 1476 compatible = "mediatek,mt8183-imgsys", "syscon"; 1477 reg = <0 0x15020000 0 0x1000>; 1478 #clock-cells = <1>; 1479 }; 1480 1481 larb5: larb@15021000 { 1482 compatible = "mediatek,mt8183-smi-larb"; 1483 reg = <0 0x15021000 0 0x1000>; 1484 mediatek,smi = <&smi_common>; 1485 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1486 <&mmsys CLK_MM_GALS_IMG2MM>; 1487 clock-names = "apb", "smi", "gals"; 1488 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1489 }; 1490 1491 larb2: larb@1502f000 { 1492 compatible = "mediatek,mt8183-smi-larb"; 1493 reg = <0 0x1502f000 0 0x1000>; 1494 mediatek,smi = <&smi_common>; 1495 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1496 <&mmsys CLK_MM_GALS_IPU2MM>; 1497 clock-names = "apb", "smi", "gals"; 1498 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1499 }; 1500 1501 vdecsys: syscon@16000000 { 1502 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1503 reg = <0 0x16000000 0 0x1000>; 1504 #clock-cells = <1>; 1505 }; 1506 1507 larb1: larb@16010000 { 1508 compatible = "mediatek,mt8183-smi-larb"; 1509 reg = <0 0x16010000 0 0x1000>; 1510 mediatek,smi = <&smi_common>; 1511 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1512 clock-names = "apb", "smi"; 1513 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1514 }; 1515 1516 vencsys: syscon@17000000 { 1517 compatible = "mediatek,mt8183-vencsys", "syscon"; 1518 reg = <0 0x17000000 0 0x1000>; 1519 #clock-cells = <1>; 1520 }; 1521 1522 larb4: larb@17010000 { 1523 compatible = "mediatek,mt8183-smi-larb"; 1524 reg = <0 0x17010000 0 0x1000>; 1525 mediatek,smi = <&smi_common>; 1526 clocks = <&vencsys CLK_VENC_LARB>, 1527 <&vencsys CLK_VENC_LARB>; 1528 clock-names = "apb", "smi"; 1529 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1530 }; 1531 1532 ipu_conn: syscon@19000000 { 1533 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1534 reg = <0 0x19000000 0 0x1000>; 1535 #clock-cells = <1>; 1536 }; 1537 1538 ipu_adl: syscon@19010000 { 1539 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1540 reg = <0 0x19010000 0 0x1000>; 1541 #clock-cells = <1>; 1542 }; 1543 1544 ipu_core0: syscon@19180000 { 1545 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1546 reg = <0 0x19180000 0 0x1000>; 1547 #clock-cells = <1>; 1548 }; 1549 1550 ipu_core1: syscon@19280000 { 1551 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1552 reg = <0 0x19280000 0 0x1000>; 1553 #clock-cells = <1>; 1554 }; 1555 1556 camsys: syscon@1a000000 { 1557 compatible = "mediatek,mt8183-camsys", "syscon"; 1558 reg = <0 0x1a000000 0 0x1000>; 1559 #clock-cells = <1>; 1560 }; 1561 1562 larb6: larb@1a001000 { 1563 compatible = "mediatek,mt8183-smi-larb"; 1564 reg = <0 0x1a001000 0 0x1000>; 1565 mediatek,smi = <&smi_common>; 1566 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1567 <&mmsys CLK_MM_GALS_CAM2MM>; 1568 clock-names = "apb", "smi", "gals"; 1569 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1570 }; 1571 1572 larb3: larb@1a002000 { 1573 compatible = "mediatek,mt8183-smi-larb"; 1574 reg = <0 0x1a002000 0 0x1000>; 1575 mediatek,smi = <&smi_common>; 1576 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1577 <&mmsys CLK_MM_GALS_IPU12MM>; 1578 clock-names = "apb", "smi", "gals"; 1579 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1580 }; 1581 }; 1582}; 1583