1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	compatible = "mediatek,mt8183";
14	interrupt-parent = <&sysirq>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu-map {
23			cluster0 {
24				core0 {
25					cpu = <&cpu0>;
26				};
27				core1 {
28					cpu = <&cpu1>;
29				};
30				core2 {
31					cpu = <&cpu2>;
32				};
33				core3 {
34					cpu = <&cpu3>;
35				};
36			};
37
38			cluster1 {
39				core0 {
40					cpu = <&cpu4>;
41				};
42				core1 {
43					cpu = <&cpu5>;
44				};
45				core2 {
46					cpu = <&cpu6>;
47				};
48				core3 {
49					cpu = <&cpu7>;
50				};
51			};
52		};
53
54		cpu0: cpu@0 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a53";
57			reg = <0x000>;
58			enable-method = "psci";
59		};
60
61		cpu1: cpu@1 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a53";
64			reg = <0x001>;
65			enable-method = "psci";
66		};
67
68		cpu2: cpu@2 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a53";
71			reg = <0x002>;
72			enable-method = "psci";
73		};
74
75		cpu3: cpu@3 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a53";
78			reg = <0x003>;
79			enable-method = "psci";
80		};
81
82		cpu4: cpu@100 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a73";
85			reg = <0x100>;
86			enable-method = "psci";
87		};
88
89		cpu5: cpu@101 {
90			device_type = "cpu";
91			compatible = "arm,cortex-a73";
92			reg = <0x101>;
93			enable-method = "psci";
94		};
95
96		cpu6: cpu@102 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a73";
99			reg = <0x102>;
100			enable-method = "psci";
101		};
102
103		cpu7: cpu@103 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a73";
106			reg = <0x103>;
107			enable-method = "psci";
108		};
109	};
110
111	pmu-a53 {
112		compatible = "arm,cortex-a53-pmu";
113		interrupt-parent = <&gic>;
114		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
115	};
116
117	pmu-a73 {
118		compatible = "arm,cortex-a73-pmu";
119		interrupt-parent = <&gic>;
120		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
121	};
122
123	psci {
124		compatible      = "arm,psci-1.0";
125		method          = "smc";
126	};
127
128	clk26m: oscillator {
129		compatible = "fixed-clock";
130		#clock-cells = <0>;
131		clock-frequency = <26000000>;
132		clock-output-names = "clk26m";
133	};
134
135	timer {
136		compatible = "arm,armv8-timer";
137		interrupt-parent = <&gic>;
138		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
139			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
140			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
141			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
142	};
143
144	soc {
145		#address-cells = <2>;
146		#size-cells = <2>;
147		compatible = "simple-bus";
148		ranges;
149
150		gic: interrupt-controller@c000000 {
151			compatible = "arm,gic-v3";
152			#interrupt-cells = <4>;
153			interrupt-parent = <&gic>;
154			interrupt-controller;
155			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
156			      <0 0x0c100000 0 0x200000>, /* GICR */
157			      <0 0x0c400000 0 0x2000>,   /* GICC */
158			      <0 0x0c410000 0 0x1000>,   /* GICH */
159			      <0 0x0c420000 0 0x2000>;   /* GICV */
160
161			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
162			ppi-partitions {
163				ppi_cluster0: interrupt-partition-0 {
164					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
165				};
166				ppi_cluster1: interrupt-partition-1 {
167					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
168				};
169			};
170		};
171
172		mcucfg: syscon@c530000 {
173			compatible = "mediatek,mt8183-mcucfg", "syscon";
174			reg = <0 0x0c530000 0 0x1000>;
175			#clock-cells = <1>;
176		};
177
178		sysirq: interrupt-controller@c530a80 {
179			compatible = "mediatek,mt8183-sysirq",
180				     "mediatek,mt6577-sysirq";
181			interrupt-controller;
182			#interrupt-cells = <3>;
183			interrupt-parent = <&gic>;
184			reg = <0 0x0c530a80 0 0x50>;
185		};
186
187		topckgen: syscon@10000000 {
188			compatible = "mediatek,mt8183-topckgen", "syscon";
189			reg = <0 0x10000000 0 0x1000>;
190			#clock-cells = <1>;
191		};
192
193		infracfg: syscon@10001000 {
194			compatible = "mediatek,mt8183-infracfg", "syscon";
195			reg = <0 0x10001000 0 0x1000>;
196			#clock-cells = <1>;
197		};
198
199		apmixedsys: syscon@1000c000 {
200			compatible = "mediatek,mt8183-apmixedsys", "syscon";
201			reg = <0 0x1000c000 0 0x1000>;
202			#clock-cells = <1>;
203		};
204
205		pwrap: pwrap@1000d000 {
206			compatible = "mediatek,mt8183-pwrap";
207			reg = <0 0x1000d000 0 0x1000>;
208			reg-names = "pwrap";
209			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
210			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
211				 <&infracfg CLK_INFRA_PMIC_AP>;
212			clock-names = "spi", "wrap";
213		};
214
215		uart0: serial@11002000 {
216			compatible = "mediatek,mt8183-uart",
217				     "mediatek,mt6577-uart";
218			reg = <0 0x11002000 0 0x1000>;
219			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
220			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
221			clock-names = "baud", "bus";
222			status = "disabled";
223		};
224
225		uart1: serial@11003000 {
226			compatible = "mediatek,mt8183-uart",
227				     "mediatek,mt6577-uart";
228			reg = <0 0x11003000 0 0x1000>;
229			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
230			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
231			clock-names = "baud", "bus";
232			status = "disabled";
233		};
234
235		uart2: serial@11004000 {
236			compatible = "mediatek,mt8183-uart",
237				     "mediatek,mt6577-uart";
238			reg = <0 0x11004000 0 0x1000>;
239			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
240			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
241			clock-names = "baud", "bus";
242			status = "disabled";
243		};
244
245		audiosys: syscon@11220000 {
246			compatible = "mediatek,mt8183-audiosys", "syscon";
247			reg = <0 0x11220000 0 0x1000>;
248			#clock-cells = <1>;
249		};
250
251		mfgcfg: syscon@13000000 {
252			compatible = "mediatek,mt8183-mfgcfg", "syscon";
253			reg = <0 0x13000000 0 0x1000>;
254			#clock-cells = <1>;
255		};
256
257		mmsys: syscon@14000000 {
258			compatible = "mediatek,mt8183-mmsys", "syscon";
259			reg = <0 0x14000000 0 0x1000>;
260			#clock-cells = <1>;
261		};
262
263		imgsys: syscon@15020000 {
264			compatible = "mediatek,mt8183-imgsys", "syscon";
265			reg = <0 0x15020000 0 0x1000>;
266			#clock-cells = <1>;
267		};
268
269		vdecsys: syscon@16000000 {
270			compatible = "mediatek,mt8183-vdecsys", "syscon";
271			reg = <0 0x16000000 0 0x1000>;
272			#clock-cells = <1>;
273		};
274
275		vencsys: syscon@17000000 {
276			compatible = "mediatek,mt8183-vencsys", "syscon";
277			reg = <0 0x17000000 0 0x1000>;
278			#clock-cells = <1>;
279		};
280
281		ipu_conn: syscon@19000000 {
282			compatible = "mediatek,mt8183-ipu_conn", "syscon";
283			reg = <0 0x19000000 0 0x1000>;
284			#clock-cells = <1>;
285		};
286
287		ipu_adl: syscon@19010000 {
288			compatible = "mediatek,mt8183-ipu_adl", "syscon";
289			reg = <0 0x19010000 0 0x1000>;
290			#clock-cells = <1>;
291		};
292
293		ipu_core0: syscon@19180000 {
294			compatible = "mediatek,mt8183-ipu_core0", "syscon";
295			reg = <0 0x19180000 0 0x1000>;
296			#clock-cells = <1>;
297		};
298
299		ipu_core1: syscon@19280000 {
300			compatible = "mediatek,mt8183-ipu_core1", "syscon";
301			reg = <0 0x19280000 0 0x1000>;
302			#clock-cells = <1>;
303		};
304
305		camsys: syscon@1a000000 {
306			compatible = "mediatek,mt8183-camsys", "syscon";
307			reg = <0 0x1a000000 0 0x1000>;
308			#clock-cells = <1>;
309		};
310	};
311};
312