1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include "mt8183-pinfunc.h" 12 13/ { 14 compatible = "mediatek,mt8183"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 i2c6 = &i2c6; 27 i2c7 = &i2c7; 28 i2c8 = &i2c8; 29 i2c9 = &i2c9; 30 i2c10 = &i2c10; 31 i2c11 = &i2c11; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu-map { 39 cluster0 { 40 core0 { 41 cpu = <&cpu0>; 42 }; 43 core1 { 44 cpu = <&cpu1>; 45 }; 46 core2 { 47 cpu = <&cpu2>; 48 }; 49 core3 { 50 cpu = <&cpu3>; 51 }; 52 }; 53 54 cluster1 { 55 core0 { 56 cpu = <&cpu4>; 57 }; 58 core1 { 59 cpu = <&cpu5>; 60 }; 61 core2 { 62 cpu = <&cpu6>; 63 }; 64 core3 { 65 cpu = <&cpu7>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <741>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x001>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <741>; 84 }; 85 86 cpu2: cpu@2 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x002>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <741>; 92 }; 93 94 cpu3: cpu@3 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x003>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <741>; 100 }; 101 102 cpu4: cpu@100 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a73"; 105 reg = <0x100>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1024>; 108 }; 109 110 cpu5: cpu@101 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a73"; 113 reg = <0x101>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <1024>; 116 }; 117 118 cpu6: cpu@102 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a73"; 121 reg = <0x102>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <1024>; 124 }; 125 126 cpu7: cpu@103 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a73"; 129 reg = <0x103>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 }; 133 }; 134 135 pmu-a53 { 136 compatible = "arm,cortex-a53-pmu"; 137 interrupt-parent = <&gic>; 138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 139 }; 140 141 pmu-a73 { 142 compatible = "arm,cortex-a73-pmu"; 143 interrupt-parent = <&gic>; 144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0"; 149 method = "smc"; 150 }; 151 152 clk26m: oscillator { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <26000000>; 156 clock-output-names = "clk26m"; 157 }; 158 159 timer { 160 compatible = "arm,armv8-timer"; 161 interrupt-parent = <&gic>; 162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 163 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 164 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 165 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 166 }; 167 168 soc { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 compatible = "simple-bus"; 172 ranges; 173 174 soc_data: soc_data@8000000 { 175 compatible = "mediatek,mt8183-efuse", 176 "mediatek,efuse"; 177 reg = <0 0x08000000 0 0x0010>; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 status = "disabled"; 181 }; 182 183 gic: interrupt-controller@c000000 { 184 compatible = "arm,gic-v3"; 185 #interrupt-cells = <4>; 186 interrupt-parent = <&gic>; 187 interrupt-controller; 188 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 189 <0 0x0c100000 0 0x200000>, /* GICR */ 190 <0 0x0c400000 0 0x2000>, /* GICC */ 191 <0 0x0c410000 0 0x1000>, /* GICH */ 192 <0 0x0c420000 0 0x2000>; /* GICV */ 193 194 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 195 ppi-partitions { 196 ppi_cluster0: interrupt-partition-0 { 197 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 198 }; 199 ppi_cluster1: interrupt-partition-1 { 200 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 201 }; 202 }; 203 }; 204 205 mcucfg: syscon@c530000 { 206 compatible = "mediatek,mt8183-mcucfg", "syscon"; 207 reg = <0 0x0c530000 0 0x1000>; 208 #clock-cells = <1>; 209 }; 210 211 sysirq: interrupt-controller@c530a80 { 212 compatible = "mediatek,mt8183-sysirq", 213 "mediatek,mt6577-sysirq"; 214 interrupt-controller; 215 #interrupt-cells = <3>; 216 interrupt-parent = <&gic>; 217 reg = <0 0x0c530a80 0 0x50>; 218 }; 219 220 topckgen: syscon@10000000 { 221 compatible = "mediatek,mt8183-topckgen", "syscon"; 222 reg = <0 0x10000000 0 0x1000>; 223 #clock-cells = <1>; 224 }; 225 226 infracfg: syscon@10001000 { 227 compatible = "mediatek,mt8183-infracfg", "syscon"; 228 reg = <0 0x10001000 0 0x1000>; 229 #clock-cells = <1>; 230 }; 231 232 pio: pinctrl@10005000 { 233 compatible = "mediatek,mt8183-pinctrl"; 234 reg = <0 0x10005000 0 0x1000>, 235 <0 0x11f20000 0 0x1000>, 236 <0 0x11e80000 0 0x1000>, 237 <0 0x11e70000 0 0x1000>, 238 <0 0x11e90000 0 0x1000>, 239 <0 0x11d30000 0 0x1000>, 240 <0 0x11d20000 0 0x1000>, 241 <0 0x11c50000 0 0x1000>, 242 <0 0x11f30000 0 0x1000>, 243 <0 0x1000b000 0 0x1000>; 244 reg-names = "iocfg0", "iocfg1", "iocfg2", 245 "iocfg3", "iocfg4", "iocfg5", 246 "iocfg6", "iocfg7", "iocfg8", 247 "eint"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 gpio-ranges = <&pio 0 0 192>; 251 interrupt-controller; 252 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 253 #interrupt-cells = <2>; 254 }; 255 256 apmixedsys: syscon@1000c000 { 257 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 258 reg = <0 0x1000c000 0 0x1000>; 259 #clock-cells = <1>; 260 }; 261 262 pwrap: pwrap@1000d000 { 263 compatible = "mediatek,mt8183-pwrap"; 264 reg = <0 0x1000d000 0 0x1000>; 265 reg-names = "pwrap"; 266 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 268 <&infracfg CLK_INFRA_PMIC_AP>; 269 clock-names = "spi", "wrap"; 270 }; 271 272 systimer: timer@10017000 { 273 compatible = "mediatek,mt8183-timer", 274 "mediatek,mt6765-timer"; 275 reg = <0 0x10017000 0 0x1000>; 276 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&topckgen CLK_TOP_CLK13M>; 278 clock-names = "clk13m"; 279 }; 280 281 gce: mailbox@10238000 { 282 compatible = "mediatek,mt8183-gce"; 283 reg = <0 0x10238000 0 0x4000>; 284 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 285 #mbox-cells = <3>; 286 clocks = <&infracfg CLK_INFRA_GCE>; 287 clock-names = "gce"; 288 }; 289 290 auxadc: auxadc@11001000 { 291 compatible = "mediatek,mt8183-auxadc", 292 "mediatek,mt8173-auxadc"; 293 reg = <0 0x11001000 0 0x1000>; 294 clocks = <&infracfg CLK_INFRA_AUXADC>; 295 clock-names = "main"; 296 #io-channel-cells = <1>; 297 status = "disabled"; 298 }; 299 300 uart0: serial@11002000 { 301 compatible = "mediatek,mt8183-uart", 302 "mediatek,mt6577-uart"; 303 reg = <0 0x11002000 0 0x1000>; 304 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 305 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 306 clock-names = "baud", "bus"; 307 status = "disabled"; 308 }; 309 310 uart1: serial@11003000 { 311 compatible = "mediatek,mt8183-uart", 312 "mediatek,mt6577-uart"; 313 reg = <0 0x11003000 0 0x1000>; 314 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 315 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 316 clock-names = "baud", "bus"; 317 status = "disabled"; 318 }; 319 320 uart2: serial@11004000 { 321 compatible = "mediatek,mt8183-uart", 322 "mediatek,mt6577-uart"; 323 reg = <0 0x11004000 0 0x1000>; 324 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 325 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 326 clock-names = "baud", "bus"; 327 status = "disabled"; 328 }; 329 330 i2c6: i2c@11005000 { 331 compatible = "mediatek,mt8183-i2c"; 332 reg = <0 0x11005000 0 0x1000>, 333 <0 0x11000600 0 0x80>; 334 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 335 clocks = <&infracfg CLK_INFRA_I2C6>, 336 <&infracfg CLK_INFRA_AP_DMA>; 337 clock-names = "main", "dma"; 338 clock-div = <1>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 i2c0: i2c@11007000 { 345 compatible = "mediatek,mt8183-i2c"; 346 reg = <0 0x11007000 0 0x1000>, 347 <0 0x11000080 0 0x80>; 348 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 349 clocks = <&infracfg CLK_INFRA_I2C0>, 350 <&infracfg CLK_INFRA_AP_DMA>; 351 clock-names = "main", "dma"; 352 clock-div = <1>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 i2c4: i2c@11008000 { 359 compatible = "mediatek,mt8183-i2c"; 360 reg = <0 0x11008000 0 0x1000>, 361 <0 0x11000100 0 0x80>; 362 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 363 clocks = <&infracfg CLK_INFRA_I2C1>, 364 <&infracfg CLK_INFRA_AP_DMA>, 365 <&infracfg CLK_INFRA_I2C1_ARBITER>; 366 clock-names = "main", "dma","arb"; 367 clock-div = <1>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 status = "disabled"; 371 }; 372 373 i2c2: i2c@11009000 { 374 compatible = "mediatek,mt8183-i2c"; 375 reg = <0 0x11009000 0 0x1000>, 376 <0 0x11000280 0 0x80>; 377 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 378 clocks = <&infracfg CLK_INFRA_I2C2>, 379 <&infracfg CLK_INFRA_AP_DMA>, 380 <&infracfg CLK_INFRA_I2C2_ARBITER>; 381 clock-names = "main", "dma", "arb"; 382 clock-div = <1>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 status = "disabled"; 386 }; 387 388 spi0: spi@1100a000 { 389 compatible = "mediatek,mt8183-spi"; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 reg = <0 0x1100a000 0 0x1000>; 393 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 394 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 395 <&topckgen CLK_TOP_MUX_SPI>, 396 <&infracfg CLK_INFRA_SPI0>; 397 clock-names = "parent-clk", "sel-clk", "spi-clk"; 398 status = "disabled"; 399 }; 400 401 i2c3: i2c@1100f000 { 402 compatible = "mediatek,mt8183-i2c"; 403 reg = <0 0x1100f000 0 0x1000>, 404 <0 0x11000400 0 0x80>; 405 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 406 clocks = <&infracfg CLK_INFRA_I2C3>, 407 <&infracfg CLK_INFRA_AP_DMA>; 408 clock-names = "main", "dma"; 409 clock-div = <1>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 spi1: spi@11010000 { 416 compatible = "mediatek,mt8183-spi"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 reg = <0 0x11010000 0 0x1000>; 420 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 421 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 422 <&topckgen CLK_TOP_MUX_SPI>, 423 <&infracfg CLK_INFRA_SPI1>; 424 clock-names = "parent-clk", "sel-clk", "spi-clk"; 425 status = "disabled"; 426 }; 427 428 i2c1: i2c@11011000 { 429 compatible = "mediatek,mt8183-i2c"; 430 reg = <0 0x11011000 0 0x1000>, 431 <0 0x11000480 0 0x80>; 432 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 433 clocks = <&infracfg CLK_INFRA_I2C4>, 434 <&infracfg CLK_INFRA_AP_DMA>; 435 clock-names = "main", "dma"; 436 clock-div = <1>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 }; 441 442 spi2: spi@11012000 { 443 compatible = "mediatek,mt8183-spi"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 reg = <0 0x11012000 0 0x1000>; 447 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 448 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 449 <&topckgen CLK_TOP_MUX_SPI>, 450 <&infracfg CLK_INFRA_SPI2>; 451 clock-names = "parent-clk", "sel-clk", "spi-clk"; 452 status = "disabled"; 453 }; 454 455 spi3: spi@11013000 { 456 compatible = "mediatek,mt8183-spi"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 reg = <0 0x11013000 0 0x1000>; 460 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 461 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 462 <&topckgen CLK_TOP_MUX_SPI>, 463 <&infracfg CLK_INFRA_SPI3>; 464 clock-names = "parent-clk", "sel-clk", "spi-clk"; 465 status = "disabled"; 466 }; 467 468 i2c9: i2c@11014000 { 469 compatible = "mediatek,mt8183-i2c"; 470 reg = <0 0x11014000 0 0x1000>, 471 <0 0x11000180 0 0x80>; 472 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 473 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 474 <&infracfg CLK_INFRA_AP_DMA>, 475 <&infracfg CLK_INFRA_I2C1_ARBITER>; 476 clock-names = "main", "dma", "arb"; 477 clock-div = <1>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 status = "disabled"; 481 }; 482 483 i2c10: i2c@11015000 { 484 compatible = "mediatek,mt8183-i2c"; 485 reg = <0 0x11015000 0 0x1000>, 486 <0 0x11000300 0 0x80>; 487 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 488 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 489 <&infracfg CLK_INFRA_AP_DMA>, 490 <&infracfg CLK_INFRA_I2C2_ARBITER>; 491 clock-names = "main", "dma", "arb"; 492 clock-div = <1>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 i2c5: i2c@11016000 { 499 compatible = "mediatek,mt8183-i2c"; 500 reg = <0 0x11016000 0 0x1000>, 501 <0 0x11000500 0 0x80>; 502 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 503 clocks = <&infracfg CLK_INFRA_I2C5>, 504 <&infracfg CLK_INFRA_AP_DMA>, 505 <&infracfg CLK_INFRA_I2C5_ARBITER>; 506 clock-names = "main", "dma", "arb"; 507 clock-div = <1>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 }; 512 513 i2c11: i2c@11017000 { 514 compatible = "mediatek,mt8183-i2c"; 515 reg = <0 0x11017000 0 0x1000>, 516 <0 0x11000580 0 0x80>; 517 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 518 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 519 <&infracfg CLK_INFRA_AP_DMA>, 520 <&infracfg CLK_INFRA_I2C5_ARBITER>; 521 clock-names = "main", "dma", "arb"; 522 clock-div = <1>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 }; 527 528 spi4: spi@11018000 { 529 compatible = "mediatek,mt8183-spi"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 reg = <0 0x11018000 0 0x1000>; 533 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 534 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 535 <&topckgen CLK_TOP_MUX_SPI>, 536 <&infracfg CLK_INFRA_SPI4>; 537 clock-names = "parent-clk", "sel-clk", "spi-clk"; 538 status = "disabled"; 539 }; 540 541 spi5: spi@11019000 { 542 compatible = "mediatek,mt8183-spi"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 reg = <0 0x11019000 0 0x1000>; 546 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 547 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 548 <&topckgen CLK_TOP_MUX_SPI>, 549 <&infracfg CLK_INFRA_SPI5>; 550 clock-names = "parent-clk", "sel-clk", "spi-clk"; 551 status = "disabled"; 552 }; 553 554 i2c7: i2c@1101a000 { 555 compatible = "mediatek,mt8183-i2c"; 556 reg = <0 0x1101a000 0 0x1000>, 557 <0 0x11000680 0 0x80>; 558 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 559 clocks = <&infracfg CLK_INFRA_I2C7>, 560 <&infracfg CLK_INFRA_AP_DMA>; 561 clock-names = "main", "dma"; 562 clock-div = <1>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 i2c8: i2c@1101b000 { 569 compatible = "mediatek,mt8183-i2c"; 570 reg = <0 0x1101b000 0 0x1000>, 571 <0 0x11000700 0 0x80>; 572 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 573 clocks = <&infracfg CLK_INFRA_I2C8>, 574 <&infracfg CLK_INFRA_AP_DMA>; 575 clock-names = "main", "dma"; 576 clock-div = <1>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 status = "disabled"; 580 }; 581 582 audiosys: syscon@11220000 { 583 compatible = "mediatek,mt8183-audiosys", "syscon"; 584 reg = <0 0x11220000 0 0x1000>; 585 #clock-cells = <1>; 586 }; 587 588 efuse: efuse@11f10000 { 589 compatible = "mediatek,mt8183-efuse", 590 "mediatek,efuse"; 591 reg = <0 0x11f10000 0 0x1000>; 592 }; 593 594 mfgcfg: syscon@13000000 { 595 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 596 reg = <0 0x13000000 0 0x1000>; 597 #clock-cells = <1>; 598 }; 599 600 mmsys: syscon@14000000 { 601 compatible = "mediatek,mt8183-mmsys", "syscon"; 602 reg = <0 0x14000000 0 0x1000>; 603 #clock-cells = <1>; 604 }; 605 606 imgsys: syscon@15020000 { 607 compatible = "mediatek,mt8183-imgsys", "syscon"; 608 reg = <0 0x15020000 0 0x1000>; 609 #clock-cells = <1>; 610 }; 611 612 vdecsys: syscon@16000000 { 613 compatible = "mediatek,mt8183-vdecsys", "syscon"; 614 reg = <0 0x16000000 0 0x1000>; 615 #clock-cells = <1>; 616 }; 617 618 vencsys: syscon@17000000 { 619 compatible = "mediatek,mt8183-vencsys", "syscon"; 620 reg = <0 0x17000000 0 0x1000>; 621 #clock-cells = <1>; 622 }; 623 624 ipu_conn: syscon@19000000 { 625 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 626 reg = <0 0x19000000 0 0x1000>; 627 #clock-cells = <1>; 628 }; 629 630 ipu_adl: syscon@19010000 { 631 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 632 reg = <0 0x19010000 0 0x1000>; 633 #clock-cells = <1>; 634 }; 635 636 ipu_core0: syscon@19180000 { 637 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 638 reg = <0 0x19180000 0 0x1000>; 639 #clock-cells = <1>; 640 }; 641 642 ipu_core1: syscon@19280000 { 643 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 644 reg = <0 0x19280000 0 0x1000>; 645 #clock-cells = <1>; 646 }; 647 648 camsys: syscon@1a000000 { 649 compatible = "mediatek,mt8183-camsys", "syscon"; 650 reg = <0 0x1a000000 0 0x1000>; 651 #clock-cells = <1>; 652 }; 653 }; 654}; 655