1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cci: cci { 284 compatible = "mediatek,mt8183-cci"; 285 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 clock-names = "cci", "intermediate"; 288 operating-points-v2 = <&cci_opp>; 289 }; 290 291 cpus { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&cpu0>; 299 }; 300 core1 { 301 cpu = <&cpu1>; 302 }; 303 core2 { 304 cpu = <&cpu2>; 305 }; 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 }; 310 311 cluster1 { 312 core0 { 313 cpu = <&cpu4>; 314 }; 315 core1 { 316 cpu = <&cpu5>; 317 }; 318 core2 { 319 cpu = <&cpu6>; 320 }; 321 core3 { 322 cpu = <&cpu7>; 323 }; 324 }; 325 }; 326 327 cpu0: cpu@0 { 328 device_type = "cpu"; 329 compatible = "arm,cortex-a53"; 330 reg = <0x000>; 331 enable-method = "psci"; 332 capacity-dmips-mhz = <741>; 333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 336 clock-names = "cpu", "intermediate"; 337 operating-points-v2 = <&cluster0_opp>; 338 dynamic-power-coefficient = <84>; 339 #cooling-cells = <2>; 340 mediatek,cci = <&cci>; 341 }; 342 343 cpu1: cpu@1 { 344 device_type = "cpu"; 345 compatible = "arm,cortex-a53"; 346 reg = <0x001>; 347 enable-method = "psci"; 348 capacity-dmips-mhz = <741>; 349 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 350 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 351 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 352 clock-names = "cpu", "intermediate"; 353 operating-points-v2 = <&cluster0_opp>; 354 dynamic-power-coefficient = <84>; 355 #cooling-cells = <2>; 356 mediatek,cci = <&cci>; 357 }; 358 359 cpu2: cpu@2 { 360 device_type = "cpu"; 361 compatible = "arm,cortex-a53"; 362 reg = <0x002>; 363 enable-method = "psci"; 364 capacity-dmips-mhz = <741>; 365 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 366 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 367 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 368 clock-names = "cpu", "intermediate"; 369 operating-points-v2 = <&cluster0_opp>; 370 dynamic-power-coefficient = <84>; 371 #cooling-cells = <2>; 372 mediatek,cci = <&cci>; 373 }; 374 375 cpu3: cpu@3 { 376 device_type = "cpu"; 377 compatible = "arm,cortex-a53"; 378 reg = <0x003>; 379 enable-method = "psci"; 380 capacity-dmips-mhz = <741>; 381 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 382 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 383 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 384 clock-names = "cpu", "intermediate"; 385 operating-points-v2 = <&cluster0_opp>; 386 dynamic-power-coefficient = <84>; 387 #cooling-cells = <2>; 388 mediatek,cci = <&cci>; 389 }; 390 391 cpu4: cpu@100 { 392 device_type = "cpu"; 393 compatible = "arm,cortex-a73"; 394 reg = <0x100>; 395 enable-method = "psci"; 396 capacity-dmips-mhz = <1024>; 397 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 398 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 399 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 400 clock-names = "cpu", "intermediate"; 401 operating-points-v2 = <&cluster1_opp>; 402 dynamic-power-coefficient = <211>; 403 #cooling-cells = <2>; 404 mediatek,cci = <&cci>; 405 }; 406 407 cpu5: cpu@101 { 408 device_type = "cpu"; 409 compatible = "arm,cortex-a73"; 410 reg = <0x101>; 411 enable-method = "psci"; 412 capacity-dmips-mhz = <1024>; 413 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 414 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 415 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 416 clock-names = "cpu", "intermediate"; 417 operating-points-v2 = <&cluster1_opp>; 418 dynamic-power-coefficient = <211>; 419 #cooling-cells = <2>; 420 mediatek,cci = <&cci>; 421 }; 422 423 cpu6: cpu@102 { 424 device_type = "cpu"; 425 compatible = "arm,cortex-a73"; 426 reg = <0x102>; 427 enable-method = "psci"; 428 capacity-dmips-mhz = <1024>; 429 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 430 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 431 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 432 clock-names = "cpu", "intermediate"; 433 operating-points-v2 = <&cluster1_opp>; 434 dynamic-power-coefficient = <211>; 435 #cooling-cells = <2>; 436 mediatek,cci = <&cci>; 437 }; 438 439 cpu7: cpu@103 { 440 device_type = "cpu"; 441 compatible = "arm,cortex-a73"; 442 reg = <0x103>; 443 enable-method = "psci"; 444 capacity-dmips-mhz = <1024>; 445 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 446 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 447 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 448 clock-names = "cpu", "intermediate"; 449 operating-points-v2 = <&cluster1_opp>; 450 dynamic-power-coefficient = <211>; 451 #cooling-cells = <2>; 452 mediatek,cci = <&cci>; 453 }; 454 455 idle-states { 456 entry-method = "psci"; 457 458 CPU_SLEEP: cpu-sleep { 459 compatible = "arm,idle-state"; 460 local-timer-stop; 461 arm,psci-suspend-param = <0x00010001>; 462 entry-latency-us = <200>; 463 exit-latency-us = <200>; 464 min-residency-us = <800>; 465 }; 466 467 CLUSTER_SLEEP0: cluster-sleep-0 { 468 compatible = "arm,idle-state"; 469 local-timer-stop; 470 arm,psci-suspend-param = <0x01010001>; 471 entry-latency-us = <250>; 472 exit-latency-us = <400>; 473 min-residency-us = <1000>; 474 }; 475 CLUSTER_SLEEP1: cluster-sleep-1 { 476 compatible = "arm,idle-state"; 477 local-timer-stop; 478 arm,psci-suspend-param = <0x01010001>; 479 entry-latency-us = <250>; 480 exit-latency-us = <400>; 481 min-residency-us = <1300>; 482 }; 483 }; 484 }; 485 486 gpu_opp_table: opp-table-0 { 487 compatible = "operating-points-v2"; 488 opp-shared; 489 490 opp-300000000 { 491 opp-hz = /bits/ 64 <300000000>; 492 opp-microvolt = <625000>, <850000>; 493 }; 494 495 opp-320000000 { 496 opp-hz = /bits/ 64 <320000000>; 497 opp-microvolt = <631250>, <850000>; 498 }; 499 500 opp-340000000 { 501 opp-hz = /bits/ 64 <340000000>; 502 opp-microvolt = <637500>, <850000>; 503 }; 504 505 opp-360000000 { 506 opp-hz = /bits/ 64 <360000000>; 507 opp-microvolt = <643750>, <850000>; 508 }; 509 510 opp-380000000 { 511 opp-hz = /bits/ 64 <380000000>; 512 opp-microvolt = <650000>, <850000>; 513 }; 514 515 opp-400000000 { 516 opp-hz = /bits/ 64 <400000000>; 517 opp-microvolt = <656250>, <850000>; 518 }; 519 520 opp-420000000 { 521 opp-hz = /bits/ 64 <420000000>; 522 opp-microvolt = <662500>, <850000>; 523 }; 524 525 opp-460000000 { 526 opp-hz = /bits/ 64 <460000000>; 527 opp-microvolt = <675000>, <850000>; 528 }; 529 530 opp-500000000 { 531 opp-hz = /bits/ 64 <500000000>; 532 opp-microvolt = <687500>, <850000>; 533 }; 534 535 opp-540000000 { 536 opp-hz = /bits/ 64 <540000000>; 537 opp-microvolt = <700000>, <850000>; 538 }; 539 540 opp-580000000 { 541 opp-hz = /bits/ 64 <580000000>; 542 opp-microvolt = <712500>, <850000>; 543 }; 544 545 opp-620000000 { 546 opp-hz = /bits/ 64 <620000000>; 547 opp-microvolt = <725000>, <850000>; 548 }; 549 550 opp-653000000 { 551 opp-hz = /bits/ 64 <653000000>; 552 opp-microvolt = <743750>, <850000>; 553 }; 554 555 opp-698000000 { 556 opp-hz = /bits/ 64 <698000000>; 557 opp-microvolt = <768750>, <868750>; 558 }; 559 560 opp-743000000 { 561 opp-hz = /bits/ 64 <743000000>; 562 opp-microvolt = <793750>, <893750>; 563 }; 564 565 opp-800000000 { 566 opp-hz = /bits/ 64 <800000000>; 567 opp-microvolt = <825000>, <925000>; 568 }; 569 }; 570 571 pmu-a53 { 572 compatible = "arm,cortex-a53-pmu"; 573 interrupt-parent = <&gic>; 574 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 575 }; 576 577 pmu-a73 { 578 compatible = "arm,cortex-a73-pmu"; 579 interrupt-parent = <&gic>; 580 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 581 }; 582 583 psci { 584 compatible = "arm,psci-1.0"; 585 method = "smc"; 586 }; 587 588 clk13m: fixed-factor-clock-13m { 589 compatible = "fixed-factor-clock"; 590 #clock-cells = <0>; 591 clocks = <&clk26m>; 592 clock-div = <2>; 593 clock-mult = <1>; 594 clock-output-names = "clk13m"; 595 }; 596 597 clk26m: oscillator { 598 compatible = "fixed-clock"; 599 #clock-cells = <0>; 600 clock-frequency = <26000000>; 601 clock-output-names = "clk26m"; 602 }; 603 604 timer { 605 compatible = "arm,armv8-timer"; 606 interrupt-parent = <&gic>; 607 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 608 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 609 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 610 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 611 }; 612 613 soc { 614 #address-cells = <2>; 615 #size-cells = <2>; 616 compatible = "simple-bus"; 617 ranges; 618 619 soc_data: efuse@8000000 { 620 compatible = "mediatek,mt8183-efuse", 621 "mediatek,efuse"; 622 reg = <0 0x08000000 0 0x0010>; 623 #address-cells = <1>; 624 #size-cells = <1>; 625 status = "disabled"; 626 }; 627 628 gic: interrupt-controller@c000000 { 629 compatible = "arm,gic-v3"; 630 #interrupt-cells = <4>; 631 interrupt-parent = <&gic>; 632 interrupt-controller; 633 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 634 <0 0x0c100000 0 0x200000>, /* GICR */ 635 <0 0x0c400000 0 0x2000>, /* GICC */ 636 <0 0x0c410000 0 0x1000>, /* GICH */ 637 <0 0x0c420000 0 0x2000>; /* GICV */ 638 639 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 640 ppi-partitions { 641 ppi_cluster0: interrupt-partition-0 { 642 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 643 }; 644 ppi_cluster1: interrupt-partition-1 { 645 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 646 }; 647 }; 648 }; 649 650 mcucfg: syscon@c530000 { 651 compatible = "mediatek,mt8183-mcucfg", "syscon"; 652 reg = <0 0x0c530000 0 0x1000>; 653 #clock-cells = <1>; 654 }; 655 656 sysirq: interrupt-controller@c530a80 { 657 compatible = "mediatek,mt8183-sysirq", 658 "mediatek,mt6577-sysirq"; 659 interrupt-controller; 660 #interrupt-cells = <3>; 661 interrupt-parent = <&gic>; 662 reg = <0 0x0c530a80 0 0x50>; 663 }; 664 665 cpu_debug0: cpu-debug@d410000 { 666 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 667 reg = <0x0 0xd410000 0x0 0x1000>; 668 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 669 clock-names = "apb_pclk"; 670 cpu = <&cpu0>; 671 }; 672 673 cpu_debug1: cpu-debug@d510000 { 674 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 675 reg = <0x0 0xd510000 0x0 0x1000>; 676 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 677 clock-names = "apb_pclk"; 678 cpu = <&cpu1>; 679 }; 680 681 cpu_debug2: cpu-debug@d610000 { 682 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 683 reg = <0x0 0xd610000 0x0 0x1000>; 684 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 685 clock-names = "apb_pclk"; 686 cpu = <&cpu2>; 687 }; 688 689 cpu_debug3: cpu-debug@d710000 { 690 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 691 reg = <0x0 0xd710000 0x0 0x1000>; 692 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 693 clock-names = "apb_pclk"; 694 cpu = <&cpu3>; 695 }; 696 697 cpu_debug4: cpu-debug@d810000 { 698 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 699 reg = <0x0 0xd810000 0x0 0x1000>; 700 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 701 clock-names = "apb_pclk"; 702 cpu = <&cpu4>; 703 }; 704 705 cpu_debug5: cpu-debug@d910000 { 706 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 707 reg = <0x0 0xd910000 0x0 0x1000>; 708 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 709 clock-names = "apb_pclk"; 710 cpu = <&cpu5>; 711 }; 712 713 cpu_debug6: cpu-debug@da10000 { 714 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 715 reg = <0x0 0xda10000 0x0 0x1000>; 716 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 717 clock-names = "apb_pclk"; 718 cpu = <&cpu6>; 719 }; 720 721 cpu_debug7: cpu-debug@db10000 { 722 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 723 reg = <0x0 0xdb10000 0x0 0x1000>; 724 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 725 clock-names = "apb_pclk"; 726 cpu = <&cpu7>; 727 }; 728 729 topckgen: syscon@10000000 { 730 compatible = "mediatek,mt8183-topckgen", "syscon"; 731 reg = <0 0x10000000 0 0x1000>; 732 #clock-cells = <1>; 733 }; 734 735 infracfg: syscon@10001000 { 736 compatible = "mediatek,mt8183-infracfg", "syscon"; 737 reg = <0 0x10001000 0 0x1000>; 738 #clock-cells = <1>; 739 #reset-cells = <1>; 740 }; 741 742 pericfg: syscon@10003000 { 743 compatible = "mediatek,mt8183-pericfg", "syscon"; 744 reg = <0 0x10003000 0 0x1000>; 745 #clock-cells = <1>; 746 }; 747 748 pio: pinctrl@10005000 { 749 compatible = "mediatek,mt8183-pinctrl"; 750 reg = <0 0x10005000 0 0x1000>, 751 <0 0x11f20000 0 0x1000>, 752 <0 0x11e80000 0 0x1000>, 753 <0 0x11e70000 0 0x1000>, 754 <0 0x11e90000 0 0x1000>, 755 <0 0x11d30000 0 0x1000>, 756 <0 0x11d20000 0 0x1000>, 757 <0 0x11c50000 0 0x1000>, 758 <0 0x11f30000 0 0x1000>, 759 <0 0x1000b000 0 0x1000>; 760 reg-names = "iocfg0", "iocfg1", "iocfg2", 761 "iocfg3", "iocfg4", "iocfg5", 762 "iocfg6", "iocfg7", "iocfg8", 763 "eint"; 764 gpio-controller; 765 #gpio-cells = <2>; 766 gpio-ranges = <&pio 0 0 192>; 767 interrupt-controller; 768 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 769 #interrupt-cells = <2>; 770 }; 771 772 scpsys: syscon@10006000 { 773 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; 774 reg = <0 0x10006000 0 0x1000>; 775 776 /* System Power Manager */ 777 spm: power-controller { 778 compatible = "mediatek,mt8183-power-controller"; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 #power-domain-cells = <1>; 782 783 /* power domain of the SoC */ 784 power-domain@MT8183_POWER_DOMAIN_AUDIO { 785 reg = <MT8183_POWER_DOMAIN_AUDIO>; 786 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 787 <&infracfg CLK_INFRA_AUDIO>, 788 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 789 clock-names = "audio", "audio1", "audio2"; 790 #power-domain-cells = <0>; 791 }; 792 793 power-domain@MT8183_POWER_DOMAIN_CONN { 794 reg = <MT8183_POWER_DOMAIN_CONN>; 795 mediatek,infracfg = <&infracfg>; 796 #power-domain-cells = <0>; 797 }; 798 799 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 800 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 801 clocks = <&topckgen CLK_TOP_MUX_MFG>; 802 clock-names = "mfg"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 #power-domain-cells = <1>; 806 807 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 808 reg = <MT8183_POWER_DOMAIN_MFG>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 #power-domain-cells = <1>; 812 813 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 814 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 815 #power-domain-cells = <0>; 816 }; 817 818 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 819 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 820 #power-domain-cells = <0>; 821 }; 822 823 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 824 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 825 mediatek,infracfg = <&infracfg>; 826 #power-domain-cells = <0>; 827 }; 828 }; 829 }; 830 831 power-domain@MT8183_POWER_DOMAIN_DISP { 832 reg = <MT8183_POWER_DOMAIN_DISP>; 833 clocks = <&topckgen CLK_TOP_MUX_MM>, 834 <&mmsys CLK_MM_SMI_COMMON>, 835 <&mmsys CLK_MM_SMI_LARB0>, 836 <&mmsys CLK_MM_SMI_LARB1>, 837 <&mmsys CLK_MM_GALS_COMM0>, 838 <&mmsys CLK_MM_GALS_COMM1>, 839 <&mmsys CLK_MM_GALS_CCU2MM>, 840 <&mmsys CLK_MM_GALS_IPU12MM>, 841 <&mmsys CLK_MM_GALS_IMG2MM>, 842 <&mmsys CLK_MM_GALS_CAM2MM>, 843 <&mmsys CLK_MM_GALS_IPU2MM>; 844 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 845 "mm-4", "mm-5", "mm-6", "mm-7", 846 "mm-8", "mm-9"; 847 mediatek,infracfg = <&infracfg>; 848 mediatek,smi = <&smi_common>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 #power-domain-cells = <1>; 852 853 power-domain@MT8183_POWER_DOMAIN_CAM { 854 reg = <MT8183_POWER_DOMAIN_CAM>; 855 clocks = <&topckgen CLK_TOP_MUX_CAM>, 856 <&camsys CLK_CAM_LARB6>, 857 <&camsys CLK_CAM_LARB3>, 858 <&camsys CLK_CAM_SENINF>, 859 <&camsys CLK_CAM_CAMSV0>, 860 <&camsys CLK_CAM_CAMSV1>, 861 <&camsys CLK_CAM_CAMSV2>, 862 <&camsys CLK_CAM_CCU>; 863 clock-names = "cam", "cam-0", "cam-1", 864 "cam-2", "cam-3", "cam-4", 865 "cam-5", "cam-6"; 866 mediatek,infracfg = <&infracfg>; 867 mediatek,smi = <&smi_common>; 868 #power-domain-cells = <0>; 869 }; 870 871 power-domain@MT8183_POWER_DOMAIN_ISP { 872 reg = <MT8183_POWER_DOMAIN_ISP>; 873 clocks = <&topckgen CLK_TOP_MUX_IMG>, 874 <&imgsys CLK_IMG_LARB5>, 875 <&imgsys CLK_IMG_LARB2>; 876 clock-names = "isp", "isp-0", "isp-1"; 877 mediatek,infracfg = <&infracfg>; 878 mediatek,smi = <&smi_common>; 879 #power-domain-cells = <0>; 880 }; 881 882 power-domain@MT8183_POWER_DOMAIN_VDEC { 883 reg = <MT8183_POWER_DOMAIN_VDEC>; 884 mediatek,smi = <&smi_common>; 885 #power-domain-cells = <0>; 886 }; 887 888 power-domain@MT8183_POWER_DOMAIN_VENC { 889 reg = <MT8183_POWER_DOMAIN_VENC>; 890 mediatek,smi = <&smi_common>; 891 #power-domain-cells = <0>; 892 }; 893 894 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 895 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 896 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 897 <&topckgen CLK_TOP_MUX_DSP>, 898 <&ipu_conn CLK_IPU_CONN_IPU>, 899 <&ipu_conn CLK_IPU_CONN_AHB>, 900 <&ipu_conn CLK_IPU_CONN_AXI>, 901 <&ipu_conn CLK_IPU_CONN_ISP>, 902 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 903 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 904 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 905 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 906 mediatek,infracfg = <&infracfg>; 907 mediatek,smi = <&smi_common>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 #power-domain-cells = <1>; 911 912 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 913 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 914 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 915 clock-names = "vpu2"; 916 mediatek,infracfg = <&infracfg>; 917 #power-domain-cells = <0>; 918 }; 919 920 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 921 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 922 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 923 clock-names = "vpu3"; 924 mediatek,infracfg = <&infracfg>; 925 #power-domain-cells = <0>; 926 }; 927 }; 928 }; 929 }; 930 }; 931 932 watchdog: watchdog@10007000 { 933 compatible = "mediatek,mt8183-wdt"; 934 reg = <0 0x10007000 0 0x100>; 935 #reset-cells = <1>; 936 }; 937 938 apmixedsys: syscon@1000c000 { 939 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 940 reg = <0 0x1000c000 0 0x1000>; 941 #clock-cells = <1>; 942 }; 943 944 pwrap: pwrap@1000d000 { 945 compatible = "mediatek,mt8183-pwrap"; 946 reg = <0 0x1000d000 0 0x1000>; 947 reg-names = "pwrap"; 948 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 950 <&infracfg CLK_INFRA_PMIC_AP>; 951 clock-names = "spi", "wrap"; 952 }; 953 954 keyboard: keyboard@10010000 { 955 compatible = "mediatek,mt6779-keypad"; 956 reg = <0 0x10010000 0 0x1000>; 957 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; 958 clocks = <&clk26m>; 959 clock-names = "kpd"; 960 status = "disabled"; 961 }; 962 963 scp: scp@10500000 { 964 compatible = "mediatek,mt8183-scp"; 965 reg = <0 0x10500000 0 0x80000>, 966 <0 0x105c0000 0 0x19080>; 967 reg-names = "sram", "cfg"; 968 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&infracfg CLK_INFRA_SCPSYS>; 970 clock-names = "main"; 971 memory-region = <&scp_mem_reserved>; 972 status = "disabled"; 973 }; 974 975 systimer: timer@10017000 { 976 compatible = "mediatek,mt8183-timer", 977 "mediatek,mt6765-timer"; 978 reg = <0 0x10017000 0 0x1000>; 979 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&clk13m>; 981 }; 982 983 iommu: iommu@10205000 { 984 compatible = "mediatek,mt8183-m4u"; 985 reg = <0 0x10205000 0 0x1000>; 986 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 987 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 988 <&larb4>, <&larb5>, <&larb6>; 989 #iommu-cells = <1>; 990 }; 991 992 gce: mailbox@10238000 { 993 compatible = "mediatek,mt8183-gce"; 994 reg = <0 0x10238000 0 0x4000>; 995 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 996 #mbox-cells = <2>; 997 clocks = <&infracfg CLK_INFRA_GCE>; 998 clock-names = "gce"; 999 }; 1000 1001 auxadc: auxadc@11001000 { 1002 compatible = "mediatek,mt8183-auxadc", 1003 "mediatek,mt8173-auxadc"; 1004 reg = <0 0x11001000 0 0x1000>; 1005 clocks = <&infracfg CLK_INFRA_AUXADC>; 1006 clock-names = "main"; 1007 #io-channel-cells = <1>; 1008 status = "disabled"; 1009 }; 1010 1011 uart0: serial@11002000 { 1012 compatible = "mediatek,mt8183-uart", 1013 "mediatek,mt6577-uart"; 1014 reg = <0 0x11002000 0 0x1000>; 1015 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 1016 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 1017 clock-names = "baud", "bus"; 1018 status = "disabled"; 1019 }; 1020 1021 uart1: serial@11003000 { 1022 compatible = "mediatek,mt8183-uart", 1023 "mediatek,mt6577-uart"; 1024 reg = <0 0x11003000 0 0x1000>; 1025 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 1026 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 1027 clock-names = "baud", "bus"; 1028 status = "disabled"; 1029 }; 1030 1031 uart2: serial@11004000 { 1032 compatible = "mediatek,mt8183-uart", 1033 "mediatek,mt6577-uart"; 1034 reg = <0 0x11004000 0 0x1000>; 1035 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1036 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1037 clock-names = "baud", "bus"; 1038 status = "disabled"; 1039 }; 1040 1041 i2c6: i2c@11005000 { 1042 compatible = "mediatek,mt8183-i2c"; 1043 reg = <0 0x11005000 0 0x1000>, 1044 <0 0x11000600 0 0x80>; 1045 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1046 clocks = <&infracfg CLK_INFRA_I2C6>, 1047 <&infracfg CLK_INFRA_AP_DMA>; 1048 clock-names = "main", "dma"; 1049 clock-div = <1>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 i2c0: i2c@11007000 { 1056 compatible = "mediatek,mt8183-i2c"; 1057 reg = <0 0x11007000 0 0x1000>, 1058 <0 0x11000080 0 0x80>; 1059 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1060 clocks = <&infracfg CLK_INFRA_I2C0>, 1061 <&infracfg CLK_INFRA_AP_DMA>; 1062 clock-names = "main", "dma"; 1063 clock-div = <1>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c4: i2c@11008000 { 1070 compatible = "mediatek,mt8183-i2c"; 1071 reg = <0 0x11008000 0 0x1000>, 1072 <0 0x11000100 0 0x80>; 1073 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1074 clocks = <&infracfg CLK_INFRA_I2C1>, 1075 <&infracfg CLK_INFRA_AP_DMA>, 1076 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1077 clock-names = "main", "dma","arb"; 1078 clock-div = <1>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 1084 i2c2: i2c@11009000 { 1085 compatible = "mediatek,mt8183-i2c"; 1086 reg = <0 0x11009000 0 0x1000>, 1087 <0 0x11000280 0 0x80>; 1088 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1089 clocks = <&infracfg CLK_INFRA_I2C2>, 1090 <&infracfg CLK_INFRA_AP_DMA>, 1091 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1092 clock-names = "main", "dma", "arb"; 1093 clock-div = <1>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 spi0: spi@1100a000 { 1100 compatible = "mediatek,mt8183-spi"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 reg = <0 0x1100a000 0 0x1000>; 1104 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1105 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1106 <&topckgen CLK_TOP_MUX_SPI>, 1107 <&infracfg CLK_INFRA_SPI0>; 1108 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1109 status = "disabled"; 1110 }; 1111 1112 svs: svs@1100b000 { 1113 compatible = "mediatek,mt8183-svs"; 1114 reg = <0 0x1100b000 0 0x1000>; 1115 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 1116 clocks = <&infracfg CLK_INFRA_THERM>; 1117 clock-names = "main"; 1118 nvmem-cells = <&svs_calibration>, 1119 <&thermal_calibration>; 1120 nvmem-cell-names = "svs-calibration-data", 1121 "t-calibration-data"; 1122 }; 1123 1124 thermal: thermal@1100b000 { 1125 #thermal-sensor-cells = <1>; 1126 compatible = "mediatek,mt8183-thermal"; 1127 reg = <0 0x1100b000 0 0x1000>; 1128 clocks = <&infracfg CLK_INFRA_THERM>, 1129 <&infracfg CLK_INFRA_AUXADC>; 1130 clock-names = "therm", "auxadc"; 1131 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1132 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1133 mediatek,auxadc = <&auxadc>; 1134 mediatek,apmixedsys = <&apmixedsys>; 1135 nvmem-cells = <&thermal_calibration>; 1136 nvmem-cell-names = "calibration-data"; 1137 }; 1138 1139 thermal_zones: thermal-zones { 1140 cpu_thermal: cpu-thermal { 1141 polling-delay-passive = <100>; 1142 polling-delay = <500>; 1143 thermal-sensors = <&thermal 0>; 1144 sustainable-power = <5000>; 1145 1146 trips { 1147 threshold: trip-point0 { 1148 temperature = <68000>; 1149 hysteresis = <2000>; 1150 type = "passive"; 1151 }; 1152 1153 target: trip-point1 { 1154 temperature = <80000>; 1155 hysteresis = <2000>; 1156 type = "passive"; 1157 }; 1158 1159 cpu_crit: cpu-crit { 1160 temperature = <115000>; 1161 hysteresis = <2000>; 1162 type = "critical"; 1163 }; 1164 }; 1165 1166 cooling-maps { 1167 map0 { 1168 trip = <&target>; 1169 cooling-device = <&cpu0 1170 THERMAL_NO_LIMIT 1171 THERMAL_NO_LIMIT>, 1172 <&cpu1 1173 THERMAL_NO_LIMIT 1174 THERMAL_NO_LIMIT>, 1175 <&cpu2 1176 THERMAL_NO_LIMIT 1177 THERMAL_NO_LIMIT>, 1178 <&cpu3 1179 THERMAL_NO_LIMIT 1180 THERMAL_NO_LIMIT>; 1181 contribution = <3072>; 1182 }; 1183 map1 { 1184 trip = <&target>; 1185 cooling-device = <&cpu4 1186 THERMAL_NO_LIMIT 1187 THERMAL_NO_LIMIT>, 1188 <&cpu5 1189 THERMAL_NO_LIMIT 1190 THERMAL_NO_LIMIT>, 1191 <&cpu6 1192 THERMAL_NO_LIMIT 1193 THERMAL_NO_LIMIT>, 1194 <&cpu7 1195 THERMAL_NO_LIMIT 1196 THERMAL_NO_LIMIT>; 1197 contribution = <1024>; 1198 }; 1199 }; 1200 }; 1201 1202 /* The tzts1 ~ tzts6 don't need to polling */ 1203 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 1204 1205 tzts1: tzts1 { 1206 polling-delay-passive = <0>; 1207 polling-delay = <0>; 1208 thermal-sensors = <&thermal 1>; 1209 sustainable-power = <5000>; 1210 trips {}; 1211 cooling-maps {}; 1212 }; 1213 1214 tzts2: tzts2 { 1215 polling-delay-passive = <0>; 1216 polling-delay = <0>; 1217 thermal-sensors = <&thermal 2>; 1218 sustainable-power = <5000>; 1219 trips {}; 1220 cooling-maps {}; 1221 }; 1222 1223 tzts3: tzts3 { 1224 polling-delay-passive = <0>; 1225 polling-delay = <0>; 1226 thermal-sensors = <&thermal 3>; 1227 sustainable-power = <5000>; 1228 trips {}; 1229 cooling-maps {}; 1230 }; 1231 1232 tzts4: tzts4 { 1233 polling-delay-passive = <0>; 1234 polling-delay = <0>; 1235 thermal-sensors = <&thermal 4>; 1236 sustainable-power = <5000>; 1237 trips {}; 1238 cooling-maps {}; 1239 }; 1240 1241 tzts5: tzts5 { 1242 polling-delay-passive = <0>; 1243 polling-delay = <0>; 1244 thermal-sensors = <&thermal 5>; 1245 sustainable-power = <5000>; 1246 trips {}; 1247 cooling-maps {}; 1248 }; 1249 1250 tztsABB: tztsABB { 1251 polling-delay-passive = <0>; 1252 polling-delay = <0>; 1253 thermal-sensors = <&thermal 6>; 1254 sustainable-power = <5000>; 1255 trips {}; 1256 cooling-maps {}; 1257 }; 1258 }; 1259 1260 pwm0: pwm@1100e000 { 1261 compatible = "mediatek,mt8183-disp-pwm"; 1262 reg = <0 0x1100e000 0 0x1000>; 1263 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1264 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1265 #pwm-cells = <2>; 1266 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1267 <&infracfg CLK_INFRA_DISP_PWM>; 1268 clock-names = "main", "mm"; 1269 }; 1270 1271 pwm1: pwm@11006000 { 1272 compatible = "mediatek,mt8183-pwm"; 1273 reg = <0 0x11006000 0 0x1000>; 1274 #pwm-cells = <2>; 1275 clocks = <&infracfg CLK_INFRA_PWM>, 1276 <&infracfg CLK_INFRA_PWM_HCLK>, 1277 <&infracfg CLK_INFRA_PWM1>, 1278 <&infracfg CLK_INFRA_PWM2>, 1279 <&infracfg CLK_INFRA_PWM3>, 1280 <&infracfg CLK_INFRA_PWM4>; 1281 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1282 "pwm4"; 1283 }; 1284 1285 i2c3: i2c@1100f000 { 1286 compatible = "mediatek,mt8183-i2c"; 1287 reg = <0 0x1100f000 0 0x1000>, 1288 <0 0x11000400 0 0x80>; 1289 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1290 clocks = <&infracfg CLK_INFRA_I2C3>, 1291 <&infracfg CLK_INFRA_AP_DMA>; 1292 clock-names = "main", "dma"; 1293 clock-div = <1>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi1: spi@11010000 { 1300 compatible = "mediatek,mt8183-spi"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 reg = <0 0x11010000 0 0x1000>; 1304 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1305 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1306 <&topckgen CLK_TOP_MUX_SPI>, 1307 <&infracfg CLK_INFRA_SPI1>; 1308 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1309 status = "disabled"; 1310 }; 1311 1312 i2c1: i2c@11011000 { 1313 compatible = "mediatek,mt8183-i2c"; 1314 reg = <0 0x11011000 0 0x1000>, 1315 <0 0x11000480 0 0x80>; 1316 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1317 clocks = <&infracfg CLK_INFRA_I2C4>, 1318 <&infracfg CLK_INFRA_AP_DMA>; 1319 clock-names = "main", "dma"; 1320 clock-div = <1>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 status = "disabled"; 1324 }; 1325 1326 spi2: spi@11012000 { 1327 compatible = "mediatek,mt8183-spi"; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 reg = <0 0x11012000 0 0x1000>; 1331 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1332 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1333 <&topckgen CLK_TOP_MUX_SPI>, 1334 <&infracfg CLK_INFRA_SPI2>; 1335 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1336 status = "disabled"; 1337 }; 1338 1339 spi3: spi@11013000 { 1340 compatible = "mediatek,mt8183-spi"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 reg = <0 0x11013000 0 0x1000>; 1344 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1345 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1346 <&topckgen CLK_TOP_MUX_SPI>, 1347 <&infracfg CLK_INFRA_SPI3>; 1348 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1349 status = "disabled"; 1350 }; 1351 1352 i2c9: i2c@11014000 { 1353 compatible = "mediatek,mt8183-i2c"; 1354 reg = <0 0x11014000 0 0x1000>, 1355 <0 0x11000180 0 0x80>; 1356 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1357 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1358 <&infracfg CLK_INFRA_AP_DMA>, 1359 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1360 clock-names = "main", "dma", "arb"; 1361 clock-div = <1>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 i2c10: i2c@11015000 { 1368 compatible = "mediatek,mt8183-i2c"; 1369 reg = <0 0x11015000 0 0x1000>, 1370 <0 0x11000300 0 0x80>; 1371 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1372 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1373 <&infracfg CLK_INFRA_AP_DMA>, 1374 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1375 clock-names = "main", "dma", "arb"; 1376 clock-div = <1>; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 i2c5: i2c@11016000 { 1383 compatible = "mediatek,mt8183-i2c"; 1384 reg = <0 0x11016000 0 0x1000>, 1385 <0 0x11000500 0 0x80>; 1386 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1387 clocks = <&infracfg CLK_INFRA_I2C5>, 1388 <&infracfg CLK_INFRA_AP_DMA>, 1389 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1390 clock-names = "main", "dma", "arb"; 1391 clock-div = <1>; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 status = "disabled"; 1395 }; 1396 1397 i2c11: i2c@11017000 { 1398 compatible = "mediatek,mt8183-i2c"; 1399 reg = <0 0x11017000 0 0x1000>, 1400 <0 0x11000580 0 0x80>; 1401 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1402 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1403 <&infracfg CLK_INFRA_AP_DMA>, 1404 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1405 clock-names = "main", "dma", "arb"; 1406 clock-div = <1>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 spi4: spi@11018000 { 1413 compatible = "mediatek,mt8183-spi"; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 reg = <0 0x11018000 0 0x1000>; 1417 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1418 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1419 <&topckgen CLK_TOP_MUX_SPI>, 1420 <&infracfg CLK_INFRA_SPI4>; 1421 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1422 status = "disabled"; 1423 }; 1424 1425 spi5: spi@11019000 { 1426 compatible = "mediatek,mt8183-spi"; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 reg = <0 0x11019000 0 0x1000>; 1430 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1431 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1432 <&topckgen CLK_TOP_MUX_SPI>, 1433 <&infracfg CLK_INFRA_SPI5>; 1434 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1435 status = "disabled"; 1436 }; 1437 1438 i2c7: i2c@1101a000 { 1439 compatible = "mediatek,mt8183-i2c"; 1440 reg = <0 0x1101a000 0 0x1000>, 1441 <0 0x11000680 0 0x80>; 1442 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1443 clocks = <&infracfg CLK_INFRA_I2C7>, 1444 <&infracfg CLK_INFRA_AP_DMA>; 1445 clock-names = "main", "dma"; 1446 clock-div = <1>; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 i2c8: i2c@1101b000 { 1453 compatible = "mediatek,mt8183-i2c"; 1454 reg = <0 0x1101b000 0 0x1000>, 1455 <0 0x11000700 0 0x80>; 1456 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1457 clocks = <&infracfg CLK_INFRA_I2C8>, 1458 <&infracfg CLK_INFRA_AP_DMA>; 1459 clock-names = "main", "dma"; 1460 clock-div = <1>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 ssusb: usb@11201000 { 1467 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; 1468 reg = <0 0x11201000 0 0x2e00>, 1469 <0 0x11203e00 0 0x0100>; 1470 reg-names = "mac", "ippc"; 1471 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1472 phys = <&u2port0 PHY_TYPE_USB2>, 1473 <&u3port0 PHY_TYPE_USB3>; 1474 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1475 <&infracfg CLK_INFRA_USB>; 1476 clock-names = "sys_ck", "ref_ck"; 1477 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1478 #address-cells = <2>; 1479 #size-cells = <2>; 1480 ranges; 1481 status = "disabled"; 1482 1483 usb_host: usb@11200000 { 1484 compatible = "mediatek,mt8183-xhci", 1485 "mediatek,mtk-xhci"; 1486 reg = <0 0x11200000 0 0x1000>; 1487 reg-names = "mac"; 1488 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1489 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1490 <&infracfg CLK_INFRA_USB>; 1491 clock-names = "sys_ck", "ref_ck"; 1492 status = "disabled"; 1493 }; 1494 }; 1495 1496 audiosys: audio-controller@11220000 { 1497 compatible = "mediatek,mt8183-audiosys", "syscon"; 1498 reg = <0 0x11220000 0 0x1000>; 1499 #clock-cells = <1>; 1500 afe: mt8183-afe-pcm { 1501 compatible = "mediatek,mt8183-audio"; 1502 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1503 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1504 reset-names = "audiosys"; 1505 power-domains = 1506 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1507 clocks = <&audiosys CLK_AUDIO_AFE>, 1508 <&audiosys CLK_AUDIO_DAC>, 1509 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1510 <&audiosys CLK_AUDIO_ADC>, 1511 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1512 <&audiosys CLK_AUDIO_22M>, 1513 <&audiosys CLK_AUDIO_24M>, 1514 <&audiosys CLK_AUDIO_APLL_TUNER>, 1515 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1516 <&audiosys CLK_AUDIO_I2S1>, 1517 <&audiosys CLK_AUDIO_I2S2>, 1518 <&audiosys CLK_AUDIO_I2S3>, 1519 <&audiosys CLK_AUDIO_I2S4>, 1520 <&audiosys CLK_AUDIO_TDM>, 1521 <&audiosys CLK_AUDIO_TML>, 1522 <&infracfg CLK_INFRA_AUDIO>, 1523 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1524 <&topckgen CLK_TOP_MUX_AUDIO>, 1525 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1526 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1527 <&topckgen CLK_TOP_MUX_AUD_1>, 1528 <&topckgen CLK_TOP_APLL1_CK>, 1529 <&topckgen CLK_TOP_MUX_AUD_2>, 1530 <&topckgen CLK_TOP_APLL2_CK>, 1531 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1532 <&topckgen CLK_TOP_APLL1_D8>, 1533 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1534 <&topckgen CLK_TOP_APLL2_D8>, 1535 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1536 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1537 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1538 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1539 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1540 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1541 <&topckgen CLK_TOP_APLL12_DIV0>, 1542 <&topckgen CLK_TOP_APLL12_DIV1>, 1543 <&topckgen CLK_TOP_APLL12_DIV2>, 1544 <&topckgen CLK_TOP_APLL12_DIV3>, 1545 <&topckgen CLK_TOP_APLL12_DIV4>, 1546 <&topckgen CLK_TOP_APLL12_DIVB>, 1547 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1548 <&clk26m>; 1549 clock-names = "aud_afe_clk", 1550 "aud_dac_clk", 1551 "aud_dac_predis_clk", 1552 "aud_adc_clk", 1553 "aud_adc_adda6_clk", 1554 "aud_apll22m_clk", 1555 "aud_apll24m_clk", 1556 "aud_apll1_tuner_clk", 1557 "aud_apll2_tuner_clk", 1558 "aud_i2s1_bclk_sw", 1559 "aud_i2s2_bclk_sw", 1560 "aud_i2s3_bclk_sw", 1561 "aud_i2s4_bclk_sw", 1562 "aud_tdm_clk", 1563 "aud_tml_clk", 1564 "aud_infra_clk", 1565 "mtkaif_26m_clk", 1566 "top_mux_audio", 1567 "top_mux_aud_intbus", 1568 "top_syspll_d2_d4", 1569 "top_mux_aud_1", 1570 "top_apll1_ck", 1571 "top_mux_aud_2", 1572 "top_apll2_ck", 1573 "top_mux_aud_eng1", 1574 "top_apll1_d8", 1575 "top_mux_aud_eng2", 1576 "top_apll2_d8", 1577 "top_i2s0_m_sel", 1578 "top_i2s1_m_sel", 1579 "top_i2s2_m_sel", 1580 "top_i2s3_m_sel", 1581 "top_i2s4_m_sel", 1582 "top_i2s5_m_sel", 1583 "top_apll12_div0", 1584 "top_apll12_div1", 1585 "top_apll12_div2", 1586 "top_apll12_div3", 1587 "top_apll12_div4", 1588 "top_apll12_divb", 1589 /*"top_apll12_div5",*/ 1590 "top_clk26m_clk"; 1591 }; 1592 }; 1593 1594 mmc0: mmc@11230000 { 1595 compatible = "mediatek,mt8183-mmc"; 1596 reg = <0 0x11230000 0 0x1000>, 1597 <0 0x11f50000 0 0x1000>; 1598 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1599 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1600 <&infracfg CLK_INFRA_MSDC0>, 1601 <&infracfg CLK_INFRA_MSDC0_SCK>; 1602 clock-names = "source", "hclk", "source_cg"; 1603 status = "disabled"; 1604 }; 1605 1606 mmc1: mmc@11240000 { 1607 compatible = "mediatek,mt8183-mmc"; 1608 reg = <0 0x11240000 0 0x1000>, 1609 <0 0x11e10000 0 0x1000>; 1610 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1611 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1612 <&infracfg CLK_INFRA_MSDC1>, 1613 <&infracfg CLK_INFRA_MSDC1_SCK>; 1614 clock-names = "source", "hclk", "source_cg"; 1615 status = "disabled"; 1616 }; 1617 1618 mipi_tx0: dsi-phy@11e50000 { 1619 compatible = "mediatek,mt8183-mipi-tx"; 1620 reg = <0 0x11e50000 0 0x1000>; 1621 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1622 #clock-cells = <0>; 1623 #phy-cells = <0>; 1624 clock-output-names = "mipi_tx0_pll"; 1625 nvmem-cells = <&mipi_tx_calibration>; 1626 nvmem-cell-names = "calibration-data"; 1627 }; 1628 1629 efuse: efuse@11f10000 { 1630 compatible = "mediatek,mt8183-efuse", 1631 "mediatek,efuse"; 1632 reg = <0 0x11f10000 0 0x1000>; 1633 #address-cells = <1>; 1634 #size-cells = <1>; 1635 thermal_calibration: calib@180 { 1636 reg = <0x180 0xc>; 1637 }; 1638 1639 mipi_tx_calibration: calib@190 { 1640 reg = <0x190 0xc>; 1641 }; 1642 1643 svs_calibration: calib@580 { 1644 reg = <0x580 0x64>; 1645 }; 1646 }; 1647 1648 u3phy: t-phy@11f40000 { 1649 compatible = "mediatek,mt8183-tphy", 1650 "mediatek,generic-tphy-v2"; 1651 #address-cells = <1>; 1652 #size-cells = <1>; 1653 ranges = <0 0 0x11f40000 0x1000>; 1654 status = "okay"; 1655 1656 u2port0: usb-phy@0 { 1657 reg = <0x0 0x700>; 1658 clocks = <&clk26m>; 1659 clock-names = "ref"; 1660 #phy-cells = <1>; 1661 mediatek,discth = <15>; 1662 status = "okay"; 1663 }; 1664 1665 u3port0: usb-phy@700 { 1666 reg = <0x0700 0x900>; 1667 clocks = <&clk26m>; 1668 clock-names = "ref"; 1669 #phy-cells = <1>; 1670 status = "okay"; 1671 }; 1672 }; 1673 1674 mfgcfg: syscon@13000000 { 1675 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1676 reg = <0 0x13000000 0 0x1000>; 1677 #clock-cells = <1>; 1678 }; 1679 1680 gpu: gpu@13040000 { 1681 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; 1682 reg = <0 0x13040000 0 0x4000>; 1683 interrupts = 1684 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1685 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1686 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1687 interrupt-names = "job", "mmu", "gpu"; 1688 1689 clocks = <&mfgcfg CLK_MFG_BG3D>; 1690 1691 power-domains = 1692 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1693 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1694 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1695 power-domain-names = "core0", "core1", "core2"; 1696 1697 operating-points-v2 = <&gpu_opp_table>; 1698 }; 1699 1700 mmsys: syscon@14000000 { 1701 compatible = "mediatek,mt8183-mmsys", "syscon"; 1702 reg = <0 0x14000000 0 0x1000>; 1703 #clock-cells = <1>; 1704 #reset-cells = <1>; 1705 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1706 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1707 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1708 }; 1709 1710 mdp3-rdma0@14001000 { 1711 compatible = "mediatek,mt8183-mdp3-rdma"; 1712 reg = <0 0x14001000 0 0x1000>; 1713 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1714 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1715 <CMDQ_EVENT_MDP_RDMA0_EOF>; 1716 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1717 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1718 <&mmsys CLK_MM_MDP_RSZ1>; 1719 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1720 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, 1721 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; 1722 }; 1723 1724 mdp3-rsz0@14003000 { 1725 compatible = "mediatek,mt8183-mdp3-rsz"; 1726 reg = <0 0x14003000 0 0x1000>; 1727 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; 1728 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, 1729 <CMDQ_EVENT_MDP_RSZ0_EOF>; 1730 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1731 }; 1732 1733 mdp3-rsz1@14004000 { 1734 compatible = "mediatek,mt8183-mdp3-rsz"; 1735 reg = <0 0x14004000 0 0x1000>; 1736 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; 1737 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, 1738 <CMDQ_EVENT_MDP_RSZ1_EOF>; 1739 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1740 }; 1741 1742 mdp3-wrot0@14005000 { 1743 compatible = "mediatek,mt8183-mdp3-wrot"; 1744 reg = <0 0x14005000 0 0x1000>; 1745 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1746 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 1747 <CMDQ_EVENT_MDP_WROT0_EOF>; 1748 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1749 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1750 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1751 }; 1752 1753 mdp3-wdma@14006000 { 1754 compatible = "mediatek,mt8183-mdp3-wdma"; 1755 reg = <0 0x14006000 0 0x1000>; 1756 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1757 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, 1758 <CMDQ_EVENT_MDP_WDMA0_EOF>; 1759 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1760 clocks = <&mmsys CLK_MM_MDP_WDMA0>; 1761 iommus = <&iommu M4U_PORT_MDP_WDMA0>; 1762 }; 1763 1764 ovl0: ovl@14008000 { 1765 compatible = "mediatek,mt8183-disp-ovl"; 1766 reg = <0 0x14008000 0 0x1000>; 1767 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1768 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1769 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1770 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1771 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1772 }; 1773 1774 ovl_2l0: ovl@14009000 { 1775 compatible = "mediatek,mt8183-disp-ovl-2l"; 1776 reg = <0 0x14009000 0 0x1000>; 1777 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1778 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1779 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1780 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1781 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1782 }; 1783 1784 ovl_2l1: ovl@1400a000 { 1785 compatible = "mediatek,mt8183-disp-ovl-2l"; 1786 reg = <0 0x1400a000 0 0x1000>; 1787 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1788 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1789 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1790 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1791 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1792 }; 1793 1794 rdma0: rdma@1400b000 { 1795 compatible = "mediatek,mt8183-disp-rdma"; 1796 reg = <0 0x1400b000 0 0x1000>; 1797 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1798 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1799 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1800 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1801 mediatek,rdma-fifo-size = <5120>; 1802 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1803 }; 1804 1805 rdma1: rdma@1400c000 { 1806 compatible = "mediatek,mt8183-disp-rdma"; 1807 reg = <0 0x1400c000 0 0x1000>; 1808 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1809 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1810 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1811 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1812 mediatek,rdma-fifo-size = <2048>; 1813 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1814 }; 1815 1816 color0: color@1400e000 { 1817 compatible = "mediatek,mt8183-disp-color", 1818 "mediatek,mt8173-disp-color"; 1819 reg = <0 0x1400e000 0 0x1000>; 1820 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1821 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1822 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1823 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1824 }; 1825 1826 ccorr0: ccorr@1400f000 { 1827 compatible = "mediatek,mt8183-disp-ccorr"; 1828 reg = <0 0x1400f000 0 0x1000>; 1829 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1830 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1831 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1832 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1833 }; 1834 1835 aal0: aal@14010000 { 1836 compatible = "mediatek,mt8183-disp-aal"; 1837 reg = <0 0x14010000 0 0x1000>; 1838 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1839 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1840 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1841 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1842 }; 1843 1844 gamma0: gamma@14011000 { 1845 compatible = "mediatek,mt8183-disp-gamma"; 1846 reg = <0 0x14011000 0 0x1000>; 1847 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1848 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1849 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1850 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1851 }; 1852 1853 dither0: dither@14012000 { 1854 compatible = "mediatek,mt8183-disp-dither"; 1855 reg = <0 0x14012000 0 0x1000>; 1856 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1857 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1858 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1859 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1860 }; 1861 1862 dsi0: dsi@14014000 { 1863 compatible = "mediatek,mt8183-dsi"; 1864 reg = <0 0x14014000 0 0x1000>; 1865 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1866 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1867 clocks = <&mmsys CLK_MM_DSI0_MM>, 1868 <&mmsys CLK_MM_DSI0_IF>, 1869 <&mipi_tx0>; 1870 clock-names = "engine", "digital", "hs"; 1871 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 1872 phys = <&mipi_tx0>; 1873 phy-names = "dphy"; 1874 }; 1875 1876 mutex: mutex@14016000 { 1877 compatible = "mediatek,mt8183-disp-mutex"; 1878 reg = <0 0x14016000 0 0x1000>; 1879 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1880 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1881 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1882 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1883 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1884 }; 1885 1886 larb0: larb@14017000 { 1887 compatible = "mediatek,mt8183-smi-larb"; 1888 reg = <0 0x14017000 0 0x1000>; 1889 mediatek,smi = <&smi_common>; 1890 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1891 <&mmsys CLK_MM_SMI_LARB0>; 1892 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1893 clock-names = "apb", "smi"; 1894 }; 1895 1896 smi_common: smi@14019000 { 1897 compatible = "mediatek,mt8183-smi-common"; 1898 reg = <0 0x14019000 0 0x1000>; 1899 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1900 <&mmsys CLK_MM_SMI_COMMON>, 1901 <&mmsys CLK_MM_GALS_COMM0>, 1902 <&mmsys CLK_MM_GALS_COMM1>; 1903 clock-names = "apb", "smi", "gals0", "gals1"; 1904 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1905 }; 1906 1907 mdp3-ccorr@1401c000 { 1908 compatible = "mediatek,mt8183-mdp3-ccorr"; 1909 reg = <0 0x1401c000 0 0x1000>; 1910 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; 1911 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, 1912 <CMDQ_EVENT_MDP_CCORR_EOF>; 1913 clocks = <&mmsys CLK_MM_MDP_CCORR>; 1914 }; 1915 1916 imgsys: syscon@15020000 { 1917 compatible = "mediatek,mt8183-imgsys", "syscon"; 1918 reg = <0 0x15020000 0 0x1000>; 1919 #clock-cells = <1>; 1920 }; 1921 1922 larb5: larb@15021000 { 1923 compatible = "mediatek,mt8183-smi-larb"; 1924 reg = <0 0x15021000 0 0x1000>; 1925 mediatek,smi = <&smi_common>; 1926 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1927 <&mmsys CLK_MM_GALS_IMG2MM>; 1928 clock-names = "apb", "smi", "gals"; 1929 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1930 }; 1931 1932 larb2: larb@1502f000 { 1933 compatible = "mediatek,mt8183-smi-larb"; 1934 reg = <0 0x1502f000 0 0x1000>; 1935 mediatek,smi = <&smi_common>; 1936 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1937 <&mmsys CLK_MM_GALS_IPU2MM>; 1938 clock-names = "apb", "smi", "gals"; 1939 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1940 }; 1941 1942 vdecsys: syscon@16000000 { 1943 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1944 reg = <0 0x16000000 0 0x1000>; 1945 #clock-cells = <1>; 1946 }; 1947 1948 larb1: larb@16010000 { 1949 compatible = "mediatek,mt8183-smi-larb"; 1950 reg = <0 0x16010000 0 0x1000>; 1951 mediatek,smi = <&smi_common>; 1952 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1953 clock-names = "apb", "smi"; 1954 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1955 }; 1956 1957 vencsys: syscon@17000000 { 1958 compatible = "mediatek,mt8183-vencsys", "syscon"; 1959 reg = <0 0x17000000 0 0x1000>; 1960 #clock-cells = <1>; 1961 }; 1962 1963 larb4: larb@17010000 { 1964 compatible = "mediatek,mt8183-smi-larb"; 1965 reg = <0 0x17010000 0 0x1000>; 1966 mediatek,smi = <&smi_common>; 1967 clocks = <&vencsys CLK_VENC_LARB>, 1968 <&vencsys CLK_VENC_LARB>; 1969 clock-names = "apb", "smi"; 1970 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1971 }; 1972 1973 venc_jpg: venc_jpg@17030000 { 1974 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 1975 reg = <0 0x17030000 0 0x1000>; 1976 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 1977 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 1978 <&iommu M4U_PORT_JPGENC_BSDMA>; 1979 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1980 clocks = <&vencsys CLK_VENC_JPGENC>; 1981 clock-names = "jpgenc"; 1982 }; 1983 1984 ipu_conn: syscon@19000000 { 1985 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1986 reg = <0 0x19000000 0 0x1000>; 1987 #clock-cells = <1>; 1988 }; 1989 1990 ipu_adl: syscon@19010000 { 1991 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1992 reg = <0 0x19010000 0 0x1000>; 1993 #clock-cells = <1>; 1994 }; 1995 1996 ipu_core0: syscon@19180000 { 1997 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1998 reg = <0 0x19180000 0 0x1000>; 1999 #clock-cells = <1>; 2000 }; 2001 2002 ipu_core1: syscon@19280000 { 2003 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 2004 reg = <0 0x19280000 0 0x1000>; 2005 #clock-cells = <1>; 2006 }; 2007 2008 camsys: syscon@1a000000 { 2009 compatible = "mediatek,mt8183-camsys", "syscon"; 2010 reg = <0 0x1a000000 0 0x1000>; 2011 #clock-cells = <1>; 2012 }; 2013 2014 larb6: larb@1a001000 { 2015 compatible = "mediatek,mt8183-smi-larb"; 2016 reg = <0 0x1a001000 0 0x1000>; 2017 mediatek,smi = <&smi_common>; 2018 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 2019 <&mmsys CLK_MM_GALS_CAM2MM>; 2020 clock-names = "apb", "smi", "gals"; 2021 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2022 }; 2023 2024 larb3: larb@1a002000 { 2025 compatible = "mediatek,mt8183-smi-larb"; 2026 reg = <0 0x1a002000 0 0x1000>; 2027 mediatek,smi = <&smi_common>; 2028 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 2029 <&mmsys CLK_MM_GALS_IPU12MM>; 2030 clock-names = "apb", "smi", "gals"; 2031 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2032 }; 2033 }; 2034}; 2035