1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 compatible = "mediatek,mt8183"; 14 interrupt-parent = <&sysirq>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 core2 { 31 cpu = <&cpu2>; 32 }; 33 core3 { 34 cpu = <&cpu3>; 35 }; 36 }; 37 38 cluster1 { 39 core0 { 40 cpu = <&cpu4>; 41 }; 42 core1 { 43 cpu = <&cpu5>; 44 }; 45 core2 { 46 cpu = <&cpu6>; 47 }; 48 core3 { 49 cpu = <&cpu7>; 50 }; 51 }; 52 }; 53 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x000>; 58 enable-method = "psci"; 59 capacity-dmips-mhz = <741>; 60 }; 61 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x001>; 66 enable-method = "psci"; 67 capacity-dmips-mhz = <741>; 68 }; 69 70 cpu2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x002>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <741>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x003>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <741>; 84 }; 85 86 cpu4: cpu@100 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a73"; 89 reg = <0x100>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <1024>; 92 }; 93 94 cpu5: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a73"; 97 reg = <0x101>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <1024>; 100 }; 101 102 cpu6: cpu@102 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a73"; 105 reg = <0x102>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1024>; 108 }; 109 110 cpu7: cpu@103 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a73"; 113 reg = <0x103>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <1024>; 116 }; 117 }; 118 119 pmu-a53 { 120 compatible = "arm,cortex-a53-pmu"; 121 interrupt-parent = <&gic>; 122 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 123 }; 124 125 pmu-a73 { 126 compatible = "arm,cortex-a73-pmu"; 127 interrupt-parent = <&gic>; 128 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 129 }; 130 131 psci { 132 compatible = "arm,psci-1.0"; 133 method = "smc"; 134 }; 135 136 clk26m: oscillator { 137 compatible = "fixed-clock"; 138 #clock-cells = <0>; 139 clock-frequency = <26000000>; 140 clock-output-names = "clk26m"; 141 }; 142 143 timer { 144 compatible = "arm,armv8-timer"; 145 interrupt-parent = <&gic>; 146 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 147 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 148 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 149 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 150 }; 151 152 soc { 153 #address-cells = <2>; 154 #size-cells = <2>; 155 compatible = "simple-bus"; 156 ranges; 157 158 gic: interrupt-controller@c000000 { 159 compatible = "arm,gic-v3"; 160 #interrupt-cells = <4>; 161 interrupt-parent = <&gic>; 162 interrupt-controller; 163 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 164 <0 0x0c100000 0 0x200000>, /* GICR */ 165 <0 0x0c400000 0 0x2000>, /* GICC */ 166 <0 0x0c410000 0 0x1000>, /* GICH */ 167 <0 0x0c420000 0 0x2000>; /* GICV */ 168 169 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 170 ppi-partitions { 171 ppi_cluster0: interrupt-partition-0 { 172 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 173 }; 174 ppi_cluster1: interrupt-partition-1 { 175 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 176 }; 177 }; 178 }; 179 180 mcucfg: syscon@c530000 { 181 compatible = "mediatek,mt8183-mcucfg", "syscon"; 182 reg = <0 0x0c530000 0 0x1000>; 183 #clock-cells = <1>; 184 }; 185 186 sysirq: interrupt-controller@c530a80 { 187 compatible = "mediatek,mt8183-sysirq", 188 "mediatek,mt6577-sysirq"; 189 interrupt-controller; 190 #interrupt-cells = <3>; 191 interrupt-parent = <&gic>; 192 reg = <0 0x0c530a80 0 0x50>; 193 }; 194 195 topckgen: syscon@10000000 { 196 compatible = "mediatek,mt8183-topckgen", "syscon"; 197 reg = <0 0x10000000 0 0x1000>; 198 #clock-cells = <1>; 199 }; 200 201 infracfg: syscon@10001000 { 202 compatible = "mediatek,mt8183-infracfg", "syscon"; 203 reg = <0 0x10001000 0 0x1000>; 204 #clock-cells = <1>; 205 }; 206 207 apmixedsys: syscon@1000c000 { 208 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 209 reg = <0 0x1000c000 0 0x1000>; 210 #clock-cells = <1>; 211 }; 212 213 pwrap: pwrap@1000d000 { 214 compatible = "mediatek,mt8183-pwrap"; 215 reg = <0 0x1000d000 0 0x1000>; 216 reg-names = "pwrap"; 217 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 219 <&infracfg CLK_INFRA_PMIC_AP>; 220 clock-names = "spi", "wrap"; 221 }; 222 223 uart0: serial@11002000 { 224 compatible = "mediatek,mt8183-uart", 225 "mediatek,mt6577-uart"; 226 reg = <0 0x11002000 0 0x1000>; 227 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 228 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 229 clock-names = "baud", "bus"; 230 status = "disabled"; 231 }; 232 233 uart1: serial@11003000 { 234 compatible = "mediatek,mt8183-uart", 235 "mediatek,mt6577-uart"; 236 reg = <0 0x11003000 0 0x1000>; 237 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 238 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 239 clock-names = "baud", "bus"; 240 status = "disabled"; 241 }; 242 243 uart2: serial@11004000 { 244 compatible = "mediatek,mt8183-uart", 245 "mediatek,mt6577-uart"; 246 reg = <0 0x11004000 0 0x1000>; 247 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 248 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 249 clock-names = "baud", "bus"; 250 status = "disabled"; 251 }; 252 253 audiosys: syscon@11220000 { 254 compatible = "mediatek,mt8183-audiosys", "syscon"; 255 reg = <0 0x11220000 0 0x1000>; 256 #clock-cells = <1>; 257 }; 258 259 mfgcfg: syscon@13000000 { 260 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 261 reg = <0 0x13000000 0 0x1000>; 262 #clock-cells = <1>; 263 }; 264 265 mmsys: syscon@14000000 { 266 compatible = "mediatek,mt8183-mmsys", "syscon"; 267 reg = <0 0x14000000 0 0x1000>; 268 #clock-cells = <1>; 269 }; 270 271 imgsys: syscon@15020000 { 272 compatible = "mediatek,mt8183-imgsys", "syscon"; 273 reg = <0 0x15020000 0 0x1000>; 274 #clock-cells = <1>; 275 }; 276 277 vdecsys: syscon@16000000 { 278 compatible = "mediatek,mt8183-vdecsys", "syscon"; 279 reg = <0 0x16000000 0 0x1000>; 280 #clock-cells = <1>; 281 }; 282 283 vencsys: syscon@17000000 { 284 compatible = "mediatek,mt8183-vencsys", "syscon"; 285 reg = <0 0x17000000 0 0x1000>; 286 #clock-cells = <1>; 287 }; 288 289 ipu_conn: syscon@19000000 { 290 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 291 reg = <0 0x19000000 0 0x1000>; 292 #clock-cells = <1>; 293 }; 294 295 ipu_adl: syscon@19010000 { 296 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 297 reg = <0 0x19010000 0 0x1000>; 298 #clock-cells = <1>; 299 }; 300 301 ipu_core0: syscon@19180000 { 302 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 303 reg = <0 0x19180000 0 0x1000>; 304 #clock-cells = <1>; 305 }; 306 307 ipu_core1: syscon@19280000 { 308 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 309 reg = <0 0x19280000 0 0x1000>; 310 #clock-cells = <1>; 311 }; 312 313 camsys: syscon@1a000000 { 314 compatible = "mediatek,mt8183-camsys", "syscon"; 315 reg = <0 0x1a000000 0 0x1000>; 316 #clock-cells = <1>; 317 }; 318 }; 319}; 320