1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include "mt8183-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt8183"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c7; 29 i2c8 = &i2c8; 30 i2c9 = &i2c9; 31 i2c10 = &i2c10; 32 i2c11 = &i2c11; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 core1 { 45 cpu = <&cpu1>; 46 }; 47 core2 { 48 cpu = <&cpu2>; 49 }; 50 core3 { 51 cpu = <&cpu3>; 52 }; 53 }; 54 55 cluster1 { 56 core0 { 57 cpu = <&cpu4>; 58 }; 59 core1 { 60 cpu = <&cpu5>; 61 }; 62 core2 { 63 cpu = <&cpu6>; 64 }; 65 core3 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x000>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <741>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 78 dynamic-power-coefficient = <84>; 79 }; 80 81 cpu1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x001>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <741>; 87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 88 dynamic-power-coefficient = <84>; 89 }; 90 91 cpu2: cpu@2 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x002>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <741>; 97 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 98 dynamic-power-coefficient = <84>; 99 }; 100 101 cpu3: cpu@3 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x003>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <741>; 107 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 108 dynamic-power-coefficient = <84>; 109 }; 110 111 cpu4: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a73"; 114 reg = <0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1024>; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 118 dynamic-power-coefficient = <211>; 119 }; 120 121 cpu5: cpu@101 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a73"; 124 reg = <0x101>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 128 dynamic-power-coefficient = <211>; 129 }; 130 131 cpu6: cpu@102 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a73"; 134 reg = <0x102>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 138 dynamic-power-coefficient = <211>; 139 }; 140 141 cpu7: cpu@103 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a73"; 144 reg = <0x103>; 145 enable-method = "psci"; 146 capacity-dmips-mhz = <1024>; 147 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 148 dynamic-power-coefficient = <211>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 CPU_SLEEP: cpu-sleep { 155 compatible = "arm,idle-state"; 156 local-timer-stop; 157 arm,psci-suspend-param = <0x00010001>; 158 entry-latency-us = <200>; 159 exit-latency-us = <200>; 160 min-residency-us = <800>; 161 }; 162 163 CLUSTER_SLEEP: cluster-sleep { 164 compatible = "arm,idle-state"; 165 local-timer-stop; 166 arm,psci-suspend-param = <0x01010001>; 167 entry-latency-us = <250>; 168 exit-latency-us = <400>; 169 min-residency-us = <1300>; 170 }; 171 }; 172 }; 173 174 pmu-a53 { 175 compatible = "arm,cortex-a53-pmu"; 176 interrupt-parent = <&gic>; 177 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 178 }; 179 180 pmu-a73 { 181 compatible = "arm,cortex-a73-pmu"; 182 interrupt-parent = <&gic>; 183 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 184 }; 185 186 psci { 187 compatible = "arm,psci-1.0"; 188 method = "smc"; 189 }; 190 191 clk26m: oscillator { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <26000000>; 195 clock-output-names = "clk26m"; 196 }; 197 198 timer { 199 compatible = "arm,armv8-timer"; 200 interrupt-parent = <&gic>; 201 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 202 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 203 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 204 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 205 }; 206 207 soc { 208 #address-cells = <2>; 209 #size-cells = <2>; 210 compatible = "simple-bus"; 211 ranges; 212 213 soc_data: soc_data@8000000 { 214 compatible = "mediatek,mt8183-efuse", 215 "mediatek,efuse"; 216 reg = <0 0x08000000 0 0x0010>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 status = "disabled"; 220 }; 221 222 gic: interrupt-controller@c000000 { 223 compatible = "arm,gic-v3"; 224 #interrupt-cells = <4>; 225 interrupt-parent = <&gic>; 226 interrupt-controller; 227 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 228 <0 0x0c100000 0 0x200000>, /* GICR */ 229 <0 0x0c400000 0 0x2000>, /* GICC */ 230 <0 0x0c410000 0 0x1000>, /* GICH */ 231 <0 0x0c420000 0 0x2000>; /* GICV */ 232 233 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 234 ppi-partitions { 235 ppi_cluster0: interrupt-partition-0 { 236 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 237 }; 238 ppi_cluster1: interrupt-partition-1 { 239 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 240 }; 241 }; 242 }; 243 244 mcucfg: syscon@c530000 { 245 compatible = "mediatek,mt8183-mcucfg", "syscon"; 246 reg = <0 0x0c530000 0 0x1000>; 247 #clock-cells = <1>; 248 }; 249 250 sysirq: interrupt-controller@c530a80 { 251 compatible = "mediatek,mt8183-sysirq", 252 "mediatek,mt6577-sysirq"; 253 interrupt-controller; 254 #interrupt-cells = <3>; 255 interrupt-parent = <&gic>; 256 reg = <0 0x0c530a80 0 0x50>; 257 }; 258 259 topckgen: syscon@10000000 { 260 compatible = "mediatek,mt8183-topckgen", "syscon"; 261 reg = <0 0x10000000 0 0x1000>; 262 #clock-cells = <1>; 263 }; 264 265 infracfg: syscon@10001000 { 266 compatible = "mediatek,mt8183-infracfg", "syscon"; 267 reg = <0 0x10001000 0 0x1000>; 268 #clock-cells = <1>; 269 #reset-cells = <1>; 270 }; 271 272 pio: pinctrl@10005000 { 273 compatible = "mediatek,mt8183-pinctrl"; 274 reg = <0 0x10005000 0 0x1000>, 275 <0 0x11f20000 0 0x1000>, 276 <0 0x11e80000 0 0x1000>, 277 <0 0x11e70000 0 0x1000>, 278 <0 0x11e90000 0 0x1000>, 279 <0 0x11d30000 0 0x1000>, 280 <0 0x11d20000 0 0x1000>, 281 <0 0x11c50000 0 0x1000>, 282 <0 0x11f30000 0 0x1000>, 283 <0 0x1000b000 0 0x1000>; 284 reg-names = "iocfg0", "iocfg1", "iocfg2", 285 "iocfg3", "iocfg4", "iocfg5", 286 "iocfg6", "iocfg7", "iocfg8", 287 "eint"; 288 gpio-controller; 289 #gpio-cells = <2>; 290 gpio-ranges = <&pio 0 0 192>; 291 interrupt-controller; 292 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 293 #interrupt-cells = <2>; 294 }; 295 296 watchdog: watchdog@10007000 { 297 compatible = "mediatek,mt8183-wdt", 298 "mediatek,mt6589-wdt"; 299 reg = <0 0x10007000 0 0x100>; 300 #reset-cells = <1>; 301 }; 302 303 apmixedsys: syscon@1000c000 { 304 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 305 reg = <0 0x1000c000 0 0x1000>; 306 #clock-cells = <1>; 307 }; 308 309 pwrap: pwrap@1000d000 { 310 compatible = "mediatek,mt8183-pwrap"; 311 reg = <0 0x1000d000 0 0x1000>; 312 reg-names = "pwrap"; 313 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 315 <&infracfg CLK_INFRA_PMIC_AP>; 316 clock-names = "spi", "wrap"; 317 }; 318 319 systimer: timer@10017000 { 320 compatible = "mediatek,mt8183-timer", 321 "mediatek,mt6765-timer"; 322 reg = <0 0x10017000 0 0x1000>; 323 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&topckgen CLK_TOP_CLK13M>; 325 clock-names = "clk13m"; 326 }; 327 328 gce: mailbox@10238000 { 329 compatible = "mediatek,mt8183-gce"; 330 reg = <0 0x10238000 0 0x4000>; 331 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 332 #mbox-cells = <3>; 333 clocks = <&infracfg CLK_INFRA_GCE>; 334 clock-names = "gce"; 335 }; 336 337 auxadc: auxadc@11001000 { 338 compatible = "mediatek,mt8183-auxadc", 339 "mediatek,mt8173-auxadc"; 340 reg = <0 0x11001000 0 0x1000>; 341 clocks = <&infracfg CLK_INFRA_AUXADC>; 342 clock-names = "main"; 343 #io-channel-cells = <1>; 344 status = "disabled"; 345 }; 346 347 uart0: serial@11002000 { 348 compatible = "mediatek,mt8183-uart", 349 "mediatek,mt6577-uart"; 350 reg = <0 0x11002000 0 0x1000>; 351 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 352 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 353 clock-names = "baud", "bus"; 354 status = "disabled"; 355 }; 356 357 uart1: serial@11003000 { 358 compatible = "mediatek,mt8183-uart", 359 "mediatek,mt6577-uart"; 360 reg = <0 0x11003000 0 0x1000>; 361 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 362 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 363 clock-names = "baud", "bus"; 364 status = "disabled"; 365 }; 366 367 uart2: serial@11004000 { 368 compatible = "mediatek,mt8183-uart", 369 "mediatek,mt6577-uart"; 370 reg = <0 0x11004000 0 0x1000>; 371 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 372 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 373 clock-names = "baud", "bus"; 374 status = "disabled"; 375 }; 376 377 i2c6: i2c@11005000 { 378 compatible = "mediatek,mt8183-i2c"; 379 reg = <0 0x11005000 0 0x1000>, 380 <0 0x11000600 0 0x80>; 381 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 382 clocks = <&infracfg CLK_INFRA_I2C6>, 383 <&infracfg CLK_INFRA_AP_DMA>; 384 clock-names = "main", "dma"; 385 clock-div = <1>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 status = "disabled"; 389 }; 390 391 i2c0: i2c@11007000 { 392 compatible = "mediatek,mt8183-i2c"; 393 reg = <0 0x11007000 0 0x1000>, 394 <0 0x11000080 0 0x80>; 395 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 396 clocks = <&infracfg CLK_INFRA_I2C0>, 397 <&infracfg CLK_INFRA_AP_DMA>; 398 clock-names = "main", "dma"; 399 clock-div = <1>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 i2c4: i2c@11008000 { 406 compatible = "mediatek,mt8183-i2c"; 407 reg = <0 0x11008000 0 0x1000>, 408 <0 0x11000100 0 0x80>; 409 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 410 clocks = <&infracfg CLK_INFRA_I2C1>, 411 <&infracfg CLK_INFRA_AP_DMA>, 412 <&infracfg CLK_INFRA_I2C1_ARBITER>; 413 clock-names = "main", "dma","arb"; 414 clock-div = <1>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 i2c2: i2c@11009000 { 421 compatible = "mediatek,mt8183-i2c"; 422 reg = <0 0x11009000 0 0x1000>, 423 <0 0x11000280 0 0x80>; 424 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 425 clocks = <&infracfg CLK_INFRA_I2C2>, 426 <&infracfg CLK_INFRA_AP_DMA>, 427 <&infracfg CLK_INFRA_I2C2_ARBITER>; 428 clock-names = "main", "dma", "arb"; 429 clock-div = <1>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 status = "disabled"; 433 }; 434 435 spi0: spi@1100a000 { 436 compatible = "mediatek,mt8183-spi"; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 reg = <0 0x1100a000 0 0x1000>; 440 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 441 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 442 <&topckgen CLK_TOP_MUX_SPI>, 443 <&infracfg CLK_INFRA_SPI0>; 444 clock-names = "parent-clk", "sel-clk", "spi-clk"; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@1100f000 { 449 compatible = "mediatek,mt8183-i2c"; 450 reg = <0 0x1100f000 0 0x1000>, 451 <0 0x11000400 0 0x80>; 452 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 453 clocks = <&infracfg CLK_INFRA_I2C3>, 454 <&infracfg CLK_INFRA_AP_DMA>; 455 clock-names = "main", "dma"; 456 clock-div = <1>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 spi1: spi@11010000 { 463 compatible = "mediatek,mt8183-spi"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 reg = <0 0x11010000 0 0x1000>; 467 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 468 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 469 <&topckgen CLK_TOP_MUX_SPI>, 470 <&infracfg CLK_INFRA_SPI1>; 471 clock-names = "parent-clk", "sel-clk", "spi-clk"; 472 status = "disabled"; 473 }; 474 475 i2c1: i2c@11011000 { 476 compatible = "mediatek,mt8183-i2c"; 477 reg = <0 0x11011000 0 0x1000>, 478 <0 0x11000480 0 0x80>; 479 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 480 clocks = <&infracfg CLK_INFRA_I2C4>, 481 <&infracfg CLK_INFRA_AP_DMA>; 482 clock-names = "main", "dma"; 483 clock-div = <1>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 spi2: spi@11012000 { 490 compatible = "mediatek,mt8183-spi"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0 0x11012000 0 0x1000>; 494 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 495 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 496 <&topckgen CLK_TOP_MUX_SPI>, 497 <&infracfg CLK_INFRA_SPI2>; 498 clock-names = "parent-clk", "sel-clk", "spi-clk"; 499 status = "disabled"; 500 }; 501 502 spi3: spi@11013000 { 503 compatible = "mediatek,mt8183-spi"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0 0x11013000 0 0x1000>; 507 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 508 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 509 <&topckgen CLK_TOP_MUX_SPI>, 510 <&infracfg CLK_INFRA_SPI3>; 511 clock-names = "parent-clk", "sel-clk", "spi-clk"; 512 status = "disabled"; 513 }; 514 515 i2c9: i2c@11014000 { 516 compatible = "mediatek,mt8183-i2c"; 517 reg = <0 0x11014000 0 0x1000>, 518 <0 0x11000180 0 0x80>; 519 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 520 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 521 <&infracfg CLK_INFRA_AP_DMA>, 522 <&infracfg CLK_INFRA_I2C1_ARBITER>; 523 clock-names = "main", "dma", "arb"; 524 clock-div = <1>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 status = "disabled"; 528 }; 529 530 i2c10: i2c@11015000 { 531 compatible = "mediatek,mt8183-i2c"; 532 reg = <0 0x11015000 0 0x1000>, 533 <0 0x11000300 0 0x80>; 534 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 535 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 536 <&infracfg CLK_INFRA_AP_DMA>, 537 <&infracfg CLK_INFRA_I2C2_ARBITER>; 538 clock-names = "main", "dma", "arb"; 539 clock-div = <1>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 status = "disabled"; 543 }; 544 545 i2c5: i2c@11016000 { 546 compatible = "mediatek,mt8183-i2c"; 547 reg = <0 0x11016000 0 0x1000>, 548 <0 0x11000500 0 0x80>; 549 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 550 clocks = <&infracfg CLK_INFRA_I2C5>, 551 <&infracfg CLK_INFRA_AP_DMA>, 552 <&infracfg CLK_INFRA_I2C5_ARBITER>; 553 clock-names = "main", "dma", "arb"; 554 clock-div = <1>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 i2c11: i2c@11017000 { 561 compatible = "mediatek,mt8183-i2c"; 562 reg = <0 0x11017000 0 0x1000>, 563 <0 0x11000580 0 0x80>; 564 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 565 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 566 <&infracfg CLK_INFRA_AP_DMA>, 567 <&infracfg CLK_INFRA_I2C5_ARBITER>; 568 clock-names = "main", "dma", "arb"; 569 clock-div = <1>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 status = "disabled"; 573 }; 574 575 spi4: spi@11018000 { 576 compatible = "mediatek,mt8183-spi"; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 reg = <0 0x11018000 0 0x1000>; 580 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 581 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 582 <&topckgen CLK_TOP_MUX_SPI>, 583 <&infracfg CLK_INFRA_SPI4>; 584 clock-names = "parent-clk", "sel-clk", "spi-clk"; 585 status = "disabled"; 586 }; 587 588 spi5: spi@11019000 { 589 compatible = "mediatek,mt8183-spi"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 reg = <0 0x11019000 0 0x1000>; 593 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 594 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 595 <&topckgen CLK_TOP_MUX_SPI>, 596 <&infracfg CLK_INFRA_SPI5>; 597 clock-names = "parent-clk", "sel-clk", "spi-clk"; 598 status = "disabled"; 599 }; 600 601 i2c7: i2c@1101a000 { 602 compatible = "mediatek,mt8183-i2c"; 603 reg = <0 0x1101a000 0 0x1000>, 604 <0 0x11000680 0 0x80>; 605 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 606 clocks = <&infracfg CLK_INFRA_I2C7>, 607 <&infracfg CLK_INFRA_AP_DMA>; 608 clock-names = "main", "dma"; 609 clock-div = <1>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 status = "disabled"; 613 }; 614 615 i2c8: i2c@1101b000 { 616 compatible = "mediatek,mt8183-i2c"; 617 reg = <0 0x1101b000 0 0x1000>, 618 <0 0x11000700 0 0x80>; 619 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 620 clocks = <&infracfg CLK_INFRA_I2C8>, 621 <&infracfg CLK_INFRA_AP_DMA>; 622 clock-names = "main", "dma"; 623 clock-div = <1>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 629 audiosys: syscon@11220000 { 630 compatible = "mediatek,mt8183-audiosys", "syscon"; 631 reg = <0 0x11220000 0 0x1000>; 632 #clock-cells = <1>; 633 }; 634 635 efuse: efuse@11f10000 { 636 compatible = "mediatek,mt8183-efuse", 637 "mediatek,efuse"; 638 reg = <0 0x11f10000 0 0x1000>; 639 }; 640 641 mfgcfg: syscon@13000000 { 642 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 643 reg = <0 0x13000000 0 0x1000>; 644 #clock-cells = <1>; 645 }; 646 647 mmsys: syscon@14000000 { 648 compatible = "mediatek,mt8183-mmsys", "syscon"; 649 reg = <0 0x14000000 0 0x1000>; 650 #clock-cells = <1>; 651 }; 652 653 imgsys: syscon@15020000 { 654 compatible = "mediatek,mt8183-imgsys", "syscon"; 655 reg = <0 0x15020000 0 0x1000>; 656 #clock-cells = <1>; 657 }; 658 659 vdecsys: syscon@16000000 { 660 compatible = "mediatek,mt8183-vdecsys", "syscon"; 661 reg = <0 0x16000000 0 0x1000>; 662 #clock-cells = <1>; 663 }; 664 665 vencsys: syscon@17000000 { 666 compatible = "mediatek,mt8183-vencsys", "syscon"; 667 reg = <0 0x17000000 0 0x1000>; 668 #clock-cells = <1>; 669 }; 670 671 ipu_conn: syscon@19000000 { 672 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 673 reg = <0 0x19000000 0 0x1000>; 674 #clock-cells = <1>; 675 }; 676 677 ipu_adl: syscon@19010000 { 678 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 679 reg = <0 0x19010000 0 0x1000>; 680 #clock-cells = <1>; 681 }; 682 683 ipu_core0: syscon@19180000 { 684 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 685 reg = <0 0x19180000 0 0x1000>; 686 #clock-cells = <1>; 687 }; 688 689 ipu_core1: syscon@19280000 { 690 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 691 reg = <0 0x19280000 0 0x1000>; 692 #clock-cells = <1>; 693 }; 694 695 camsys: syscon@1a000000 { 696 compatible = "mediatek,mt8183-camsys", "syscon"; 697 reg = <0 0x1a000000 0 0x1000>; 698 #clock-cells = <1>; 699 }; 700 }; 701}; 702