1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include "mt8183-pinfunc.h"
12
13/ {
14	compatible = "mediatek,mt8183";
15	interrupt-parent = <&sysirq>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu-map {
24			cluster0 {
25				core0 {
26					cpu = <&cpu0>;
27				};
28				core1 {
29					cpu = <&cpu1>;
30				};
31				core2 {
32					cpu = <&cpu2>;
33				};
34				core3 {
35					cpu = <&cpu3>;
36				};
37			};
38
39			cluster1 {
40				core0 {
41					cpu = <&cpu4>;
42				};
43				core1 {
44					cpu = <&cpu5>;
45				};
46				core2 {
47					cpu = <&cpu6>;
48				};
49				core3 {
50					cpu = <&cpu7>;
51				};
52			};
53		};
54
55		cpu0: cpu@0 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			reg = <0x000>;
59			enable-method = "psci";
60			capacity-dmips-mhz = <741>;
61		};
62
63		cpu1: cpu@1 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53";
66			reg = <0x001>;
67			enable-method = "psci";
68			capacity-dmips-mhz = <741>;
69		};
70
71		cpu2: cpu@2 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a53";
74			reg = <0x002>;
75			enable-method = "psci";
76			capacity-dmips-mhz = <741>;
77		};
78
79		cpu3: cpu@3 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a53";
82			reg = <0x003>;
83			enable-method = "psci";
84			capacity-dmips-mhz = <741>;
85		};
86
87		cpu4: cpu@100 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a73";
90			reg = <0x100>;
91			enable-method = "psci";
92			capacity-dmips-mhz = <1024>;
93		};
94
95		cpu5: cpu@101 {
96			device_type = "cpu";
97			compatible = "arm,cortex-a73";
98			reg = <0x101>;
99			enable-method = "psci";
100			capacity-dmips-mhz = <1024>;
101		};
102
103		cpu6: cpu@102 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a73";
106			reg = <0x102>;
107			enable-method = "psci";
108			capacity-dmips-mhz = <1024>;
109		};
110
111		cpu7: cpu@103 {
112			device_type = "cpu";
113			compatible = "arm,cortex-a73";
114			reg = <0x103>;
115			enable-method = "psci";
116			capacity-dmips-mhz = <1024>;
117		};
118	};
119
120	pmu-a53 {
121		compatible = "arm,cortex-a53-pmu";
122		interrupt-parent = <&gic>;
123		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
124	};
125
126	pmu-a73 {
127		compatible = "arm,cortex-a73-pmu";
128		interrupt-parent = <&gic>;
129		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
130	};
131
132	psci {
133		compatible      = "arm,psci-1.0";
134		method          = "smc";
135	};
136
137	clk26m: oscillator {
138		compatible = "fixed-clock";
139		#clock-cells = <0>;
140		clock-frequency = <26000000>;
141		clock-output-names = "clk26m";
142	};
143
144	timer {
145		compatible = "arm,armv8-timer";
146		interrupt-parent = <&gic>;
147		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
148			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
149			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
150			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
151	};
152
153	soc {
154		#address-cells = <2>;
155		#size-cells = <2>;
156		compatible = "simple-bus";
157		ranges;
158
159		soc_data: soc_data@8000000 {
160			compatible = "mediatek,mt8183-efuse",
161				     "mediatek,efuse";
162			reg = <0 0x08000000 0 0x0010>;
163			#address-cells = <1>;
164			#size-cells = <1>;
165			status = "disabled";
166		};
167
168		gic: interrupt-controller@c000000 {
169			compatible = "arm,gic-v3";
170			#interrupt-cells = <4>;
171			interrupt-parent = <&gic>;
172			interrupt-controller;
173			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
174			      <0 0x0c100000 0 0x200000>, /* GICR */
175			      <0 0x0c400000 0 0x2000>,   /* GICC */
176			      <0 0x0c410000 0 0x1000>,   /* GICH */
177			      <0 0x0c420000 0 0x2000>;   /* GICV */
178
179			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
180			ppi-partitions {
181				ppi_cluster0: interrupt-partition-0 {
182					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
183				};
184				ppi_cluster1: interrupt-partition-1 {
185					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
186				};
187			};
188		};
189
190		mcucfg: syscon@c530000 {
191			compatible = "mediatek,mt8183-mcucfg", "syscon";
192			reg = <0 0x0c530000 0 0x1000>;
193			#clock-cells = <1>;
194		};
195
196		sysirq: interrupt-controller@c530a80 {
197			compatible = "mediatek,mt8183-sysirq",
198				     "mediatek,mt6577-sysirq";
199			interrupt-controller;
200			#interrupt-cells = <3>;
201			interrupt-parent = <&gic>;
202			reg = <0 0x0c530a80 0 0x50>;
203		};
204
205		topckgen: syscon@10000000 {
206			compatible = "mediatek,mt8183-topckgen", "syscon";
207			reg = <0 0x10000000 0 0x1000>;
208			#clock-cells = <1>;
209		};
210
211		infracfg: syscon@10001000 {
212			compatible = "mediatek,mt8183-infracfg", "syscon";
213			reg = <0 0x10001000 0 0x1000>;
214			#clock-cells = <1>;
215		};
216
217		pio: pinctrl@10005000 {
218			compatible = "mediatek,mt8183-pinctrl";
219			reg = <0 0x10005000 0 0x1000>,
220			      <0 0x11f20000 0 0x1000>,
221			      <0 0x11e80000 0 0x1000>,
222			      <0 0x11e70000 0 0x1000>,
223			      <0 0x11e90000 0 0x1000>,
224			      <0 0x11d30000 0 0x1000>,
225			      <0 0x11d20000 0 0x1000>,
226			      <0 0x11c50000 0 0x1000>,
227			      <0 0x11f30000 0 0x1000>,
228			      <0 0x1000b000 0 0x1000>;
229			reg-names = "iocfg0", "iocfg1", "iocfg2",
230				    "iocfg3", "iocfg4", "iocfg5",
231				    "iocfg6", "iocfg7", "iocfg8",
232				    "eint";
233			gpio-controller;
234			#gpio-cells = <2>;
235			gpio-ranges = <&pio 0 0 192>;
236			interrupt-controller;
237			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
238			#interrupt-cells = <2>;
239		};
240
241		apmixedsys: syscon@1000c000 {
242			compatible = "mediatek,mt8183-apmixedsys", "syscon";
243			reg = <0 0x1000c000 0 0x1000>;
244			#clock-cells = <1>;
245		};
246
247		pwrap: pwrap@1000d000 {
248			compatible = "mediatek,mt8183-pwrap";
249			reg = <0 0x1000d000 0 0x1000>;
250			reg-names = "pwrap";
251			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
252			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
253				 <&infracfg CLK_INFRA_PMIC_AP>;
254			clock-names = "spi", "wrap";
255		};
256
257		auxadc: auxadc@11001000 {
258			compatible = "mediatek,mt8183-auxadc",
259				     "mediatek,mt8173-auxadc";
260			reg = <0 0x11001000 0 0x1000>;
261			clocks = <&infracfg CLK_INFRA_AUXADC>;
262			clock-names = "main";
263			#io-channel-cells = <1>;
264			status = "disabled";
265		};
266
267		uart0: serial@11002000 {
268			compatible = "mediatek,mt8183-uart",
269				     "mediatek,mt6577-uart";
270			reg = <0 0x11002000 0 0x1000>;
271			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
272			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
273			clock-names = "baud", "bus";
274			status = "disabled";
275		};
276
277		uart1: serial@11003000 {
278			compatible = "mediatek,mt8183-uart",
279				     "mediatek,mt6577-uart";
280			reg = <0 0x11003000 0 0x1000>;
281			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
282			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
283			clock-names = "baud", "bus";
284			status = "disabled";
285		};
286
287		uart2: serial@11004000 {
288			compatible = "mediatek,mt8183-uart",
289				     "mediatek,mt6577-uart";
290			reg = <0 0x11004000 0 0x1000>;
291			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
292			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
293			clock-names = "baud", "bus";
294			status = "disabled";
295		};
296
297		spi0: spi@1100a000 {
298			compatible = "mediatek,mt8183-spi";
299			#address-cells = <1>;
300			#size-cells = <0>;
301			reg = <0 0x1100a000 0 0x1000>;
302			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
303			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
304				 <&topckgen CLK_TOP_MUX_SPI>,
305				 <&infracfg CLK_INFRA_SPI0>;
306			clock-names = "parent-clk", "sel-clk", "spi-clk";
307			status = "disabled";
308		};
309
310		spi1: spi@11010000 {
311			compatible = "mediatek,mt8183-spi";
312			#address-cells = <1>;
313			#size-cells = <0>;
314			reg = <0 0x11010000 0 0x1000>;
315			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
316			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
317				 <&topckgen CLK_TOP_MUX_SPI>,
318				 <&infracfg CLK_INFRA_SPI1>;
319			clock-names = "parent-clk", "sel-clk", "spi-clk";
320			status = "disabled";
321		};
322
323		spi2: spi@11012000 {
324			compatible = "mediatek,mt8183-spi";
325			#address-cells = <1>;
326			#size-cells = <0>;
327			reg = <0 0x11012000 0 0x1000>;
328			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
329			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
330				 <&topckgen CLK_TOP_MUX_SPI>,
331				 <&infracfg CLK_INFRA_SPI2>;
332			clock-names = "parent-clk", "sel-clk", "spi-clk";
333			status = "disabled";
334		};
335
336		spi3: spi@11013000 {
337			compatible = "mediatek,mt8183-spi";
338			#address-cells = <1>;
339			#size-cells = <0>;
340			reg = <0 0x11013000 0 0x1000>;
341			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
342			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
343				 <&topckgen CLK_TOP_MUX_SPI>,
344				 <&infracfg CLK_INFRA_SPI3>;
345			clock-names = "parent-clk", "sel-clk", "spi-clk";
346			status = "disabled";
347		};
348
349		spi4: spi@11018000 {
350			compatible = "mediatek,mt8183-spi";
351			#address-cells = <1>;
352			#size-cells = <0>;
353			reg = <0 0x11018000 0 0x1000>;
354			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
355			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
356				 <&topckgen CLK_TOP_MUX_SPI>,
357				 <&infracfg CLK_INFRA_SPI4>;
358			clock-names = "parent-clk", "sel-clk", "spi-clk";
359			status = "disabled";
360		};
361
362		spi5: spi@11019000 {
363			compatible = "mediatek,mt8183-spi";
364			#address-cells = <1>;
365			#size-cells = <0>;
366			reg = <0 0x11019000 0 0x1000>;
367			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
368			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
369				 <&topckgen CLK_TOP_MUX_SPI>,
370				 <&infracfg CLK_INFRA_SPI5>;
371			clock-names = "parent-clk", "sel-clk", "spi-clk";
372			status = "disabled";
373		};
374
375		audiosys: syscon@11220000 {
376			compatible = "mediatek,mt8183-audiosys", "syscon";
377			reg = <0 0x11220000 0 0x1000>;
378			#clock-cells = <1>;
379		};
380
381		efuse: efuse@11f10000 {
382			compatible = "mediatek,mt8183-efuse",
383				     "mediatek,efuse";
384			reg = <0 0x11f10000 0 0x1000>;
385		};
386
387		mfgcfg: syscon@13000000 {
388			compatible = "mediatek,mt8183-mfgcfg", "syscon";
389			reg = <0 0x13000000 0 0x1000>;
390			#clock-cells = <1>;
391		};
392
393		mmsys: syscon@14000000 {
394			compatible = "mediatek,mt8183-mmsys", "syscon";
395			reg = <0 0x14000000 0 0x1000>;
396			#clock-cells = <1>;
397		};
398
399		imgsys: syscon@15020000 {
400			compatible = "mediatek,mt8183-imgsys", "syscon";
401			reg = <0 0x15020000 0 0x1000>;
402			#clock-cells = <1>;
403		};
404
405		vdecsys: syscon@16000000 {
406			compatible = "mediatek,mt8183-vdecsys", "syscon";
407			reg = <0 0x16000000 0 0x1000>;
408			#clock-cells = <1>;
409		};
410
411		vencsys: syscon@17000000 {
412			compatible = "mediatek,mt8183-vencsys", "syscon";
413			reg = <0 0x17000000 0 0x1000>;
414			#clock-cells = <1>;
415		};
416
417		ipu_conn: syscon@19000000 {
418			compatible = "mediatek,mt8183-ipu_conn", "syscon";
419			reg = <0 0x19000000 0 0x1000>;
420			#clock-cells = <1>;
421		};
422
423		ipu_adl: syscon@19010000 {
424			compatible = "mediatek,mt8183-ipu_adl", "syscon";
425			reg = <0 0x19010000 0 0x1000>;
426			#clock-cells = <1>;
427		};
428
429		ipu_core0: syscon@19180000 {
430			compatible = "mediatek,mt8183-ipu_core0", "syscon";
431			reg = <0 0x19180000 0 0x1000>;
432			#clock-cells = <1>;
433		};
434
435		ipu_core1: syscon@19280000 {
436			compatible = "mediatek,mt8183-ipu_core1", "syscon";
437			reg = <0 0x19280000 0 0x1000>;
438			#clock-cells = <1>;
439		};
440
441		camsys: syscon@1a000000 {
442			compatible = "mediatek,mt8183-camsys", "syscon";
443			reg = <0 0x1a000000 0 0x1000>;
444			#clock-cells = <1>;
445		};
446	};
447};
448