1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8183-larb-port.h> 12#include <dt-bindings/power/mt8183-power.h> 13#include <dt-bindings/reset-controller/mt8183-resets.h> 14#include <dt-bindings/phy/phy.h> 15#include "mt8183-pinfunc.h" 16 17/ { 18 compatible = "mediatek,mt8183"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 i2c9 = &i2c9; 34 i2c10 = &i2c10; 35 i2c11 = &i2c11; 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 cpu-map { 43 cluster0 { 44 core0 { 45 cpu = <&cpu0>; 46 }; 47 core1 { 48 cpu = <&cpu1>; 49 }; 50 core2 { 51 cpu = <&cpu2>; 52 }; 53 core3 { 54 cpu = <&cpu3>; 55 }; 56 }; 57 58 cluster1 { 59 core0 { 60 cpu = <&cpu4>; 61 }; 62 core1 { 63 cpu = <&cpu5>; 64 }; 65 core2 { 66 cpu = <&cpu6>; 67 }; 68 core3 { 69 cpu = <&cpu7>; 70 }; 71 }; 72 }; 73 74 cpu0: cpu@0 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x000>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <741>; 80 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 81 dynamic-power-coefficient = <84>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x001>; 89 enable-method = "psci"; 90 capacity-dmips-mhz = <741>; 91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 92 dynamic-power-coefficient = <84>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu2: cpu@2 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x002>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <741>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 103 dynamic-power-coefficient = <84>; 104 #cooling-cells = <2>; 105 }; 106 107 cpu3: cpu@3 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a53"; 110 reg = <0x003>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <741>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 114 dynamic-power-coefficient = <84>; 115 #cooling-cells = <2>; 116 }; 117 118 cpu4: cpu@100 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a73"; 121 reg = <0x100>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <1024>; 124 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 125 dynamic-power-coefficient = <211>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu5: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a73"; 132 reg = <0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 136 dynamic-power-coefficient = <211>; 137 #cooling-cells = <2>; 138 }; 139 140 cpu6: cpu@102 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a73"; 143 reg = <0x102>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 147 dynamic-power-coefficient = <211>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu7: cpu@103 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a73"; 154 reg = <0x103>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 158 dynamic-power-coefficient = <211>; 159 #cooling-cells = <2>; 160 }; 161 162 idle-states { 163 entry-method = "psci"; 164 165 CPU_SLEEP: cpu-sleep { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x00010001>; 169 entry-latency-us = <200>; 170 exit-latency-us = <200>; 171 min-residency-us = <800>; 172 }; 173 174 CLUSTER_SLEEP0: cluster-sleep-0 { 175 compatible = "arm,idle-state"; 176 local-timer-stop; 177 arm,psci-suspend-param = <0x01010001>; 178 entry-latency-us = <250>; 179 exit-latency-us = <400>; 180 min-residency-us = <1000>; 181 }; 182 CLUSTER_SLEEP1: cluster-sleep-1 { 183 compatible = "arm,idle-state"; 184 local-timer-stop; 185 arm,psci-suspend-param = <0x01010001>; 186 entry-latency-us = <250>; 187 exit-latency-us = <400>; 188 min-residency-us = <1300>; 189 }; 190 }; 191 }; 192 193 pmu-a53 { 194 compatible = "arm,cortex-a53-pmu"; 195 interrupt-parent = <&gic>; 196 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 197 }; 198 199 pmu-a73 { 200 compatible = "arm,cortex-a73-pmu"; 201 interrupt-parent = <&gic>; 202 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 203 }; 204 205 psci { 206 compatible = "arm,psci-1.0"; 207 method = "smc"; 208 }; 209 210 clk26m: oscillator { 211 compatible = "fixed-clock"; 212 #clock-cells = <0>; 213 clock-frequency = <26000000>; 214 clock-output-names = "clk26m"; 215 }; 216 217 timer { 218 compatible = "arm,armv8-timer"; 219 interrupt-parent = <&gic>; 220 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 221 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 222 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 223 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 224 }; 225 226 soc { 227 #address-cells = <2>; 228 #size-cells = <2>; 229 compatible = "simple-bus"; 230 ranges; 231 232 soc_data: soc_data@8000000 { 233 compatible = "mediatek,mt8183-efuse", 234 "mediatek,efuse"; 235 reg = <0 0x08000000 0 0x0010>; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 status = "disabled"; 239 }; 240 241 gic: interrupt-controller@c000000 { 242 compatible = "arm,gic-v3"; 243 #interrupt-cells = <4>; 244 interrupt-parent = <&gic>; 245 interrupt-controller; 246 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 247 <0 0x0c100000 0 0x200000>, /* GICR */ 248 <0 0x0c400000 0 0x2000>, /* GICC */ 249 <0 0x0c410000 0 0x1000>, /* GICH */ 250 <0 0x0c420000 0 0x2000>; /* GICV */ 251 252 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 253 ppi-partitions { 254 ppi_cluster0: interrupt-partition-0 { 255 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 256 }; 257 ppi_cluster1: interrupt-partition-1 { 258 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 259 }; 260 }; 261 }; 262 263 mcucfg: syscon@c530000 { 264 compatible = "mediatek,mt8183-mcucfg", "syscon"; 265 reg = <0 0x0c530000 0 0x1000>; 266 #clock-cells = <1>; 267 }; 268 269 sysirq: interrupt-controller@c530a80 { 270 compatible = "mediatek,mt8183-sysirq", 271 "mediatek,mt6577-sysirq"; 272 interrupt-controller; 273 #interrupt-cells = <3>; 274 interrupt-parent = <&gic>; 275 reg = <0 0x0c530a80 0 0x50>; 276 }; 277 278 topckgen: syscon@10000000 { 279 compatible = "mediatek,mt8183-topckgen", "syscon"; 280 reg = <0 0x10000000 0 0x1000>; 281 #clock-cells = <1>; 282 }; 283 284 infracfg: syscon@10001000 { 285 compatible = "mediatek,mt8183-infracfg", "syscon"; 286 reg = <0 0x10001000 0 0x1000>; 287 #clock-cells = <1>; 288 #reset-cells = <1>; 289 }; 290 291 pericfg: syscon@10003000 { 292 compatible = "mediatek,mt8183-pericfg", "syscon"; 293 reg = <0 0x10003000 0 0x1000>; 294 #clock-cells = <1>; 295 }; 296 297 pio: pinctrl@10005000 { 298 compatible = "mediatek,mt8183-pinctrl"; 299 reg = <0 0x10005000 0 0x1000>, 300 <0 0x11f20000 0 0x1000>, 301 <0 0x11e80000 0 0x1000>, 302 <0 0x11e70000 0 0x1000>, 303 <0 0x11e90000 0 0x1000>, 304 <0 0x11d30000 0 0x1000>, 305 <0 0x11d20000 0 0x1000>, 306 <0 0x11c50000 0 0x1000>, 307 <0 0x11f30000 0 0x1000>, 308 <0 0x1000b000 0 0x1000>; 309 reg-names = "iocfg0", "iocfg1", "iocfg2", 310 "iocfg3", "iocfg4", "iocfg5", 311 "iocfg6", "iocfg7", "iocfg8", 312 "eint"; 313 gpio-controller; 314 #gpio-cells = <2>; 315 gpio-ranges = <&pio 0 0 192>; 316 interrupt-controller; 317 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 318 #interrupt-cells = <2>; 319 }; 320 321 scpsys: syscon@10006000 { 322 compatible = "syscon", "simple-mfd"; 323 reg = <0 0x10006000 0 0x1000>; 324 #power-domain-cells = <1>; 325 326 /* System Power Manager */ 327 spm: power-controller { 328 compatible = "mediatek,mt8183-power-controller"; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 #power-domain-cells = <1>; 332 333 /* power domain of the SoC */ 334 power-domain@MT8183_POWER_DOMAIN_AUDIO { 335 reg = <MT8183_POWER_DOMAIN_AUDIO>; 336 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 337 <&infracfg CLK_INFRA_AUDIO>, 338 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 339 clock-names = "audio", "audio1", "audio2"; 340 #power-domain-cells = <0>; 341 }; 342 343 power-domain@MT8183_POWER_DOMAIN_CONN { 344 reg = <MT8183_POWER_DOMAIN_CONN>; 345 mediatek,infracfg = <&infracfg>; 346 #power-domain-cells = <0>; 347 }; 348 349 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 350 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 351 clocks = <&topckgen CLK_TOP_MUX_MFG>; 352 clock-names = "mfg"; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 #power-domain-cells = <1>; 356 357 power-domain@MT8183_POWER_DOMAIN_MFG { 358 reg = <MT8183_POWER_DOMAIN_MFG>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 #power-domain-cells = <1>; 362 363 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 364 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 365 #power-domain-cells = <0>; 366 }; 367 368 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 369 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 370 #power-domain-cells = <0>; 371 }; 372 373 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 374 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 375 mediatek,infracfg = <&infracfg>; 376 #power-domain-cells = <0>; 377 }; 378 }; 379 }; 380 381 power-domain@MT8183_POWER_DOMAIN_DISP { 382 reg = <MT8183_POWER_DOMAIN_DISP>; 383 clocks = <&topckgen CLK_TOP_MUX_MM>, 384 <&mmsys CLK_MM_SMI_COMMON>, 385 <&mmsys CLK_MM_SMI_LARB0>, 386 <&mmsys CLK_MM_SMI_LARB1>, 387 <&mmsys CLK_MM_GALS_COMM0>, 388 <&mmsys CLK_MM_GALS_COMM1>, 389 <&mmsys CLK_MM_GALS_CCU2MM>, 390 <&mmsys CLK_MM_GALS_IPU12MM>, 391 <&mmsys CLK_MM_GALS_IMG2MM>, 392 <&mmsys CLK_MM_GALS_CAM2MM>, 393 <&mmsys CLK_MM_GALS_IPU2MM>; 394 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 395 "mm-4", "mm-5", "mm-6", "mm-7", 396 "mm-8", "mm-9"; 397 mediatek,infracfg = <&infracfg>; 398 mediatek,smi = <&smi_common>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 #power-domain-cells = <1>; 402 403 power-domain@MT8183_POWER_DOMAIN_CAM { 404 reg = <MT8183_POWER_DOMAIN_CAM>; 405 clocks = <&topckgen CLK_TOP_MUX_CAM>, 406 <&camsys CLK_CAM_LARB6>, 407 <&camsys CLK_CAM_LARB3>, 408 <&camsys CLK_CAM_SENINF>, 409 <&camsys CLK_CAM_CAMSV0>, 410 <&camsys CLK_CAM_CAMSV1>, 411 <&camsys CLK_CAM_CAMSV2>, 412 <&camsys CLK_CAM_CCU>; 413 clock-names = "cam", "cam-0", "cam-1", 414 "cam-2", "cam-3", "cam-4", 415 "cam-5", "cam-6"; 416 mediatek,infracfg = <&infracfg>; 417 mediatek,smi = <&smi_common>; 418 #power-domain-cells = <0>; 419 }; 420 421 power-domain@MT8183_POWER_DOMAIN_ISP { 422 reg = <MT8183_POWER_DOMAIN_ISP>; 423 clocks = <&topckgen CLK_TOP_MUX_IMG>, 424 <&imgsys CLK_IMG_LARB5>, 425 <&imgsys CLK_IMG_LARB2>; 426 clock-names = "isp", "isp-0", "isp-1"; 427 mediatek,infracfg = <&infracfg>; 428 mediatek,smi = <&smi_common>; 429 #power-domain-cells = <0>; 430 }; 431 432 power-domain@MT8183_POWER_DOMAIN_VDEC { 433 reg = <MT8183_POWER_DOMAIN_VDEC>; 434 mediatek,smi = <&smi_common>; 435 #power-domain-cells = <0>; 436 }; 437 438 power-domain@MT8183_POWER_DOMAIN_VENC { 439 reg = <MT8183_POWER_DOMAIN_VENC>; 440 mediatek,smi = <&smi_common>; 441 #power-domain-cells = <0>; 442 }; 443 444 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 445 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 446 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 447 <&topckgen CLK_TOP_MUX_DSP>, 448 <&ipu_conn CLK_IPU_CONN_IPU>, 449 <&ipu_conn CLK_IPU_CONN_AHB>, 450 <&ipu_conn CLK_IPU_CONN_AXI>, 451 <&ipu_conn CLK_IPU_CONN_ISP>, 452 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 453 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 454 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 455 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 456 mediatek,infracfg = <&infracfg>; 457 mediatek,smi = <&smi_common>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 #power-domain-cells = <1>; 461 462 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 463 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 464 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 465 clock-names = "vpu2"; 466 mediatek,infracfg = <&infracfg>; 467 #power-domain-cells = <0>; 468 }; 469 470 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 471 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 472 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 473 clock-names = "vpu3"; 474 mediatek,infracfg = <&infracfg>; 475 #power-domain-cells = <0>; 476 }; 477 }; 478 }; 479 }; 480 }; 481 482 watchdog: watchdog@10007000 { 483 compatible = "mediatek,mt8183-wdt"; 484 reg = <0 0x10007000 0 0x100>; 485 #reset-cells = <1>; 486 }; 487 488 apmixedsys: syscon@1000c000 { 489 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 490 reg = <0 0x1000c000 0 0x1000>; 491 #clock-cells = <1>; 492 }; 493 494 pwrap: pwrap@1000d000 { 495 compatible = "mediatek,mt8183-pwrap"; 496 reg = <0 0x1000d000 0 0x1000>; 497 reg-names = "pwrap"; 498 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 500 <&infracfg CLK_INFRA_PMIC_AP>; 501 clock-names = "spi", "wrap"; 502 }; 503 504 scp: scp@10500000 { 505 compatible = "mediatek,mt8183-scp"; 506 reg = <0 0x10500000 0 0x80000>, 507 <0 0x105c0000 0 0x19080>; 508 reg-names = "sram", "cfg"; 509 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&infracfg CLK_INFRA_SCPSYS>; 511 clock-names = "main"; 512 memory-region = <&scp_mem_reserved>; 513 status = "disabled"; 514 }; 515 516 systimer: timer@10017000 { 517 compatible = "mediatek,mt8183-timer", 518 "mediatek,mt6765-timer"; 519 reg = <0 0x10017000 0 0x1000>; 520 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&topckgen CLK_TOP_CLK13M>; 522 clock-names = "clk13m"; 523 }; 524 525 iommu: iommu@10205000 { 526 compatible = "mediatek,mt8183-m4u"; 527 reg = <0 0x10205000 0 0x1000>; 528 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 529 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 530 &larb4 &larb5 &larb6>; 531 #iommu-cells = <1>; 532 }; 533 534 gce: mailbox@10238000 { 535 compatible = "mediatek,mt8183-gce"; 536 reg = <0 0x10238000 0 0x4000>; 537 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 538 #mbox-cells = <2>; 539 clocks = <&infracfg CLK_INFRA_GCE>; 540 clock-names = "gce"; 541 }; 542 543 auxadc: auxadc@11001000 { 544 compatible = "mediatek,mt8183-auxadc", 545 "mediatek,mt8173-auxadc"; 546 reg = <0 0x11001000 0 0x1000>; 547 clocks = <&infracfg CLK_INFRA_AUXADC>; 548 clock-names = "main"; 549 #io-channel-cells = <1>; 550 status = "disabled"; 551 }; 552 553 uart0: serial@11002000 { 554 compatible = "mediatek,mt8183-uart", 555 "mediatek,mt6577-uart"; 556 reg = <0 0x11002000 0 0x1000>; 557 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 558 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 559 clock-names = "baud", "bus"; 560 status = "disabled"; 561 }; 562 563 uart1: serial@11003000 { 564 compatible = "mediatek,mt8183-uart", 565 "mediatek,mt6577-uart"; 566 reg = <0 0x11003000 0 0x1000>; 567 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 568 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 569 clock-names = "baud", "bus"; 570 status = "disabled"; 571 }; 572 573 uart2: serial@11004000 { 574 compatible = "mediatek,mt8183-uart", 575 "mediatek,mt6577-uart"; 576 reg = <0 0x11004000 0 0x1000>; 577 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 578 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 579 clock-names = "baud", "bus"; 580 status = "disabled"; 581 }; 582 583 i2c6: i2c@11005000 { 584 compatible = "mediatek,mt8183-i2c"; 585 reg = <0 0x11005000 0 0x1000>, 586 <0 0x11000600 0 0x80>; 587 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 588 clocks = <&infracfg CLK_INFRA_I2C6>, 589 <&infracfg CLK_INFRA_AP_DMA>; 590 clock-names = "main", "dma"; 591 clock-div = <1>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 i2c0: i2c@11007000 { 598 compatible = "mediatek,mt8183-i2c"; 599 reg = <0 0x11007000 0 0x1000>, 600 <0 0x11000080 0 0x80>; 601 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 602 clocks = <&infracfg CLK_INFRA_I2C0>, 603 <&infracfg CLK_INFRA_AP_DMA>; 604 clock-names = "main", "dma"; 605 clock-div = <1>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 i2c4: i2c@11008000 { 612 compatible = "mediatek,mt8183-i2c"; 613 reg = <0 0x11008000 0 0x1000>, 614 <0 0x11000100 0 0x80>; 615 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 616 clocks = <&infracfg CLK_INFRA_I2C1>, 617 <&infracfg CLK_INFRA_AP_DMA>, 618 <&infracfg CLK_INFRA_I2C1_ARBITER>; 619 clock-names = "main", "dma","arb"; 620 clock-div = <1>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 i2c2: i2c@11009000 { 627 compatible = "mediatek,mt8183-i2c"; 628 reg = <0 0x11009000 0 0x1000>, 629 <0 0x11000280 0 0x80>; 630 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 631 clocks = <&infracfg CLK_INFRA_I2C2>, 632 <&infracfg CLK_INFRA_AP_DMA>, 633 <&infracfg CLK_INFRA_I2C2_ARBITER>; 634 clock-names = "main", "dma", "arb"; 635 clock-div = <1>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 spi0: spi@1100a000 { 642 compatible = "mediatek,mt8183-spi"; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 reg = <0 0x1100a000 0 0x1000>; 646 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 647 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 648 <&topckgen CLK_TOP_MUX_SPI>, 649 <&infracfg CLK_INFRA_SPI0>; 650 clock-names = "parent-clk", "sel-clk", "spi-clk"; 651 status = "disabled"; 652 }; 653 654 pwm0: pwm@1100e000 { 655 compatible = "mediatek,mt8183-disp-pwm"; 656 reg = <0 0x1100e000 0 0x1000>; 657 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 658 #pwm-cells = <2>; 659 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 660 <&infracfg CLK_INFRA_DISP_PWM>; 661 clock-names = "main", "mm"; 662 }; 663 664 i2c3: i2c@1100f000 { 665 compatible = "mediatek,mt8183-i2c"; 666 reg = <0 0x1100f000 0 0x1000>, 667 <0 0x11000400 0 0x80>; 668 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 669 clocks = <&infracfg CLK_INFRA_I2C3>, 670 <&infracfg CLK_INFRA_AP_DMA>; 671 clock-names = "main", "dma"; 672 clock-div = <1>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 status = "disabled"; 676 }; 677 678 spi1: spi@11010000 { 679 compatible = "mediatek,mt8183-spi"; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 reg = <0 0x11010000 0 0x1000>; 683 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 684 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 685 <&topckgen CLK_TOP_MUX_SPI>, 686 <&infracfg CLK_INFRA_SPI1>; 687 clock-names = "parent-clk", "sel-clk", "spi-clk"; 688 status = "disabled"; 689 }; 690 691 i2c1: i2c@11011000 { 692 compatible = "mediatek,mt8183-i2c"; 693 reg = <0 0x11011000 0 0x1000>, 694 <0 0x11000480 0 0x80>; 695 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 696 clocks = <&infracfg CLK_INFRA_I2C4>, 697 <&infracfg CLK_INFRA_AP_DMA>; 698 clock-names = "main", "dma"; 699 clock-div = <1>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 spi2: spi@11012000 { 706 compatible = "mediatek,mt8183-spi"; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 reg = <0 0x11012000 0 0x1000>; 710 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 711 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 712 <&topckgen CLK_TOP_MUX_SPI>, 713 <&infracfg CLK_INFRA_SPI2>; 714 clock-names = "parent-clk", "sel-clk", "spi-clk"; 715 status = "disabled"; 716 }; 717 718 spi3: spi@11013000 { 719 compatible = "mediatek,mt8183-spi"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 reg = <0 0x11013000 0 0x1000>; 723 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 724 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 725 <&topckgen CLK_TOP_MUX_SPI>, 726 <&infracfg CLK_INFRA_SPI3>; 727 clock-names = "parent-clk", "sel-clk", "spi-clk"; 728 status = "disabled"; 729 }; 730 731 i2c9: i2c@11014000 { 732 compatible = "mediatek,mt8183-i2c"; 733 reg = <0 0x11014000 0 0x1000>, 734 <0 0x11000180 0 0x80>; 735 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 736 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 737 <&infracfg CLK_INFRA_AP_DMA>, 738 <&infracfg CLK_INFRA_I2C1_ARBITER>; 739 clock-names = "main", "dma", "arb"; 740 clock-div = <1>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 status = "disabled"; 744 }; 745 746 i2c10: i2c@11015000 { 747 compatible = "mediatek,mt8183-i2c"; 748 reg = <0 0x11015000 0 0x1000>, 749 <0 0x11000300 0 0x80>; 750 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 751 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 752 <&infracfg CLK_INFRA_AP_DMA>, 753 <&infracfg CLK_INFRA_I2C2_ARBITER>; 754 clock-names = "main", "dma", "arb"; 755 clock-div = <1>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 i2c5: i2c@11016000 { 762 compatible = "mediatek,mt8183-i2c"; 763 reg = <0 0x11016000 0 0x1000>, 764 <0 0x11000500 0 0x80>; 765 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 766 clocks = <&infracfg CLK_INFRA_I2C5>, 767 <&infracfg CLK_INFRA_AP_DMA>, 768 <&infracfg CLK_INFRA_I2C5_ARBITER>; 769 clock-names = "main", "dma", "arb"; 770 clock-div = <1>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 i2c11: i2c@11017000 { 777 compatible = "mediatek,mt8183-i2c"; 778 reg = <0 0x11017000 0 0x1000>, 779 <0 0x11000580 0 0x80>; 780 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 781 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 782 <&infracfg CLK_INFRA_AP_DMA>, 783 <&infracfg CLK_INFRA_I2C5_ARBITER>; 784 clock-names = "main", "dma", "arb"; 785 clock-div = <1>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 status = "disabled"; 789 }; 790 791 spi4: spi@11018000 { 792 compatible = "mediatek,mt8183-spi"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 reg = <0 0x11018000 0 0x1000>; 796 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 797 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 798 <&topckgen CLK_TOP_MUX_SPI>, 799 <&infracfg CLK_INFRA_SPI4>; 800 clock-names = "parent-clk", "sel-clk", "spi-clk"; 801 status = "disabled"; 802 }; 803 804 spi5: spi@11019000 { 805 compatible = "mediatek,mt8183-spi"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 reg = <0 0x11019000 0 0x1000>; 809 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 810 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 811 <&topckgen CLK_TOP_MUX_SPI>, 812 <&infracfg CLK_INFRA_SPI5>; 813 clock-names = "parent-clk", "sel-clk", "spi-clk"; 814 status = "disabled"; 815 }; 816 817 i2c7: i2c@1101a000 { 818 compatible = "mediatek,mt8183-i2c"; 819 reg = <0 0x1101a000 0 0x1000>, 820 <0 0x11000680 0 0x80>; 821 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 822 clocks = <&infracfg CLK_INFRA_I2C7>, 823 <&infracfg CLK_INFRA_AP_DMA>; 824 clock-names = "main", "dma"; 825 clock-div = <1>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 status = "disabled"; 829 }; 830 831 i2c8: i2c@1101b000 { 832 compatible = "mediatek,mt8183-i2c"; 833 reg = <0 0x1101b000 0 0x1000>, 834 <0 0x11000700 0 0x80>; 835 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 836 clocks = <&infracfg CLK_INFRA_I2C8>, 837 <&infracfg CLK_INFRA_AP_DMA>; 838 clock-names = "main", "dma"; 839 clock-div = <1>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 ssusb: usb@11201000 { 846 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 847 reg = <0 0x11201000 0 0x2e00>, 848 <0 0x11203e00 0 0x0100>; 849 reg-names = "mac", "ippc"; 850 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 851 phys = <&u2port0 PHY_TYPE_USB2>, 852 <&u3port0 PHY_TYPE_USB3>; 853 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 854 <&infracfg CLK_INFRA_USB>; 855 clock-names = "sys_ck", "ref_ck"; 856 mediatek,syscon-wakeup = <&pericfg 0x400 0>; 857 #address-cells = <2>; 858 #size-cells = <2>; 859 ranges; 860 status = "disabled"; 861 862 usb_host: xhci@11200000 { 863 compatible = "mediatek,mt8183-xhci", 864 "mediatek,mtk-xhci"; 865 reg = <0 0x11200000 0 0x1000>; 866 reg-names = "mac"; 867 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 868 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 869 <&infracfg CLK_INFRA_USB>; 870 clock-names = "sys_ck", "ref_ck"; 871 status = "disabled"; 872 }; 873 }; 874 875 audiosys: syscon@11220000 { 876 compatible = "mediatek,mt8183-audiosys", "syscon"; 877 reg = <0 0x11220000 0 0x1000>; 878 #clock-cells = <1>; 879 }; 880 881 mmc0: mmc@11230000 { 882 compatible = "mediatek,mt8183-mmc"; 883 reg = <0 0x11230000 0 0x1000>, 884 <0 0x11f50000 0 0x1000>; 885 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 886 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 887 <&infracfg CLK_INFRA_MSDC0>, 888 <&infracfg CLK_INFRA_MSDC0_SCK>; 889 clock-names = "source", "hclk", "source_cg"; 890 status = "disabled"; 891 }; 892 893 mmc1: mmc@11240000 { 894 compatible = "mediatek,mt8183-mmc"; 895 reg = <0 0x11240000 0 0x1000>, 896 <0 0x11e10000 0 0x1000>; 897 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 898 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 899 <&infracfg CLK_INFRA_MSDC1>, 900 <&infracfg CLK_INFRA_MSDC1_SCK>; 901 clock-names = "source", "hclk", "source_cg"; 902 status = "disabled"; 903 }; 904 905 mipi_tx0: mipi-dphy@11e50000 { 906 compatible = "mediatek,mt8183-mipi-tx"; 907 reg = <0 0x11e50000 0 0x1000>; 908 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 909 clock-names = "ref_clk"; 910 #clock-cells = <0>; 911 #phy-cells = <0>; 912 clock-output-names = "mipi_tx0_pll"; 913 nvmem-cells = <&mipi_tx_calibration>; 914 nvmem-cell-names = "calibration-data"; 915 }; 916 917 efuse: efuse@11f10000 { 918 compatible = "mediatek,mt8183-efuse", 919 "mediatek,efuse"; 920 reg = <0 0x11f10000 0 0x1000>; 921 #address-cells = <1>; 922 #size-cells = <1>; 923 mipi_tx_calibration: calib@190 { 924 reg = <0x190 0xc>; 925 }; 926 }; 927 928 u3phy: usb-phy@11f40000 { 929 compatible = "mediatek,mt8183-tphy", 930 "mediatek,generic-tphy-v2"; 931 #address-cells = <1>; 932 #phy-cells = <1>; 933 #size-cells = <1>; 934 ranges = <0 0 0x11f40000 0x1000>; 935 status = "okay"; 936 937 u2port0: usb-phy@0 { 938 reg = <0x0 0x700>; 939 clocks = <&clk26m>; 940 clock-names = "ref"; 941 #phy-cells = <1>; 942 mediatek,discth = <15>; 943 status = "okay"; 944 }; 945 946 u3port0: usb-phy@0700 { 947 reg = <0x0700 0x900>; 948 clocks = <&clk26m>; 949 clock-names = "ref"; 950 #phy-cells = <1>; 951 status = "okay"; 952 }; 953 }; 954 955 mfgcfg: syscon@13000000 { 956 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 957 reg = <0 0x13000000 0 0x1000>; 958 #clock-cells = <1>; 959 }; 960 961 mmsys: syscon@14000000 { 962 compatible = "mediatek,mt8183-mmsys", "syscon"; 963 reg = <0 0x14000000 0 0x1000>; 964 #clock-cells = <1>; 965 }; 966 967 dsi0: dsi@14014000 { 968 compatible = "mediatek,mt8183-dsi"; 969 reg = <0 0x14014000 0 0x1000>; 970 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 971 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 972 mediatek,syscon-dsi = <&mmsys 0x140>; 973 clocks = <&mmsys CLK_MM_DSI0_MM>, 974 <&mmsys CLK_MM_DSI0_IF>, 975 <&mipi_tx0>; 976 clock-names = "engine", "digital", "hs"; 977 phys = <&mipi_tx0>; 978 phy-names = "dphy"; 979 }; 980 981 larb0: larb@14017000 { 982 compatible = "mediatek,mt8183-smi-larb"; 983 reg = <0 0x14017000 0 0x1000>; 984 mediatek,smi = <&smi_common>; 985 clocks = <&mmsys CLK_MM_SMI_LARB0>, 986 <&mmsys CLK_MM_SMI_LARB0>; 987 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 988 clock-names = "apb", "smi"; 989 }; 990 991 smi_common: smi@14019000 { 992 compatible = "mediatek,mt8183-smi-common", "syscon"; 993 reg = <0 0x14019000 0 0x1000>; 994 clocks = <&mmsys CLK_MM_SMI_COMMON>, 995 <&mmsys CLK_MM_SMI_COMMON>, 996 <&mmsys CLK_MM_GALS_COMM0>, 997 <&mmsys CLK_MM_GALS_COMM1>; 998 clock-names = "apb", "smi", "gals0", "gals1"; 999 }; 1000 1001 imgsys: syscon@15020000 { 1002 compatible = "mediatek,mt8183-imgsys", "syscon"; 1003 reg = <0 0x15020000 0 0x1000>; 1004 #clock-cells = <1>; 1005 }; 1006 1007 larb5: larb@15021000 { 1008 compatible = "mediatek,mt8183-smi-larb"; 1009 reg = <0 0x15021000 0 0x1000>; 1010 mediatek,smi = <&smi_common>; 1011 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1012 <&mmsys CLK_MM_GALS_IMG2MM>; 1013 clock-names = "apb", "smi", "gals"; 1014 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1015 }; 1016 1017 larb2: larb@1502f000 { 1018 compatible = "mediatek,mt8183-smi-larb"; 1019 reg = <0 0x1502f000 0 0x1000>; 1020 mediatek,smi = <&smi_common>; 1021 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1022 <&mmsys CLK_MM_GALS_IPU2MM>; 1023 clock-names = "apb", "smi", "gals"; 1024 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1025 }; 1026 1027 vdecsys: syscon@16000000 { 1028 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1029 reg = <0 0x16000000 0 0x1000>; 1030 #clock-cells = <1>; 1031 }; 1032 1033 larb1: larb@16010000 { 1034 compatible = "mediatek,mt8183-smi-larb"; 1035 reg = <0 0x16010000 0 0x1000>; 1036 mediatek,smi = <&smi_common>; 1037 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1038 clock-names = "apb", "smi"; 1039 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1040 }; 1041 1042 vencsys: syscon@17000000 { 1043 compatible = "mediatek,mt8183-vencsys", "syscon"; 1044 reg = <0 0x17000000 0 0x1000>; 1045 #clock-cells = <1>; 1046 }; 1047 1048 larb4: larb@17010000 { 1049 compatible = "mediatek,mt8183-smi-larb"; 1050 reg = <0 0x17010000 0 0x1000>; 1051 mediatek,smi = <&smi_common>; 1052 clocks = <&vencsys CLK_VENC_LARB>, 1053 <&vencsys CLK_VENC_LARB>; 1054 clock-names = "apb", "smi"; 1055 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1056 }; 1057 1058 ipu_conn: syscon@19000000 { 1059 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1060 reg = <0 0x19000000 0 0x1000>; 1061 #clock-cells = <1>; 1062 }; 1063 1064 ipu_adl: syscon@19010000 { 1065 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1066 reg = <0 0x19010000 0 0x1000>; 1067 #clock-cells = <1>; 1068 }; 1069 1070 ipu_core0: syscon@19180000 { 1071 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1072 reg = <0 0x19180000 0 0x1000>; 1073 #clock-cells = <1>; 1074 }; 1075 1076 ipu_core1: syscon@19280000 { 1077 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1078 reg = <0 0x19280000 0 0x1000>; 1079 #clock-cells = <1>; 1080 }; 1081 1082 camsys: syscon@1a000000 { 1083 compatible = "mediatek,mt8183-camsys", "syscon"; 1084 reg = <0 0x1a000000 0 0x1000>; 1085 #clock-cells = <1>; 1086 }; 1087 1088 larb6: larb@1a001000 { 1089 compatible = "mediatek,mt8183-smi-larb"; 1090 reg = <0 0x1a001000 0 0x1000>; 1091 mediatek,smi = <&smi_common>; 1092 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1093 <&mmsys CLK_MM_GALS_CAM2MM>; 1094 clock-names = "apb", "smi", "gals"; 1095 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1096 }; 1097 1098 larb3: larb@1a002000 { 1099 compatible = "mediatek,mt8183-smi-larb"; 1100 reg = <0 0x1a002000 0 0x1000>; 1101 mediatek,smi = <&smi_common>; 1102 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1103 <&mmsys CLK_MM_GALS_IPU12MM>; 1104 clock-names = "apb", "smi", "gals"; 1105 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1106 }; 1107 }; 1108}; 1109