1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include "mt8183-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt8183"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c7; 29 i2c8 = &i2c8; 30 i2c9 = &i2c9; 31 i2c10 = &i2c10; 32 i2c11 = &i2c11; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 core1 { 45 cpu = <&cpu1>; 46 }; 47 core2 { 48 cpu = <&cpu2>; 49 }; 50 core3 { 51 cpu = <&cpu3>; 52 }; 53 }; 54 55 cluster1 { 56 core0 { 57 cpu = <&cpu4>; 58 }; 59 core1 { 60 cpu = <&cpu5>; 61 }; 62 core2 { 63 cpu = <&cpu6>; 64 }; 65 core3 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x000>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <741>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 78 }; 79 80 cpu1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x001>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <741>; 86 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 87 }; 88 89 cpu2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x002>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <741>; 95 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 96 }; 97 98 cpu3: cpu@3 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x003>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <741>; 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 105 }; 106 107 cpu4: cpu@100 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a73"; 110 reg = <0x100>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 114 }; 115 116 cpu5: cpu@101 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a73"; 119 reg = <0x101>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 123 }; 124 125 cpu6: cpu@102 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a73"; 128 reg = <0x102>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 132 }; 133 134 cpu7: cpu@103 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a73"; 137 reg = <0x103>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 141 }; 142 143 idle-states { 144 entry-method = "psci"; 145 146 CPU_SLEEP: cpu-sleep { 147 compatible = "arm,idle-state"; 148 local-timer-stop; 149 arm,psci-suspend-param = <0x00010001>; 150 entry-latency-us = <200>; 151 exit-latency-us = <200>; 152 min-residency-us = <800>; 153 }; 154 155 CLUSTER_SLEEP: cluster-sleep { 156 compatible = "arm,idle-state"; 157 local-timer-stop; 158 arm,psci-suspend-param = <0x01010001>; 159 entry-latency-us = <250>; 160 exit-latency-us = <400>; 161 min-residency-us = <1300>; 162 }; 163 }; 164 }; 165 166 pmu-a53 { 167 compatible = "arm,cortex-a53-pmu"; 168 interrupt-parent = <&gic>; 169 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 170 }; 171 172 pmu-a73 { 173 compatible = "arm,cortex-a73-pmu"; 174 interrupt-parent = <&gic>; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 clk26m: oscillator { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <26000000>; 187 clock-output-names = "clk26m"; 188 }; 189 190 timer { 191 compatible = "arm,armv8-timer"; 192 interrupt-parent = <&gic>; 193 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 194 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 195 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 196 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 197 }; 198 199 soc { 200 #address-cells = <2>; 201 #size-cells = <2>; 202 compatible = "simple-bus"; 203 ranges; 204 205 soc_data: soc_data@8000000 { 206 compatible = "mediatek,mt8183-efuse", 207 "mediatek,efuse"; 208 reg = <0 0x08000000 0 0x0010>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 status = "disabled"; 212 }; 213 214 gic: interrupt-controller@c000000 { 215 compatible = "arm,gic-v3"; 216 #interrupt-cells = <4>; 217 interrupt-parent = <&gic>; 218 interrupt-controller; 219 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 220 <0 0x0c100000 0 0x200000>, /* GICR */ 221 <0 0x0c400000 0 0x2000>, /* GICC */ 222 <0 0x0c410000 0 0x1000>, /* GICH */ 223 <0 0x0c420000 0 0x2000>; /* GICV */ 224 225 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 226 ppi-partitions { 227 ppi_cluster0: interrupt-partition-0 { 228 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 229 }; 230 ppi_cluster1: interrupt-partition-1 { 231 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 232 }; 233 }; 234 }; 235 236 mcucfg: syscon@c530000 { 237 compatible = "mediatek,mt8183-mcucfg", "syscon"; 238 reg = <0 0x0c530000 0 0x1000>; 239 #clock-cells = <1>; 240 }; 241 242 sysirq: interrupt-controller@c530a80 { 243 compatible = "mediatek,mt8183-sysirq", 244 "mediatek,mt6577-sysirq"; 245 interrupt-controller; 246 #interrupt-cells = <3>; 247 interrupt-parent = <&gic>; 248 reg = <0 0x0c530a80 0 0x50>; 249 }; 250 251 topckgen: syscon@10000000 { 252 compatible = "mediatek,mt8183-topckgen", "syscon"; 253 reg = <0 0x10000000 0 0x1000>; 254 #clock-cells = <1>; 255 }; 256 257 infracfg: syscon@10001000 { 258 compatible = "mediatek,mt8183-infracfg", "syscon"; 259 reg = <0 0x10001000 0 0x1000>; 260 #clock-cells = <1>; 261 #reset-cells = <1>; 262 }; 263 264 pio: pinctrl@10005000 { 265 compatible = "mediatek,mt8183-pinctrl"; 266 reg = <0 0x10005000 0 0x1000>, 267 <0 0x11f20000 0 0x1000>, 268 <0 0x11e80000 0 0x1000>, 269 <0 0x11e70000 0 0x1000>, 270 <0 0x11e90000 0 0x1000>, 271 <0 0x11d30000 0 0x1000>, 272 <0 0x11d20000 0 0x1000>, 273 <0 0x11c50000 0 0x1000>, 274 <0 0x11f30000 0 0x1000>, 275 <0 0x1000b000 0 0x1000>; 276 reg-names = "iocfg0", "iocfg1", "iocfg2", 277 "iocfg3", "iocfg4", "iocfg5", 278 "iocfg6", "iocfg7", "iocfg8", 279 "eint"; 280 gpio-controller; 281 #gpio-cells = <2>; 282 gpio-ranges = <&pio 0 0 192>; 283 interrupt-controller; 284 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 285 #interrupt-cells = <2>; 286 }; 287 288 watchdog: watchdog@10007000 { 289 compatible = "mediatek,mt8183-wdt", 290 "mediatek,mt6589-wdt"; 291 reg = <0 0x10007000 0 0x100>; 292 #reset-cells = <1>; 293 }; 294 295 apmixedsys: syscon@1000c000 { 296 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 297 reg = <0 0x1000c000 0 0x1000>; 298 #clock-cells = <1>; 299 }; 300 301 pwrap: pwrap@1000d000 { 302 compatible = "mediatek,mt8183-pwrap"; 303 reg = <0 0x1000d000 0 0x1000>; 304 reg-names = "pwrap"; 305 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 307 <&infracfg CLK_INFRA_PMIC_AP>; 308 clock-names = "spi", "wrap"; 309 }; 310 311 systimer: timer@10017000 { 312 compatible = "mediatek,mt8183-timer", 313 "mediatek,mt6765-timer"; 314 reg = <0 0x10017000 0 0x1000>; 315 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&topckgen CLK_TOP_CLK13M>; 317 clock-names = "clk13m"; 318 }; 319 320 gce: mailbox@10238000 { 321 compatible = "mediatek,mt8183-gce"; 322 reg = <0 0x10238000 0 0x4000>; 323 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 324 #mbox-cells = <3>; 325 clocks = <&infracfg CLK_INFRA_GCE>; 326 clock-names = "gce"; 327 }; 328 329 auxadc: auxadc@11001000 { 330 compatible = "mediatek,mt8183-auxadc", 331 "mediatek,mt8173-auxadc"; 332 reg = <0 0x11001000 0 0x1000>; 333 clocks = <&infracfg CLK_INFRA_AUXADC>; 334 clock-names = "main"; 335 #io-channel-cells = <1>; 336 status = "disabled"; 337 }; 338 339 uart0: serial@11002000 { 340 compatible = "mediatek,mt8183-uart", 341 "mediatek,mt6577-uart"; 342 reg = <0 0x11002000 0 0x1000>; 343 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 344 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 345 clock-names = "baud", "bus"; 346 status = "disabled"; 347 }; 348 349 uart1: serial@11003000 { 350 compatible = "mediatek,mt8183-uart", 351 "mediatek,mt6577-uart"; 352 reg = <0 0x11003000 0 0x1000>; 353 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 354 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 355 clock-names = "baud", "bus"; 356 status = "disabled"; 357 }; 358 359 uart2: serial@11004000 { 360 compatible = "mediatek,mt8183-uart", 361 "mediatek,mt6577-uart"; 362 reg = <0 0x11004000 0 0x1000>; 363 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 364 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 365 clock-names = "baud", "bus"; 366 status = "disabled"; 367 }; 368 369 i2c6: i2c@11005000 { 370 compatible = "mediatek,mt8183-i2c"; 371 reg = <0 0x11005000 0 0x1000>, 372 <0 0x11000600 0 0x80>; 373 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 374 clocks = <&infracfg CLK_INFRA_I2C6>, 375 <&infracfg CLK_INFRA_AP_DMA>; 376 clock-names = "main", "dma"; 377 clock-div = <1>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2c0: i2c@11007000 { 384 compatible = "mediatek,mt8183-i2c"; 385 reg = <0 0x11007000 0 0x1000>, 386 <0 0x11000080 0 0x80>; 387 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 388 clocks = <&infracfg CLK_INFRA_I2C0>, 389 <&infracfg CLK_INFRA_AP_DMA>; 390 clock-names = "main", "dma"; 391 clock-div = <1>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c4: i2c@11008000 { 398 compatible = "mediatek,mt8183-i2c"; 399 reg = <0 0x11008000 0 0x1000>, 400 <0 0x11000100 0 0x80>; 401 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&infracfg CLK_INFRA_I2C1>, 403 <&infracfg CLK_INFRA_AP_DMA>, 404 <&infracfg CLK_INFRA_I2C1_ARBITER>; 405 clock-names = "main", "dma","arb"; 406 clock-div = <1>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 status = "disabled"; 410 }; 411 412 i2c2: i2c@11009000 { 413 compatible = "mediatek,mt8183-i2c"; 414 reg = <0 0x11009000 0 0x1000>, 415 <0 0x11000280 0 0x80>; 416 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 417 clocks = <&infracfg CLK_INFRA_I2C2>, 418 <&infracfg CLK_INFRA_AP_DMA>, 419 <&infracfg CLK_INFRA_I2C2_ARBITER>; 420 clock-names = "main", "dma", "arb"; 421 clock-div = <1>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 427 spi0: spi@1100a000 { 428 compatible = "mediatek,mt8183-spi"; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 reg = <0 0x1100a000 0 0x1000>; 432 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 433 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 434 <&topckgen CLK_TOP_MUX_SPI>, 435 <&infracfg CLK_INFRA_SPI0>; 436 clock-names = "parent-clk", "sel-clk", "spi-clk"; 437 status = "disabled"; 438 }; 439 440 i2c3: i2c@1100f000 { 441 compatible = "mediatek,mt8183-i2c"; 442 reg = <0 0x1100f000 0 0x1000>, 443 <0 0x11000400 0 0x80>; 444 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 445 clocks = <&infracfg CLK_INFRA_I2C3>, 446 <&infracfg CLK_INFRA_AP_DMA>; 447 clock-names = "main", "dma"; 448 clock-div = <1>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 status = "disabled"; 452 }; 453 454 spi1: spi@11010000 { 455 compatible = "mediatek,mt8183-spi"; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 reg = <0 0x11010000 0 0x1000>; 459 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 460 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 461 <&topckgen CLK_TOP_MUX_SPI>, 462 <&infracfg CLK_INFRA_SPI1>; 463 clock-names = "parent-clk", "sel-clk", "spi-clk"; 464 status = "disabled"; 465 }; 466 467 i2c1: i2c@11011000 { 468 compatible = "mediatek,mt8183-i2c"; 469 reg = <0 0x11011000 0 0x1000>, 470 <0 0x11000480 0 0x80>; 471 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 472 clocks = <&infracfg CLK_INFRA_I2C4>, 473 <&infracfg CLK_INFRA_AP_DMA>; 474 clock-names = "main", "dma"; 475 clock-div = <1>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 status = "disabled"; 479 }; 480 481 spi2: spi@11012000 { 482 compatible = "mediatek,mt8183-spi"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 reg = <0 0x11012000 0 0x1000>; 486 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 487 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 488 <&topckgen CLK_TOP_MUX_SPI>, 489 <&infracfg CLK_INFRA_SPI2>; 490 clock-names = "parent-clk", "sel-clk", "spi-clk"; 491 status = "disabled"; 492 }; 493 494 spi3: spi@11013000 { 495 compatible = "mediatek,mt8183-spi"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <0 0x11013000 0 0x1000>; 499 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 500 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 501 <&topckgen CLK_TOP_MUX_SPI>, 502 <&infracfg CLK_INFRA_SPI3>; 503 clock-names = "parent-clk", "sel-clk", "spi-clk"; 504 status = "disabled"; 505 }; 506 507 i2c9: i2c@11014000 { 508 compatible = "mediatek,mt8183-i2c"; 509 reg = <0 0x11014000 0 0x1000>, 510 <0 0x11000180 0 0x80>; 511 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 512 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 513 <&infracfg CLK_INFRA_AP_DMA>, 514 <&infracfg CLK_INFRA_I2C1_ARBITER>; 515 clock-names = "main", "dma", "arb"; 516 clock-div = <1>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 i2c10: i2c@11015000 { 523 compatible = "mediatek,mt8183-i2c"; 524 reg = <0 0x11015000 0 0x1000>, 525 <0 0x11000300 0 0x80>; 526 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 527 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 528 <&infracfg CLK_INFRA_AP_DMA>, 529 <&infracfg CLK_INFRA_I2C2_ARBITER>; 530 clock-names = "main", "dma", "arb"; 531 clock-div = <1>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 537 i2c5: i2c@11016000 { 538 compatible = "mediatek,mt8183-i2c"; 539 reg = <0 0x11016000 0 0x1000>, 540 <0 0x11000500 0 0x80>; 541 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&infracfg CLK_INFRA_I2C5>, 543 <&infracfg CLK_INFRA_AP_DMA>, 544 <&infracfg CLK_INFRA_I2C5_ARBITER>; 545 clock-names = "main", "dma", "arb"; 546 clock-div = <1>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 i2c11: i2c@11017000 { 553 compatible = "mediatek,mt8183-i2c"; 554 reg = <0 0x11017000 0 0x1000>, 555 <0 0x11000580 0 0x80>; 556 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 557 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 558 <&infracfg CLK_INFRA_AP_DMA>, 559 <&infracfg CLK_INFRA_I2C5_ARBITER>; 560 clock-names = "main", "dma", "arb"; 561 clock-div = <1>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 spi4: spi@11018000 { 568 compatible = "mediatek,mt8183-spi"; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 reg = <0 0x11018000 0 0x1000>; 572 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 573 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 574 <&topckgen CLK_TOP_MUX_SPI>, 575 <&infracfg CLK_INFRA_SPI4>; 576 clock-names = "parent-clk", "sel-clk", "spi-clk"; 577 status = "disabled"; 578 }; 579 580 spi5: spi@11019000 { 581 compatible = "mediatek,mt8183-spi"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 reg = <0 0x11019000 0 0x1000>; 585 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 586 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 587 <&topckgen CLK_TOP_MUX_SPI>, 588 <&infracfg CLK_INFRA_SPI5>; 589 clock-names = "parent-clk", "sel-clk", "spi-clk"; 590 status = "disabled"; 591 }; 592 593 i2c7: i2c@1101a000 { 594 compatible = "mediatek,mt8183-i2c"; 595 reg = <0 0x1101a000 0 0x1000>, 596 <0 0x11000680 0 0x80>; 597 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 598 clocks = <&infracfg CLK_INFRA_I2C7>, 599 <&infracfg CLK_INFRA_AP_DMA>; 600 clock-names = "main", "dma"; 601 clock-div = <1>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 i2c8: i2c@1101b000 { 608 compatible = "mediatek,mt8183-i2c"; 609 reg = <0 0x1101b000 0 0x1000>, 610 <0 0x11000700 0 0x80>; 611 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 612 clocks = <&infracfg CLK_INFRA_I2C8>, 613 <&infracfg CLK_INFRA_AP_DMA>; 614 clock-names = "main", "dma"; 615 clock-div = <1>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 audiosys: syscon@11220000 { 622 compatible = "mediatek,mt8183-audiosys", "syscon"; 623 reg = <0 0x11220000 0 0x1000>; 624 #clock-cells = <1>; 625 }; 626 627 efuse: efuse@11f10000 { 628 compatible = "mediatek,mt8183-efuse", 629 "mediatek,efuse"; 630 reg = <0 0x11f10000 0 0x1000>; 631 }; 632 633 mfgcfg: syscon@13000000 { 634 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 635 reg = <0 0x13000000 0 0x1000>; 636 #clock-cells = <1>; 637 }; 638 639 mmsys: syscon@14000000 { 640 compatible = "mediatek,mt8183-mmsys", "syscon"; 641 reg = <0 0x14000000 0 0x1000>; 642 #clock-cells = <1>; 643 }; 644 645 imgsys: syscon@15020000 { 646 compatible = "mediatek,mt8183-imgsys", "syscon"; 647 reg = <0 0x15020000 0 0x1000>; 648 #clock-cells = <1>; 649 }; 650 651 vdecsys: syscon@16000000 { 652 compatible = "mediatek,mt8183-vdecsys", "syscon"; 653 reg = <0 0x16000000 0 0x1000>; 654 #clock-cells = <1>; 655 }; 656 657 vencsys: syscon@17000000 { 658 compatible = "mediatek,mt8183-vencsys", "syscon"; 659 reg = <0 0x17000000 0 0x1000>; 660 #clock-cells = <1>; 661 }; 662 663 ipu_conn: syscon@19000000 { 664 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 665 reg = <0 0x19000000 0 0x1000>; 666 #clock-cells = <1>; 667 }; 668 669 ipu_adl: syscon@19010000 { 670 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 671 reg = <0 0x19010000 0 0x1000>; 672 #clock-cells = <1>; 673 }; 674 675 ipu_core0: syscon@19180000 { 676 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 677 reg = <0 0x19180000 0 0x1000>; 678 #clock-cells = <1>; 679 }; 680 681 ipu_core1: syscon@19280000 { 682 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 683 reg = <0 0x19280000 0 0x1000>; 684 #clock-cells = <1>; 685 }; 686 687 camsys: syscon@1a000000 { 688 compatible = "mediatek,mt8183-camsys", "syscon"; 689 reg = <0 0x1a000000 0 0x1000>; 690 #clock-cells = <1>; 691 }; 692 }; 693}; 694