1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cpus { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 287 cpu-map { 288 cluster0 { 289 core0 { 290 cpu = <&cpu0>; 291 }; 292 core1 { 293 cpu = <&cpu1>; 294 }; 295 core2 { 296 cpu = <&cpu2>; 297 }; 298 core3 { 299 cpu = <&cpu3>; 300 }; 301 }; 302 303 cluster1 { 304 core0 { 305 cpu = <&cpu4>; 306 }; 307 core1 { 308 cpu = <&cpu5>; 309 }; 310 core2 { 311 cpu = <&cpu6>; 312 }; 313 core3 { 314 cpu = <&cpu7>; 315 }; 316 }; 317 }; 318 319 cpu0: cpu@0 { 320 device_type = "cpu"; 321 compatible = "arm,cortex-a53"; 322 reg = <0x000>; 323 enable-method = "psci"; 324 capacity-dmips-mhz = <741>; 325 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 326 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 327 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 328 clock-names = "cpu", "intermediate"; 329 operating-points-v2 = <&cluster0_opp>; 330 dynamic-power-coefficient = <84>; 331 #cooling-cells = <2>; 332 }; 333 334 cpu1: cpu@1 { 335 device_type = "cpu"; 336 compatible = "arm,cortex-a53"; 337 reg = <0x001>; 338 enable-method = "psci"; 339 capacity-dmips-mhz = <741>; 340 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 341 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 342 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 343 clock-names = "cpu", "intermediate"; 344 operating-points-v2 = <&cluster0_opp>; 345 dynamic-power-coefficient = <84>; 346 #cooling-cells = <2>; 347 }; 348 349 cpu2: cpu@2 { 350 device_type = "cpu"; 351 compatible = "arm,cortex-a53"; 352 reg = <0x002>; 353 enable-method = "psci"; 354 capacity-dmips-mhz = <741>; 355 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 356 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 357 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 358 clock-names = "cpu", "intermediate"; 359 operating-points-v2 = <&cluster0_opp>; 360 dynamic-power-coefficient = <84>; 361 #cooling-cells = <2>; 362 }; 363 364 cpu3: cpu@3 { 365 device_type = "cpu"; 366 compatible = "arm,cortex-a53"; 367 reg = <0x003>; 368 enable-method = "psci"; 369 capacity-dmips-mhz = <741>; 370 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 371 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 372 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 373 clock-names = "cpu", "intermediate"; 374 operating-points-v2 = <&cluster0_opp>; 375 dynamic-power-coefficient = <84>; 376 #cooling-cells = <2>; 377 }; 378 379 cpu4: cpu@100 { 380 device_type = "cpu"; 381 compatible = "arm,cortex-a73"; 382 reg = <0x100>; 383 enable-method = "psci"; 384 capacity-dmips-mhz = <1024>; 385 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 386 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 387 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 388 clock-names = "cpu", "intermediate"; 389 operating-points-v2 = <&cluster1_opp>; 390 dynamic-power-coefficient = <211>; 391 #cooling-cells = <2>; 392 }; 393 394 cpu5: cpu@101 { 395 device_type = "cpu"; 396 compatible = "arm,cortex-a73"; 397 reg = <0x101>; 398 enable-method = "psci"; 399 capacity-dmips-mhz = <1024>; 400 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 401 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 402 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 403 clock-names = "cpu", "intermediate"; 404 operating-points-v2 = <&cluster1_opp>; 405 dynamic-power-coefficient = <211>; 406 #cooling-cells = <2>; 407 }; 408 409 cpu6: cpu@102 { 410 device_type = "cpu"; 411 compatible = "arm,cortex-a73"; 412 reg = <0x102>; 413 enable-method = "psci"; 414 capacity-dmips-mhz = <1024>; 415 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 416 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 417 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 418 clock-names = "cpu", "intermediate"; 419 operating-points-v2 = <&cluster1_opp>; 420 dynamic-power-coefficient = <211>; 421 #cooling-cells = <2>; 422 }; 423 424 cpu7: cpu@103 { 425 device_type = "cpu"; 426 compatible = "arm,cortex-a73"; 427 reg = <0x103>; 428 enable-method = "psci"; 429 capacity-dmips-mhz = <1024>; 430 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 431 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 432 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 433 clock-names = "cpu", "intermediate"; 434 operating-points-v2 = <&cluster1_opp>; 435 dynamic-power-coefficient = <211>; 436 #cooling-cells = <2>; 437 }; 438 439 idle-states { 440 entry-method = "psci"; 441 442 CPU_SLEEP: cpu-sleep { 443 compatible = "arm,idle-state"; 444 local-timer-stop; 445 arm,psci-suspend-param = <0x00010001>; 446 entry-latency-us = <200>; 447 exit-latency-us = <200>; 448 min-residency-us = <800>; 449 }; 450 451 CLUSTER_SLEEP0: cluster-sleep-0 { 452 compatible = "arm,idle-state"; 453 local-timer-stop; 454 arm,psci-suspend-param = <0x01010001>; 455 entry-latency-us = <250>; 456 exit-latency-us = <400>; 457 min-residency-us = <1000>; 458 }; 459 CLUSTER_SLEEP1: cluster-sleep-1 { 460 compatible = "arm,idle-state"; 461 local-timer-stop; 462 arm,psci-suspend-param = <0x01010001>; 463 entry-latency-us = <250>; 464 exit-latency-us = <400>; 465 min-residency-us = <1300>; 466 }; 467 }; 468 }; 469 470 gpu_opp_table: opp-table-0 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 opp-300000000 { 475 opp-hz = /bits/ 64 <300000000>; 476 opp-microvolt = <625000>, <850000>; 477 }; 478 479 opp-320000000 { 480 opp-hz = /bits/ 64 <320000000>; 481 opp-microvolt = <631250>, <850000>; 482 }; 483 484 opp-340000000 { 485 opp-hz = /bits/ 64 <340000000>; 486 opp-microvolt = <637500>, <850000>; 487 }; 488 489 opp-360000000 { 490 opp-hz = /bits/ 64 <360000000>; 491 opp-microvolt = <643750>, <850000>; 492 }; 493 494 opp-380000000 { 495 opp-hz = /bits/ 64 <380000000>; 496 opp-microvolt = <650000>, <850000>; 497 }; 498 499 opp-400000000 { 500 opp-hz = /bits/ 64 <400000000>; 501 opp-microvolt = <656250>, <850000>; 502 }; 503 504 opp-420000000 { 505 opp-hz = /bits/ 64 <420000000>; 506 opp-microvolt = <662500>, <850000>; 507 }; 508 509 opp-460000000 { 510 opp-hz = /bits/ 64 <460000000>; 511 opp-microvolt = <675000>, <850000>; 512 }; 513 514 opp-500000000 { 515 opp-hz = /bits/ 64 <500000000>; 516 opp-microvolt = <687500>, <850000>; 517 }; 518 519 opp-540000000 { 520 opp-hz = /bits/ 64 <540000000>; 521 opp-microvolt = <700000>, <850000>; 522 }; 523 524 opp-580000000 { 525 opp-hz = /bits/ 64 <580000000>; 526 opp-microvolt = <712500>, <850000>; 527 }; 528 529 opp-620000000 { 530 opp-hz = /bits/ 64 <620000000>; 531 opp-microvolt = <725000>, <850000>; 532 }; 533 534 opp-653000000 { 535 opp-hz = /bits/ 64 <653000000>; 536 opp-microvolt = <743750>, <850000>; 537 }; 538 539 opp-698000000 { 540 opp-hz = /bits/ 64 <698000000>; 541 opp-microvolt = <768750>, <868750>; 542 }; 543 544 opp-743000000 { 545 opp-hz = /bits/ 64 <743000000>; 546 opp-microvolt = <793750>, <893750>; 547 }; 548 549 opp-800000000 { 550 opp-hz = /bits/ 64 <800000000>; 551 opp-microvolt = <825000>, <925000>; 552 }; 553 }; 554 555 pmu-a53 { 556 compatible = "arm,cortex-a53-pmu"; 557 interrupt-parent = <&gic>; 558 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 559 }; 560 561 pmu-a73 { 562 compatible = "arm,cortex-a73-pmu"; 563 interrupt-parent = <&gic>; 564 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 565 }; 566 567 psci { 568 compatible = "arm,psci-1.0"; 569 method = "smc"; 570 }; 571 572 clk26m: oscillator { 573 compatible = "fixed-clock"; 574 #clock-cells = <0>; 575 clock-frequency = <26000000>; 576 clock-output-names = "clk26m"; 577 }; 578 579 timer { 580 compatible = "arm,armv8-timer"; 581 interrupt-parent = <&gic>; 582 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 583 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 584 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 585 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 586 }; 587 588 soc { 589 #address-cells = <2>; 590 #size-cells = <2>; 591 compatible = "simple-bus"; 592 ranges; 593 594 soc_data: soc_data@8000000 { 595 compatible = "mediatek,mt8183-efuse", 596 "mediatek,efuse"; 597 reg = <0 0x08000000 0 0x0010>; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 status = "disabled"; 601 }; 602 603 gic: interrupt-controller@c000000 { 604 compatible = "arm,gic-v3"; 605 #interrupt-cells = <4>; 606 interrupt-parent = <&gic>; 607 interrupt-controller; 608 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 609 <0 0x0c100000 0 0x200000>, /* GICR */ 610 <0 0x0c400000 0 0x2000>, /* GICC */ 611 <0 0x0c410000 0 0x1000>, /* GICH */ 612 <0 0x0c420000 0 0x2000>; /* GICV */ 613 614 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 615 ppi-partitions { 616 ppi_cluster0: interrupt-partition-0 { 617 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 618 }; 619 ppi_cluster1: interrupt-partition-1 { 620 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 621 }; 622 }; 623 }; 624 625 mcucfg: syscon@c530000 { 626 compatible = "mediatek,mt8183-mcucfg", "syscon"; 627 reg = <0 0x0c530000 0 0x1000>; 628 #clock-cells = <1>; 629 }; 630 631 sysirq: interrupt-controller@c530a80 { 632 compatible = "mediatek,mt8183-sysirq", 633 "mediatek,mt6577-sysirq"; 634 interrupt-controller; 635 #interrupt-cells = <3>; 636 interrupt-parent = <&gic>; 637 reg = <0 0x0c530a80 0 0x50>; 638 }; 639 640 cpu_debug0: cpu-debug@d410000 { 641 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 642 reg = <0x0 0xd410000 0x0 0x1000>; 643 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 644 clock-names = "apb_pclk"; 645 cpu = <&cpu0>; 646 }; 647 648 cpu_debug1: cpu-debug@d510000 { 649 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 650 reg = <0x0 0xd510000 0x0 0x1000>; 651 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 652 clock-names = "apb_pclk"; 653 cpu = <&cpu1>; 654 }; 655 656 cpu_debug2: cpu-debug@d610000 { 657 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 658 reg = <0x0 0xd610000 0x0 0x1000>; 659 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 660 clock-names = "apb_pclk"; 661 cpu = <&cpu2>; 662 }; 663 664 cpu_debug3: cpu-debug@d710000 { 665 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 666 reg = <0x0 0xd710000 0x0 0x1000>; 667 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 668 clock-names = "apb_pclk"; 669 cpu = <&cpu3>; 670 }; 671 672 cpu_debug4: cpu-debug@d810000 { 673 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 674 reg = <0x0 0xd810000 0x0 0x1000>; 675 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 676 clock-names = "apb_pclk"; 677 cpu = <&cpu4>; 678 }; 679 680 cpu_debug5: cpu-debug@d910000 { 681 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 682 reg = <0x0 0xd910000 0x0 0x1000>; 683 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 684 clock-names = "apb_pclk"; 685 cpu = <&cpu5>; 686 }; 687 688 cpu_debug6: cpu-debug@da10000 { 689 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 690 reg = <0x0 0xda10000 0x0 0x1000>; 691 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 692 clock-names = "apb_pclk"; 693 cpu = <&cpu6>; 694 }; 695 696 cpu_debug7: cpu-debug@db10000 { 697 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 698 reg = <0x0 0xdb10000 0x0 0x1000>; 699 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 700 clock-names = "apb_pclk"; 701 cpu = <&cpu7>; 702 }; 703 704 topckgen: syscon@10000000 { 705 compatible = "mediatek,mt8183-topckgen", "syscon"; 706 reg = <0 0x10000000 0 0x1000>; 707 #clock-cells = <1>; 708 }; 709 710 infracfg: syscon@10001000 { 711 compatible = "mediatek,mt8183-infracfg", "syscon"; 712 reg = <0 0x10001000 0 0x1000>; 713 #clock-cells = <1>; 714 #reset-cells = <1>; 715 }; 716 717 pericfg: syscon@10003000 { 718 compatible = "mediatek,mt8183-pericfg", "syscon"; 719 reg = <0 0x10003000 0 0x1000>; 720 #clock-cells = <1>; 721 }; 722 723 pio: pinctrl@10005000 { 724 compatible = "mediatek,mt8183-pinctrl"; 725 reg = <0 0x10005000 0 0x1000>, 726 <0 0x11f20000 0 0x1000>, 727 <0 0x11e80000 0 0x1000>, 728 <0 0x11e70000 0 0x1000>, 729 <0 0x11e90000 0 0x1000>, 730 <0 0x11d30000 0 0x1000>, 731 <0 0x11d20000 0 0x1000>, 732 <0 0x11c50000 0 0x1000>, 733 <0 0x11f30000 0 0x1000>, 734 <0 0x1000b000 0 0x1000>; 735 reg-names = "iocfg0", "iocfg1", "iocfg2", 736 "iocfg3", "iocfg4", "iocfg5", 737 "iocfg6", "iocfg7", "iocfg8", 738 "eint"; 739 gpio-controller; 740 #gpio-cells = <2>; 741 gpio-ranges = <&pio 0 0 192>; 742 interrupt-controller; 743 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 744 #interrupt-cells = <2>; 745 }; 746 747 scpsys: syscon@10006000 { 748 compatible = "syscon", "simple-mfd"; 749 reg = <0 0x10006000 0 0x1000>; 750 #power-domain-cells = <1>; 751 752 /* System Power Manager */ 753 spm: power-controller { 754 compatible = "mediatek,mt8183-power-controller"; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 #power-domain-cells = <1>; 758 759 /* power domain of the SoC */ 760 power-domain@MT8183_POWER_DOMAIN_AUDIO { 761 reg = <MT8183_POWER_DOMAIN_AUDIO>; 762 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 763 <&infracfg CLK_INFRA_AUDIO>, 764 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 765 clock-names = "audio", "audio1", "audio2"; 766 #power-domain-cells = <0>; 767 }; 768 769 power-domain@MT8183_POWER_DOMAIN_CONN { 770 reg = <MT8183_POWER_DOMAIN_CONN>; 771 mediatek,infracfg = <&infracfg>; 772 #power-domain-cells = <0>; 773 }; 774 775 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 776 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 777 clocks = <&topckgen CLK_TOP_MUX_MFG>; 778 clock-names = "mfg"; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 #power-domain-cells = <1>; 782 783 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 784 reg = <MT8183_POWER_DOMAIN_MFG>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 #power-domain-cells = <1>; 788 789 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 790 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 791 #power-domain-cells = <0>; 792 }; 793 794 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 795 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 796 #power-domain-cells = <0>; 797 }; 798 799 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 800 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 801 mediatek,infracfg = <&infracfg>; 802 #power-domain-cells = <0>; 803 }; 804 }; 805 }; 806 807 power-domain@MT8183_POWER_DOMAIN_DISP { 808 reg = <MT8183_POWER_DOMAIN_DISP>; 809 clocks = <&topckgen CLK_TOP_MUX_MM>, 810 <&mmsys CLK_MM_SMI_COMMON>, 811 <&mmsys CLK_MM_SMI_LARB0>, 812 <&mmsys CLK_MM_SMI_LARB1>, 813 <&mmsys CLK_MM_GALS_COMM0>, 814 <&mmsys CLK_MM_GALS_COMM1>, 815 <&mmsys CLK_MM_GALS_CCU2MM>, 816 <&mmsys CLK_MM_GALS_IPU12MM>, 817 <&mmsys CLK_MM_GALS_IMG2MM>, 818 <&mmsys CLK_MM_GALS_CAM2MM>, 819 <&mmsys CLK_MM_GALS_IPU2MM>; 820 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 821 "mm-4", "mm-5", "mm-6", "mm-7", 822 "mm-8", "mm-9"; 823 mediatek,infracfg = <&infracfg>; 824 mediatek,smi = <&smi_common>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 #power-domain-cells = <1>; 828 829 power-domain@MT8183_POWER_DOMAIN_CAM { 830 reg = <MT8183_POWER_DOMAIN_CAM>; 831 clocks = <&topckgen CLK_TOP_MUX_CAM>, 832 <&camsys CLK_CAM_LARB6>, 833 <&camsys CLK_CAM_LARB3>, 834 <&camsys CLK_CAM_SENINF>, 835 <&camsys CLK_CAM_CAMSV0>, 836 <&camsys CLK_CAM_CAMSV1>, 837 <&camsys CLK_CAM_CAMSV2>, 838 <&camsys CLK_CAM_CCU>; 839 clock-names = "cam", "cam-0", "cam-1", 840 "cam-2", "cam-3", "cam-4", 841 "cam-5", "cam-6"; 842 mediatek,infracfg = <&infracfg>; 843 mediatek,smi = <&smi_common>; 844 #power-domain-cells = <0>; 845 }; 846 847 power-domain@MT8183_POWER_DOMAIN_ISP { 848 reg = <MT8183_POWER_DOMAIN_ISP>; 849 clocks = <&topckgen CLK_TOP_MUX_IMG>, 850 <&imgsys CLK_IMG_LARB5>, 851 <&imgsys CLK_IMG_LARB2>; 852 clock-names = "isp", "isp-0", "isp-1"; 853 mediatek,infracfg = <&infracfg>; 854 mediatek,smi = <&smi_common>; 855 #power-domain-cells = <0>; 856 }; 857 858 power-domain@MT8183_POWER_DOMAIN_VDEC { 859 reg = <MT8183_POWER_DOMAIN_VDEC>; 860 mediatek,smi = <&smi_common>; 861 #power-domain-cells = <0>; 862 }; 863 864 power-domain@MT8183_POWER_DOMAIN_VENC { 865 reg = <MT8183_POWER_DOMAIN_VENC>; 866 mediatek,smi = <&smi_common>; 867 #power-domain-cells = <0>; 868 }; 869 870 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 871 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 872 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 873 <&topckgen CLK_TOP_MUX_DSP>, 874 <&ipu_conn CLK_IPU_CONN_IPU>, 875 <&ipu_conn CLK_IPU_CONN_AHB>, 876 <&ipu_conn CLK_IPU_CONN_AXI>, 877 <&ipu_conn CLK_IPU_CONN_ISP>, 878 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 879 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 880 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 881 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 882 mediatek,infracfg = <&infracfg>; 883 mediatek,smi = <&smi_common>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 #power-domain-cells = <1>; 887 888 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 889 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 890 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 891 clock-names = "vpu2"; 892 mediatek,infracfg = <&infracfg>; 893 #power-domain-cells = <0>; 894 }; 895 896 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 897 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 898 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 899 clock-names = "vpu3"; 900 mediatek,infracfg = <&infracfg>; 901 #power-domain-cells = <0>; 902 }; 903 }; 904 }; 905 }; 906 }; 907 908 watchdog: watchdog@10007000 { 909 compatible = "mediatek,mt8183-wdt"; 910 reg = <0 0x10007000 0 0x100>; 911 #reset-cells = <1>; 912 }; 913 914 apmixedsys: syscon@1000c000 { 915 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 916 reg = <0 0x1000c000 0 0x1000>; 917 #clock-cells = <1>; 918 }; 919 920 pwrap: pwrap@1000d000 { 921 compatible = "mediatek,mt8183-pwrap"; 922 reg = <0 0x1000d000 0 0x1000>; 923 reg-names = "pwrap"; 924 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 926 <&infracfg CLK_INFRA_PMIC_AP>; 927 clock-names = "spi", "wrap"; 928 }; 929 930 scp: scp@10500000 { 931 compatible = "mediatek,mt8183-scp"; 932 reg = <0 0x10500000 0 0x80000>, 933 <0 0x105c0000 0 0x19080>; 934 reg-names = "sram", "cfg"; 935 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&infracfg CLK_INFRA_SCPSYS>; 937 clock-names = "main"; 938 memory-region = <&scp_mem_reserved>; 939 status = "disabled"; 940 }; 941 942 systimer: timer@10017000 { 943 compatible = "mediatek,mt8183-timer", 944 "mediatek,mt6765-timer"; 945 reg = <0 0x10017000 0 0x1000>; 946 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&topckgen CLK_TOP_CLK13M>; 948 clock-names = "clk13m"; 949 }; 950 951 iommu: iommu@10205000 { 952 compatible = "mediatek,mt8183-m4u"; 953 reg = <0 0x10205000 0 0x1000>; 954 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 955 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 956 <&larb4>, <&larb5>, <&larb6>; 957 #iommu-cells = <1>; 958 }; 959 960 gce: mailbox@10238000 { 961 compatible = "mediatek,mt8183-gce"; 962 reg = <0 0x10238000 0 0x4000>; 963 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 964 #mbox-cells = <2>; 965 clocks = <&infracfg CLK_INFRA_GCE>; 966 clock-names = "gce"; 967 }; 968 969 auxadc: auxadc@11001000 { 970 compatible = "mediatek,mt8183-auxadc", 971 "mediatek,mt8173-auxadc"; 972 reg = <0 0x11001000 0 0x1000>; 973 clocks = <&infracfg CLK_INFRA_AUXADC>; 974 clock-names = "main"; 975 #io-channel-cells = <1>; 976 status = "disabled"; 977 }; 978 979 uart0: serial@11002000 { 980 compatible = "mediatek,mt8183-uart", 981 "mediatek,mt6577-uart"; 982 reg = <0 0x11002000 0 0x1000>; 983 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 984 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 985 clock-names = "baud", "bus"; 986 status = "disabled"; 987 }; 988 989 uart1: serial@11003000 { 990 compatible = "mediatek,mt8183-uart", 991 "mediatek,mt6577-uart"; 992 reg = <0 0x11003000 0 0x1000>; 993 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 994 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 995 clock-names = "baud", "bus"; 996 status = "disabled"; 997 }; 998 999 uart2: serial@11004000 { 1000 compatible = "mediatek,mt8183-uart", 1001 "mediatek,mt6577-uart"; 1002 reg = <0 0x11004000 0 0x1000>; 1003 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1004 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1005 clock-names = "baud", "bus"; 1006 status = "disabled"; 1007 }; 1008 1009 i2c6: i2c@11005000 { 1010 compatible = "mediatek,mt8183-i2c"; 1011 reg = <0 0x11005000 0 0x1000>, 1012 <0 0x11000600 0 0x80>; 1013 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1014 clocks = <&infracfg CLK_INFRA_I2C6>, 1015 <&infracfg CLK_INFRA_AP_DMA>; 1016 clock-names = "main", "dma"; 1017 clock-div = <1>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 i2c0: i2c@11007000 { 1024 compatible = "mediatek,mt8183-i2c"; 1025 reg = <0 0x11007000 0 0x1000>, 1026 <0 0x11000080 0 0x80>; 1027 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1028 clocks = <&infracfg CLK_INFRA_I2C0>, 1029 <&infracfg CLK_INFRA_AP_DMA>; 1030 clock-names = "main", "dma"; 1031 clock-div = <1>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c4: i2c@11008000 { 1038 compatible = "mediatek,mt8183-i2c"; 1039 reg = <0 0x11008000 0 0x1000>, 1040 <0 0x11000100 0 0x80>; 1041 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1042 clocks = <&infracfg CLK_INFRA_I2C1>, 1043 <&infracfg CLK_INFRA_AP_DMA>, 1044 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1045 clock-names = "main", "dma","arb"; 1046 clock-div = <1>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 status = "disabled"; 1050 }; 1051 1052 i2c2: i2c@11009000 { 1053 compatible = "mediatek,mt8183-i2c"; 1054 reg = <0 0x11009000 0 0x1000>, 1055 <0 0x11000280 0 0x80>; 1056 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1057 clocks = <&infracfg CLK_INFRA_I2C2>, 1058 <&infracfg CLK_INFRA_AP_DMA>, 1059 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1060 clock-names = "main", "dma", "arb"; 1061 clock-div = <1>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 spi0: spi@1100a000 { 1068 compatible = "mediatek,mt8183-spi"; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 reg = <0 0x1100a000 0 0x1000>; 1072 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1073 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1074 <&topckgen CLK_TOP_MUX_SPI>, 1075 <&infracfg CLK_INFRA_SPI0>; 1076 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1077 status = "disabled"; 1078 }; 1079 1080 thermal: thermal@1100b000 { 1081 #thermal-sensor-cells = <1>; 1082 compatible = "mediatek,mt8183-thermal"; 1083 reg = <0 0x1100b000 0 0x1000>; 1084 clocks = <&infracfg CLK_INFRA_THERM>, 1085 <&infracfg CLK_INFRA_AUXADC>; 1086 clock-names = "therm", "auxadc"; 1087 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1088 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1089 mediatek,auxadc = <&auxadc>; 1090 mediatek,apmixedsys = <&apmixedsys>; 1091 nvmem-cells = <&thermal_calibration>; 1092 nvmem-cell-names = "calibration-data"; 1093 }; 1094 1095 thermal_zones: thermal-zones { 1096 cpu_thermal: cpu-thermal { 1097 polling-delay-passive = <100>; 1098 polling-delay = <500>; 1099 thermal-sensors = <&thermal 0>; 1100 sustainable-power = <5000>; 1101 1102 trips { 1103 threshold: trip-point0 { 1104 temperature = <68000>; 1105 hysteresis = <2000>; 1106 type = "passive"; 1107 }; 1108 1109 target: trip-point1 { 1110 temperature = <80000>; 1111 hysteresis = <2000>; 1112 type = "passive"; 1113 }; 1114 1115 cpu_crit: cpu-crit { 1116 temperature = <115000>; 1117 hysteresis = <2000>; 1118 type = "critical"; 1119 }; 1120 }; 1121 1122 cooling-maps { 1123 map0 { 1124 trip = <&target>; 1125 cooling-device = <&cpu0 1126 THERMAL_NO_LIMIT 1127 THERMAL_NO_LIMIT>, 1128 <&cpu1 1129 THERMAL_NO_LIMIT 1130 THERMAL_NO_LIMIT>, 1131 <&cpu2 1132 THERMAL_NO_LIMIT 1133 THERMAL_NO_LIMIT>, 1134 <&cpu3 1135 THERMAL_NO_LIMIT 1136 THERMAL_NO_LIMIT>; 1137 contribution = <3072>; 1138 }; 1139 map1 { 1140 trip = <&target>; 1141 cooling-device = <&cpu4 1142 THERMAL_NO_LIMIT 1143 THERMAL_NO_LIMIT>, 1144 <&cpu5 1145 THERMAL_NO_LIMIT 1146 THERMAL_NO_LIMIT>, 1147 <&cpu6 1148 THERMAL_NO_LIMIT 1149 THERMAL_NO_LIMIT>, 1150 <&cpu7 1151 THERMAL_NO_LIMIT 1152 THERMAL_NO_LIMIT>; 1153 contribution = <1024>; 1154 }; 1155 }; 1156 }; 1157 1158 /* The tzts1 ~ tzts6 don't need to polling */ 1159 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 1160 1161 tzts1: tzts1 { 1162 polling-delay-passive = <0>; 1163 polling-delay = <0>; 1164 thermal-sensors = <&thermal 1>; 1165 sustainable-power = <5000>; 1166 trips {}; 1167 cooling-maps {}; 1168 }; 1169 1170 tzts2: tzts2 { 1171 polling-delay-passive = <0>; 1172 polling-delay = <0>; 1173 thermal-sensors = <&thermal 2>; 1174 sustainable-power = <5000>; 1175 trips {}; 1176 cooling-maps {}; 1177 }; 1178 1179 tzts3: tzts3 { 1180 polling-delay-passive = <0>; 1181 polling-delay = <0>; 1182 thermal-sensors = <&thermal 3>; 1183 sustainable-power = <5000>; 1184 trips {}; 1185 cooling-maps {}; 1186 }; 1187 1188 tzts4: tzts4 { 1189 polling-delay-passive = <0>; 1190 polling-delay = <0>; 1191 thermal-sensors = <&thermal 4>; 1192 sustainable-power = <5000>; 1193 trips {}; 1194 cooling-maps {}; 1195 }; 1196 1197 tzts5: tzts5 { 1198 polling-delay-passive = <0>; 1199 polling-delay = <0>; 1200 thermal-sensors = <&thermal 5>; 1201 sustainable-power = <5000>; 1202 trips {}; 1203 cooling-maps {}; 1204 }; 1205 1206 tztsABB: tztsABB { 1207 polling-delay-passive = <0>; 1208 polling-delay = <0>; 1209 thermal-sensors = <&thermal 6>; 1210 sustainable-power = <5000>; 1211 trips {}; 1212 cooling-maps {}; 1213 }; 1214 }; 1215 1216 pwm0: pwm@1100e000 { 1217 compatible = "mediatek,mt8183-disp-pwm"; 1218 reg = <0 0x1100e000 0 0x1000>; 1219 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1220 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1221 #pwm-cells = <2>; 1222 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1223 <&infracfg CLK_INFRA_DISP_PWM>; 1224 clock-names = "main", "mm"; 1225 }; 1226 1227 pwm1: pwm@11006000 { 1228 compatible = "mediatek,mt8183-pwm"; 1229 reg = <0 0x11006000 0 0x1000>; 1230 #pwm-cells = <2>; 1231 clocks = <&infracfg CLK_INFRA_PWM>, 1232 <&infracfg CLK_INFRA_PWM_HCLK>, 1233 <&infracfg CLK_INFRA_PWM1>, 1234 <&infracfg CLK_INFRA_PWM2>, 1235 <&infracfg CLK_INFRA_PWM3>, 1236 <&infracfg CLK_INFRA_PWM4>; 1237 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1238 "pwm4"; 1239 }; 1240 1241 i2c3: i2c@1100f000 { 1242 compatible = "mediatek,mt8183-i2c"; 1243 reg = <0 0x1100f000 0 0x1000>, 1244 <0 0x11000400 0 0x80>; 1245 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1246 clocks = <&infracfg CLK_INFRA_I2C3>, 1247 <&infracfg CLK_INFRA_AP_DMA>; 1248 clock-names = "main", "dma"; 1249 clock-div = <1>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 spi1: spi@11010000 { 1256 compatible = "mediatek,mt8183-spi"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 reg = <0 0x11010000 0 0x1000>; 1260 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1261 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1262 <&topckgen CLK_TOP_MUX_SPI>, 1263 <&infracfg CLK_INFRA_SPI1>; 1264 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1265 status = "disabled"; 1266 }; 1267 1268 i2c1: i2c@11011000 { 1269 compatible = "mediatek,mt8183-i2c"; 1270 reg = <0 0x11011000 0 0x1000>, 1271 <0 0x11000480 0 0x80>; 1272 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1273 clocks = <&infracfg CLK_INFRA_I2C4>, 1274 <&infracfg CLK_INFRA_AP_DMA>; 1275 clock-names = "main", "dma"; 1276 clock-div = <1>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 status = "disabled"; 1280 }; 1281 1282 spi2: spi@11012000 { 1283 compatible = "mediatek,mt8183-spi"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 reg = <0 0x11012000 0 0x1000>; 1287 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1288 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1289 <&topckgen CLK_TOP_MUX_SPI>, 1290 <&infracfg CLK_INFRA_SPI2>; 1291 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1292 status = "disabled"; 1293 }; 1294 1295 spi3: spi@11013000 { 1296 compatible = "mediatek,mt8183-spi"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 reg = <0 0x11013000 0 0x1000>; 1300 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1301 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1302 <&topckgen CLK_TOP_MUX_SPI>, 1303 <&infracfg CLK_INFRA_SPI3>; 1304 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1305 status = "disabled"; 1306 }; 1307 1308 i2c9: i2c@11014000 { 1309 compatible = "mediatek,mt8183-i2c"; 1310 reg = <0 0x11014000 0 0x1000>, 1311 <0 0x11000180 0 0x80>; 1312 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1313 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1314 <&infracfg CLK_INFRA_AP_DMA>, 1315 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1316 clock-names = "main", "dma", "arb"; 1317 clock-div = <1>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 i2c10: i2c@11015000 { 1324 compatible = "mediatek,mt8183-i2c"; 1325 reg = <0 0x11015000 0 0x1000>, 1326 <0 0x11000300 0 0x80>; 1327 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1328 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1329 <&infracfg CLK_INFRA_AP_DMA>, 1330 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1331 clock-names = "main", "dma", "arb"; 1332 clock-div = <1>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 i2c5: i2c@11016000 { 1339 compatible = "mediatek,mt8183-i2c"; 1340 reg = <0 0x11016000 0 0x1000>, 1341 <0 0x11000500 0 0x80>; 1342 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1343 clocks = <&infracfg CLK_INFRA_I2C5>, 1344 <&infracfg CLK_INFRA_AP_DMA>, 1345 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1346 clock-names = "main", "dma", "arb"; 1347 clock-div = <1>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 i2c11: i2c@11017000 { 1354 compatible = "mediatek,mt8183-i2c"; 1355 reg = <0 0x11017000 0 0x1000>, 1356 <0 0x11000580 0 0x80>; 1357 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1358 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1359 <&infracfg CLK_INFRA_AP_DMA>, 1360 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1361 clock-names = "main", "dma", "arb"; 1362 clock-div = <1>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 1368 spi4: spi@11018000 { 1369 compatible = "mediatek,mt8183-spi"; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 reg = <0 0x11018000 0 0x1000>; 1373 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1374 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1375 <&topckgen CLK_TOP_MUX_SPI>, 1376 <&infracfg CLK_INFRA_SPI4>; 1377 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1378 status = "disabled"; 1379 }; 1380 1381 spi5: spi@11019000 { 1382 compatible = "mediatek,mt8183-spi"; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 reg = <0 0x11019000 0 0x1000>; 1386 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1387 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1388 <&topckgen CLK_TOP_MUX_SPI>, 1389 <&infracfg CLK_INFRA_SPI5>; 1390 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1391 status = "disabled"; 1392 }; 1393 1394 i2c7: i2c@1101a000 { 1395 compatible = "mediatek,mt8183-i2c"; 1396 reg = <0 0x1101a000 0 0x1000>, 1397 <0 0x11000680 0 0x80>; 1398 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1399 clocks = <&infracfg CLK_INFRA_I2C7>, 1400 <&infracfg CLK_INFRA_AP_DMA>; 1401 clock-names = "main", "dma"; 1402 clock-div = <1>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 i2c8: i2c@1101b000 { 1409 compatible = "mediatek,mt8183-i2c"; 1410 reg = <0 0x1101b000 0 0x1000>, 1411 <0 0x11000700 0 0x80>; 1412 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1413 clocks = <&infracfg CLK_INFRA_I2C8>, 1414 <&infracfg CLK_INFRA_AP_DMA>; 1415 clock-names = "main", "dma"; 1416 clock-div = <1>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 ssusb: usb@11201000 { 1423 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 1424 reg = <0 0x11201000 0 0x2e00>, 1425 <0 0x11203e00 0 0x0100>; 1426 reg-names = "mac", "ippc"; 1427 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1428 phys = <&u2port0 PHY_TYPE_USB2>, 1429 <&u3port0 PHY_TYPE_USB3>; 1430 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1431 <&infracfg CLK_INFRA_USB>; 1432 clock-names = "sys_ck", "ref_ck"; 1433 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1434 #address-cells = <2>; 1435 #size-cells = <2>; 1436 ranges; 1437 status = "disabled"; 1438 1439 usb_host: usb@11200000 { 1440 compatible = "mediatek,mt8183-xhci", 1441 "mediatek,mtk-xhci"; 1442 reg = <0 0x11200000 0 0x1000>; 1443 reg-names = "mac"; 1444 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1445 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1446 <&infracfg CLK_INFRA_USB>; 1447 clock-names = "sys_ck", "ref_ck"; 1448 status = "disabled"; 1449 }; 1450 }; 1451 1452 audiosys: audio-controller@11220000 { 1453 compatible = "mediatek,mt8183-audiosys", "syscon"; 1454 reg = <0 0x11220000 0 0x1000>; 1455 #clock-cells = <1>; 1456 afe: mt8183-afe-pcm { 1457 compatible = "mediatek,mt8183-audio"; 1458 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1459 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1460 reset-names = "audiosys"; 1461 power-domains = 1462 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1463 clocks = <&audiosys CLK_AUDIO_AFE>, 1464 <&audiosys CLK_AUDIO_DAC>, 1465 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1466 <&audiosys CLK_AUDIO_ADC>, 1467 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1468 <&audiosys CLK_AUDIO_22M>, 1469 <&audiosys CLK_AUDIO_24M>, 1470 <&audiosys CLK_AUDIO_APLL_TUNER>, 1471 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1472 <&audiosys CLK_AUDIO_I2S1>, 1473 <&audiosys CLK_AUDIO_I2S2>, 1474 <&audiosys CLK_AUDIO_I2S3>, 1475 <&audiosys CLK_AUDIO_I2S4>, 1476 <&audiosys CLK_AUDIO_TDM>, 1477 <&audiosys CLK_AUDIO_TML>, 1478 <&infracfg CLK_INFRA_AUDIO>, 1479 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1480 <&topckgen CLK_TOP_MUX_AUDIO>, 1481 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1482 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1483 <&topckgen CLK_TOP_MUX_AUD_1>, 1484 <&topckgen CLK_TOP_APLL1_CK>, 1485 <&topckgen CLK_TOP_MUX_AUD_2>, 1486 <&topckgen CLK_TOP_APLL2_CK>, 1487 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1488 <&topckgen CLK_TOP_APLL1_D8>, 1489 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1490 <&topckgen CLK_TOP_APLL2_D8>, 1491 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1492 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1493 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1494 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1495 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1496 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1497 <&topckgen CLK_TOP_APLL12_DIV0>, 1498 <&topckgen CLK_TOP_APLL12_DIV1>, 1499 <&topckgen CLK_TOP_APLL12_DIV2>, 1500 <&topckgen CLK_TOP_APLL12_DIV3>, 1501 <&topckgen CLK_TOP_APLL12_DIV4>, 1502 <&topckgen CLK_TOP_APLL12_DIVB>, 1503 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1504 <&clk26m>; 1505 clock-names = "aud_afe_clk", 1506 "aud_dac_clk", 1507 "aud_dac_predis_clk", 1508 "aud_adc_clk", 1509 "aud_adc_adda6_clk", 1510 "aud_apll22m_clk", 1511 "aud_apll24m_clk", 1512 "aud_apll1_tuner_clk", 1513 "aud_apll2_tuner_clk", 1514 "aud_i2s1_bclk_sw", 1515 "aud_i2s2_bclk_sw", 1516 "aud_i2s3_bclk_sw", 1517 "aud_i2s4_bclk_sw", 1518 "aud_tdm_clk", 1519 "aud_tml_clk", 1520 "aud_infra_clk", 1521 "mtkaif_26m_clk", 1522 "top_mux_audio", 1523 "top_mux_aud_intbus", 1524 "top_syspll_d2_d4", 1525 "top_mux_aud_1", 1526 "top_apll1_ck", 1527 "top_mux_aud_2", 1528 "top_apll2_ck", 1529 "top_mux_aud_eng1", 1530 "top_apll1_d8", 1531 "top_mux_aud_eng2", 1532 "top_apll2_d8", 1533 "top_i2s0_m_sel", 1534 "top_i2s1_m_sel", 1535 "top_i2s2_m_sel", 1536 "top_i2s3_m_sel", 1537 "top_i2s4_m_sel", 1538 "top_i2s5_m_sel", 1539 "top_apll12_div0", 1540 "top_apll12_div1", 1541 "top_apll12_div2", 1542 "top_apll12_div3", 1543 "top_apll12_div4", 1544 "top_apll12_divb", 1545 /*"top_apll12_div5",*/ 1546 "top_clk26m_clk"; 1547 }; 1548 }; 1549 1550 mmc0: mmc@11230000 { 1551 compatible = "mediatek,mt8183-mmc"; 1552 reg = <0 0x11230000 0 0x1000>, 1553 <0 0x11f50000 0 0x1000>; 1554 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1555 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1556 <&infracfg CLK_INFRA_MSDC0>, 1557 <&infracfg CLK_INFRA_MSDC0_SCK>; 1558 clock-names = "source", "hclk", "source_cg"; 1559 status = "disabled"; 1560 }; 1561 1562 mmc1: mmc@11240000 { 1563 compatible = "mediatek,mt8183-mmc"; 1564 reg = <0 0x11240000 0 0x1000>, 1565 <0 0x11e10000 0 0x1000>; 1566 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1567 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1568 <&infracfg CLK_INFRA_MSDC1>, 1569 <&infracfg CLK_INFRA_MSDC1_SCK>; 1570 clock-names = "source", "hclk", "source_cg"; 1571 status = "disabled"; 1572 }; 1573 1574 mipi_tx0: dsi-phy@11e50000 { 1575 compatible = "mediatek,mt8183-mipi-tx"; 1576 reg = <0 0x11e50000 0 0x1000>; 1577 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1578 #clock-cells = <0>; 1579 #phy-cells = <0>; 1580 clock-output-names = "mipi_tx0_pll"; 1581 nvmem-cells = <&mipi_tx_calibration>; 1582 nvmem-cell-names = "calibration-data"; 1583 }; 1584 1585 efuse: efuse@11f10000 { 1586 compatible = "mediatek,mt8183-efuse", 1587 "mediatek,efuse"; 1588 reg = <0 0x11f10000 0 0x1000>; 1589 #address-cells = <1>; 1590 #size-cells = <1>; 1591 thermal_calibration: calib@180 { 1592 reg = <0x180 0xc>; 1593 }; 1594 1595 mipi_tx_calibration: calib@190 { 1596 reg = <0x190 0xc>; 1597 }; 1598 }; 1599 1600 u3phy: t-phy@11f40000 { 1601 compatible = "mediatek,mt8183-tphy", 1602 "mediatek,generic-tphy-v2"; 1603 #address-cells = <1>; 1604 #size-cells = <1>; 1605 ranges = <0 0 0x11f40000 0x1000>; 1606 status = "okay"; 1607 1608 u2port0: usb-phy@0 { 1609 reg = <0x0 0x700>; 1610 clocks = <&clk26m>; 1611 clock-names = "ref"; 1612 #phy-cells = <1>; 1613 mediatek,discth = <15>; 1614 status = "okay"; 1615 }; 1616 1617 u3port0: usb-phy@700 { 1618 reg = <0x0700 0x900>; 1619 clocks = <&clk26m>; 1620 clock-names = "ref"; 1621 #phy-cells = <1>; 1622 status = "okay"; 1623 }; 1624 }; 1625 1626 mfgcfg: syscon@13000000 { 1627 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1628 reg = <0 0x13000000 0 0x1000>; 1629 #clock-cells = <1>; 1630 }; 1631 1632 gpu: gpu@13040000 { 1633 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; 1634 reg = <0 0x13040000 0 0x4000>; 1635 interrupts = 1636 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1637 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1638 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1639 interrupt-names = "job", "mmu", "gpu"; 1640 1641 clocks = <&topckgen CLK_TOP_MFGPLL_CK>; 1642 1643 power-domains = 1644 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1645 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1646 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1647 power-domain-names = "core0", "core1", "core2"; 1648 1649 operating-points-v2 = <&gpu_opp_table>; 1650 }; 1651 1652 mmsys: syscon@14000000 { 1653 compatible = "mediatek,mt8183-mmsys", "syscon"; 1654 reg = <0 0x14000000 0 0x1000>; 1655 #clock-cells = <1>; 1656 #reset-cells = <1>; 1657 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1658 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1659 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1660 }; 1661 1662 ovl0: ovl@14008000 { 1663 compatible = "mediatek,mt8183-disp-ovl"; 1664 reg = <0 0x14008000 0 0x1000>; 1665 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1666 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1667 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1668 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1669 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1670 }; 1671 1672 ovl_2l0: ovl@14009000 { 1673 compatible = "mediatek,mt8183-disp-ovl-2l"; 1674 reg = <0 0x14009000 0 0x1000>; 1675 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1676 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1677 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1678 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1679 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1680 }; 1681 1682 ovl_2l1: ovl@1400a000 { 1683 compatible = "mediatek,mt8183-disp-ovl-2l"; 1684 reg = <0 0x1400a000 0 0x1000>; 1685 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1686 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1687 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1688 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1689 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1690 }; 1691 1692 rdma0: rdma@1400b000 { 1693 compatible = "mediatek,mt8183-disp-rdma"; 1694 reg = <0 0x1400b000 0 0x1000>; 1695 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1696 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1697 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1698 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1699 mediatek,rdma-fifo-size = <5120>; 1700 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1701 }; 1702 1703 rdma1: rdma@1400c000 { 1704 compatible = "mediatek,mt8183-disp-rdma"; 1705 reg = <0 0x1400c000 0 0x1000>; 1706 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1707 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1708 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1709 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1710 mediatek,rdma-fifo-size = <2048>; 1711 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1712 }; 1713 1714 color0: color@1400e000 { 1715 compatible = "mediatek,mt8183-disp-color", 1716 "mediatek,mt8173-disp-color"; 1717 reg = <0 0x1400e000 0 0x1000>; 1718 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1719 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1720 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1721 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1722 }; 1723 1724 ccorr0: ccorr@1400f000 { 1725 compatible = "mediatek,mt8183-disp-ccorr"; 1726 reg = <0 0x1400f000 0 0x1000>; 1727 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1728 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1729 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1730 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1731 }; 1732 1733 aal0: aal@14010000 { 1734 compatible = "mediatek,mt8183-disp-aal"; 1735 reg = <0 0x14010000 0 0x1000>; 1736 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1737 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1738 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1739 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1740 }; 1741 1742 gamma0: gamma@14011000 { 1743 compatible = "mediatek,mt8183-disp-gamma"; 1744 reg = <0 0x14011000 0 0x1000>; 1745 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1746 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1747 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1748 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1749 }; 1750 1751 dither0: dither@14012000 { 1752 compatible = "mediatek,mt8183-disp-dither"; 1753 reg = <0 0x14012000 0 0x1000>; 1754 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1755 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1756 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1757 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1758 }; 1759 1760 dsi0: dsi@14014000 { 1761 compatible = "mediatek,mt8183-dsi"; 1762 reg = <0 0x14014000 0 0x1000>; 1763 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1764 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1765 clocks = <&mmsys CLK_MM_DSI0_MM>, 1766 <&mmsys CLK_MM_DSI0_IF>, 1767 <&mipi_tx0>; 1768 clock-names = "engine", "digital", "hs"; 1769 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 1770 phys = <&mipi_tx0>; 1771 phy-names = "dphy"; 1772 }; 1773 1774 mutex: mutex@14016000 { 1775 compatible = "mediatek,mt8183-disp-mutex"; 1776 reg = <0 0x14016000 0 0x1000>; 1777 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1778 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1779 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1780 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1781 }; 1782 1783 larb0: larb@14017000 { 1784 compatible = "mediatek,mt8183-smi-larb"; 1785 reg = <0 0x14017000 0 0x1000>; 1786 mediatek,smi = <&smi_common>; 1787 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1788 <&mmsys CLK_MM_SMI_LARB0>; 1789 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1790 clock-names = "apb", "smi"; 1791 }; 1792 1793 smi_common: smi@14019000 { 1794 compatible = "mediatek,mt8183-smi-common"; 1795 reg = <0 0x14019000 0 0x1000>; 1796 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1797 <&mmsys CLK_MM_SMI_COMMON>, 1798 <&mmsys CLK_MM_GALS_COMM0>, 1799 <&mmsys CLK_MM_GALS_COMM1>; 1800 clock-names = "apb", "smi", "gals0", "gals1"; 1801 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1802 }; 1803 1804 imgsys: syscon@15020000 { 1805 compatible = "mediatek,mt8183-imgsys", "syscon"; 1806 reg = <0 0x15020000 0 0x1000>; 1807 #clock-cells = <1>; 1808 }; 1809 1810 larb5: larb@15021000 { 1811 compatible = "mediatek,mt8183-smi-larb"; 1812 reg = <0 0x15021000 0 0x1000>; 1813 mediatek,smi = <&smi_common>; 1814 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1815 <&mmsys CLK_MM_GALS_IMG2MM>; 1816 clock-names = "apb", "smi", "gals"; 1817 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1818 }; 1819 1820 larb2: larb@1502f000 { 1821 compatible = "mediatek,mt8183-smi-larb"; 1822 reg = <0 0x1502f000 0 0x1000>; 1823 mediatek,smi = <&smi_common>; 1824 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1825 <&mmsys CLK_MM_GALS_IPU2MM>; 1826 clock-names = "apb", "smi", "gals"; 1827 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1828 }; 1829 1830 vdecsys: syscon@16000000 { 1831 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1832 reg = <0 0x16000000 0 0x1000>; 1833 #clock-cells = <1>; 1834 }; 1835 1836 larb1: larb@16010000 { 1837 compatible = "mediatek,mt8183-smi-larb"; 1838 reg = <0 0x16010000 0 0x1000>; 1839 mediatek,smi = <&smi_common>; 1840 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1841 clock-names = "apb", "smi"; 1842 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1843 }; 1844 1845 vencsys: syscon@17000000 { 1846 compatible = "mediatek,mt8183-vencsys", "syscon"; 1847 reg = <0 0x17000000 0 0x1000>; 1848 #clock-cells = <1>; 1849 }; 1850 1851 larb4: larb@17010000 { 1852 compatible = "mediatek,mt8183-smi-larb"; 1853 reg = <0 0x17010000 0 0x1000>; 1854 mediatek,smi = <&smi_common>; 1855 clocks = <&vencsys CLK_VENC_LARB>, 1856 <&vencsys CLK_VENC_LARB>; 1857 clock-names = "apb", "smi"; 1858 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1859 }; 1860 1861 venc_jpg: venc_jpg@17030000 { 1862 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 1863 reg = <0 0x17030000 0 0x1000>; 1864 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 1865 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 1866 <&iommu M4U_PORT_JPGENC_BSDMA>; 1867 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1868 clocks = <&vencsys CLK_VENC_JPGENC>; 1869 clock-names = "jpgenc"; 1870 }; 1871 1872 ipu_conn: syscon@19000000 { 1873 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1874 reg = <0 0x19000000 0 0x1000>; 1875 #clock-cells = <1>; 1876 }; 1877 1878 ipu_adl: syscon@19010000 { 1879 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1880 reg = <0 0x19010000 0 0x1000>; 1881 #clock-cells = <1>; 1882 }; 1883 1884 ipu_core0: syscon@19180000 { 1885 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1886 reg = <0 0x19180000 0 0x1000>; 1887 #clock-cells = <1>; 1888 }; 1889 1890 ipu_core1: syscon@19280000 { 1891 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1892 reg = <0 0x19280000 0 0x1000>; 1893 #clock-cells = <1>; 1894 }; 1895 1896 camsys: syscon@1a000000 { 1897 compatible = "mediatek,mt8183-camsys", "syscon"; 1898 reg = <0 0x1a000000 0 0x1000>; 1899 #clock-cells = <1>; 1900 }; 1901 1902 larb6: larb@1a001000 { 1903 compatible = "mediatek,mt8183-smi-larb"; 1904 reg = <0 0x1a001000 0 0x1000>; 1905 mediatek,smi = <&smi_common>; 1906 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1907 <&mmsys CLK_MM_GALS_CAM2MM>; 1908 clock-names = "apb", "smi", "gals"; 1909 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1910 }; 1911 1912 larb3: larb@1a002000 { 1913 compatible = "mediatek,mt8183-smi-larb"; 1914 reg = <0 0x1a002000 0 0x1000>; 1915 mediatek,smi = <&smi_common>; 1916 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1917 <&mmsys CLK_MM_GALS_IPU12MM>; 1918 clock-names = "apb", "smi", "gals"; 1919 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1920 }; 1921 }; 1922}; 1923