1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/gce/mt8173-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8183-larb-port.h>
13#include <dt-bindings/power/mt8183-power.h>
14#include <dt-bindings/reset-controller/mt8183-resets.h>
15#include <dt-bindings/phy/phy.h>
16#include "mt8183-pinfunc.h"
17
18/ {
19	compatible = "mediatek,mt8183";
20	interrupt-parent = <&sysirq>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	aliases {
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		i2c2 = &i2c2;
28		i2c3 = &i2c3;
29		i2c4 = &i2c4;
30		i2c5 = &i2c5;
31		i2c6 = &i2c6;
32		i2c7 = &i2c7;
33		i2c8 = &i2c8;
34		i2c9 = &i2c9;
35		i2c10 = &i2c10;
36		i2c11 = &i2c11;
37		ovl0 = &ovl0;
38		ovl-2l0 = &ovl_2l0;
39		ovl-2l1 = &ovl_2l1;
40		rdma0 = &rdma0;
41		rdma1 = &rdma1;
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		cpu-map {
49			cluster0 {
50				core0 {
51					cpu = <&cpu0>;
52				};
53				core1 {
54					cpu = <&cpu1>;
55				};
56				core2 {
57					cpu = <&cpu2>;
58				};
59				core3 {
60					cpu = <&cpu3>;
61				};
62			};
63
64			cluster1 {
65				core0 {
66					cpu = <&cpu4>;
67				};
68				core1 {
69					cpu = <&cpu5>;
70				};
71				core2 {
72					cpu = <&cpu6>;
73				};
74				core3 {
75					cpu = <&cpu7>;
76				};
77			};
78		};
79
80		cpu0: cpu@0 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53";
83			reg = <0x000>;
84			enable-method = "psci";
85			capacity-dmips-mhz = <741>;
86			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
87			dynamic-power-coefficient = <84>;
88			#cooling-cells = <2>;
89		};
90
91		cpu1: cpu@1 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a53";
94			reg = <0x001>;
95			enable-method = "psci";
96			capacity-dmips-mhz = <741>;
97			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
98			dynamic-power-coefficient = <84>;
99			#cooling-cells = <2>;
100		};
101
102		cpu2: cpu@2 {
103			device_type = "cpu";
104			compatible = "arm,cortex-a53";
105			reg = <0x002>;
106			enable-method = "psci";
107			capacity-dmips-mhz = <741>;
108			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
109			dynamic-power-coefficient = <84>;
110			#cooling-cells = <2>;
111		};
112
113		cpu3: cpu@3 {
114			device_type = "cpu";
115			compatible = "arm,cortex-a53";
116			reg = <0x003>;
117			enable-method = "psci";
118			capacity-dmips-mhz = <741>;
119			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
120			dynamic-power-coefficient = <84>;
121			#cooling-cells = <2>;
122		};
123
124		cpu4: cpu@100 {
125			device_type = "cpu";
126			compatible = "arm,cortex-a73";
127			reg = <0x100>;
128			enable-method = "psci";
129			capacity-dmips-mhz = <1024>;
130			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
131			dynamic-power-coefficient = <211>;
132			#cooling-cells = <2>;
133		};
134
135		cpu5: cpu@101 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a73";
138			reg = <0x101>;
139			enable-method = "psci";
140			capacity-dmips-mhz = <1024>;
141			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
142			dynamic-power-coefficient = <211>;
143			#cooling-cells = <2>;
144		};
145
146		cpu6: cpu@102 {
147			device_type = "cpu";
148			compatible = "arm,cortex-a73";
149			reg = <0x102>;
150			enable-method = "psci";
151			capacity-dmips-mhz = <1024>;
152			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
153			dynamic-power-coefficient = <211>;
154			#cooling-cells = <2>;
155		};
156
157		cpu7: cpu@103 {
158			device_type = "cpu";
159			compatible = "arm,cortex-a73";
160			reg = <0x103>;
161			enable-method = "psci";
162			capacity-dmips-mhz = <1024>;
163			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
164			dynamic-power-coefficient = <211>;
165			#cooling-cells = <2>;
166		};
167
168		idle-states {
169			entry-method = "psci";
170
171			CPU_SLEEP: cpu-sleep {
172				compatible = "arm,idle-state";
173				local-timer-stop;
174				arm,psci-suspend-param = <0x00010001>;
175				entry-latency-us = <200>;
176				exit-latency-us = <200>;
177				min-residency-us = <800>;
178			};
179
180			CLUSTER_SLEEP0: cluster-sleep-0 {
181				compatible = "arm,idle-state";
182				local-timer-stop;
183				arm,psci-suspend-param = <0x01010001>;
184				entry-latency-us = <250>;
185				exit-latency-us = <400>;
186				min-residency-us = <1000>;
187			};
188			CLUSTER_SLEEP1: cluster-sleep-1 {
189				compatible = "arm,idle-state";
190				local-timer-stop;
191				arm,psci-suspend-param = <0x01010001>;
192				entry-latency-us = <250>;
193				exit-latency-us = <400>;
194				min-residency-us = <1300>;
195			};
196		};
197	};
198
199	pmu-a53 {
200		compatible = "arm,cortex-a53-pmu";
201		interrupt-parent = <&gic>;
202		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
203	};
204
205	pmu-a73 {
206		compatible = "arm,cortex-a73-pmu";
207		interrupt-parent = <&gic>;
208		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
209	};
210
211	psci {
212		compatible      = "arm,psci-1.0";
213		method          = "smc";
214	};
215
216	clk26m: oscillator {
217		compatible = "fixed-clock";
218		#clock-cells = <0>;
219		clock-frequency = <26000000>;
220		clock-output-names = "clk26m";
221	};
222
223	timer {
224		compatible = "arm,armv8-timer";
225		interrupt-parent = <&gic>;
226		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
227			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
228			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
229			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
230	};
231
232	soc {
233		#address-cells = <2>;
234		#size-cells = <2>;
235		compatible = "simple-bus";
236		ranges;
237
238		soc_data: soc_data@8000000 {
239			compatible = "mediatek,mt8183-efuse",
240				     "mediatek,efuse";
241			reg = <0 0x08000000 0 0x0010>;
242			#address-cells = <1>;
243			#size-cells = <1>;
244			status = "disabled";
245		};
246
247		gic: interrupt-controller@c000000 {
248			compatible = "arm,gic-v3";
249			#interrupt-cells = <4>;
250			interrupt-parent = <&gic>;
251			interrupt-controller;
252			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
253			      <0 0x0c100000 0 0x200000>, /* GICR */
254			      <0 0x0c400000 0 0x2000>,   /* GICC */
255			      <0 0x0c410000 0 0x1000>,   /* GICH */
256			      <0 0x0c420000 0 0x2000>;   /* GICV */
257
258			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
259			ppi-partitions {
260				ppi_cluster0: interrupt-partition-0 {
261					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
262				};
263				ppi_cluster1: interrupt-partition-1 {
264					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
265				};
266			};
267		};
268
269		mcucfg: syscon@c530000 {
270			compatible = "mediatek,mt8183-mcucfg", "syscon";
271			reg = <0 0x0c530000 0 0x1000>;
272			#clock-cells = <1>;
273		};
274
275		sysirq: interrupt-controller@c530a80 {
276			compatible = "mediatek,mt8183-sysirq",
277				     "mediatek,mt6577-sysirq";
278			interrupt-controller;
279			#interrupt-cells = <3>;
280			interrupt-parent = <&gic>;
281			reg = <0 0x0c530a80 0 0x50>;
282		};
283
284		topckgen: syscon@10000000 {
285			compatible = "mediatek,mt8183-topckgen", "syscon";
286			reg = <0 0x10000000 0 0x1000>;
287			#clock-cells = <1>;
288		};
289
290		infracfg: syscon@10001000 {
291			compatible = "mediatek,mt8183-infracfg", "syscon";
292			reg = <0 0x10001000 0 0x1000>;
293			#clock-cells = <1>;
294			#reset-cells = <1>;
295		};
296
297		pericfg: syscon@10003000 {
298			compatible = "mediatek,mt8183-pericfg", "syscon";
299			reg = <0 0x10003000 0 0x1000>;
300			#clock-cells = <1>;
301		};
302
303		pio: pinctrl@10005000 {
304			compatible = "mediatek,mt8183-pinctrl";
305			reg = <0 0x10005000 0 0x1000>,
306			      <0 0x11f20000 0 0x1000>,
307			      <0 0x11e80000 0 0x1000>,
308			      <0 0x11e70000 0 0x1000>,
309			      <0 0x11e90000 0 0x1000>,
310			      <0 0x11d30000 0 0x1000>,
311			      <0 0x11d20000 0 0x1000>,
312			      <0 0x11c50000 0 0x1000>,
313			      <0 0x11f30000 0 0x1000>,
314			      <0 0x1000b000 0 0x1000>;
315			reg-names = "iocfg0", "iocfg1", "iocfg2",
316				    "iocfg3", "iocfg4", "iocfg5",
317				    "iocfg6", "iocfg7", "iocfg8",
318				    "eint";
319			gpio-controller;
320			#gpio-cells = <2>;
321			gpio-ranges = <&pio 0 0 192>;
322			interrupt-controller;
323			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
324			#interrupt-cells = <2>;
325		};
326
327		scpsys: syscon@10006000 {
328			compatible = "syscon", "simple-mfd";
329			reg = <0 0x10006000 0 0x1000>;
330			#power-domain-cells = <1>;
331
332			/* System Power Manager */
333			spm: power-controller {
334				compatible = "mediatek,mt8183-power-controller";
335				#address-cells = <1>;
336				#size-cells = <0>;
337				#power-domain-cells = <1>;
338
339				/* power domain of the SoC */
340				power-domain@MT8183_POWER_DOMAIN_AUDIO {
341					reg = <MT8183_POWER_DOMAIN_AUDIO>;
342					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
343						 <&infracfg CLK_INFRA_AUDIO>,
344						 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
345					clock-names = "audio", "audio1", "audio2";
346					#power-domain-cells = <0>;
347				};
348
349				power-domain@MT8183_POWER_DOMAIN_CONN {
350					reg = <MT8183_POWER_DOMAIN_CONN>;
351					mediatek,infracfg = <&infracfg>;
352					#power-domain-cells = <0>;
353				};
354
355				power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
356					reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
357					clocks =  <&topckgen CLK_TOP_MUX_MFG>;
358					clock-names = "mfg";
359					#address-cells = <1>;
360					#size-cells = <0>;
361					#power-domain-cells = <1>;
362
363					power-domain@MT8183_POWER_DOMAIN_MFG {
364						reg = <MT8183_POWER_DOMAIN_MFG>;
365						#address-cells = <1>;
366						#size-cells = <0>;
367						#power-domain-cells = <1>;
368
369						power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
370							reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
371							#power-domain-cells = <0>;
372						};
373
374						power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
375							reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
376							#power-domain-cells = <0>;
377						};
378
379						power-domain@MT8183_POWER_DOMAIN_MFG_2D {
380							reg = <MT8183_POWER_DOMAIN_MFG_2D>;
381							mediatek,infracfg = <&infracfg>;
382							#power-domain-cells = <0>;
383						};
384					};
385				};
386
387				power-domain@MT8183_POWER_DOMAIN_DISP {
388					reg = <MT8183_POWER_DOMAIN_DISP>;
389					clocks = <&topckgen CLK_TOP_MUX_MM>,
390						 <&mmsys CLK_MM_SMI_COMMON>,
391						 <&mmsys CLK_MM_SMI_LARB0>,
392						 <&mmsys CLK_MM_SMI_LARB1>,
393						 <&mmsys CLK_MM_GALS_COMM0>,
394						 <&mmsys CLK_MM_GALS_COMM1>,
395						 <&mmsys CLK_MM_GALS_CCU2MM>,
396						 <&mmsys CLK_MM_GALS_IPU12MM>,
397						 <&mmsys CLK_MM_GALS_IMG2MM>,
398						 <&mmsys CLK_MM_GALS_CAM2MM>,
399						 <&mmsys CLK_MM_GALS_IPU2MM>;
400					clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
401						      "mm-4", "mm-5", "mm-6", "mm-7",
402						      "mm-8", "mm-9";
403					mediatek,infracfg = <&infracfg>;
404					mediatek,smi = <&smi_common>;
405					#address-cells = <1>;
406					#size-cells = <0>;
407					#power-domain-cells = <1>;
408
409					power-domain@MT8183_POWER_DOMAIN_CAM {
410						reg = <MT8183_POWER_DOMAIN_CAM>;
411						clocks = <&topckgen CLK_TOP_MUX_CAM>,
412							 <&camsys CLK_CAM_LARB6>,
413							 <&camsys CLK_CAM_LARB3>,
414							 <&camsys CLK_CAM_SENINF>,
415							 <&camsys CLK_CAM_CAMSV0>,
416							 <&camsys CLK_CAM_CAMSV1>,
417							 <&camsys CLK_CAM_CAMSV2>,
418							 <&camsys CLK_CAM_CCU>;
419						clock-names = "cam", "cam-0", "cam-1",
420							      "cam-2", "cam-3", "cam-4",
421							      "cam-5", "cam-6";
422						mediatek,infracfg = <&infracfg>;
423						mediatek,smi = <&smi_common>;
424						#power-domain-cells = <0>;
425					};
426
427					power-domain@MT8183_POWER_DOMAIN_ISP {
428						reg = <MT8183_POWER_DOMAIN_ISP>;
429						clocks = <&topckgen CLK_TOP_MUX_IMG>,
430							 <&imgsys CLK_IMG_LARB5>,
431							 <&imgsys CLK_IMG_LARB2>;
432						clock-names = "isp", "isp-0", "isp-1";
433						mediatek,infracfg = <&infracfg>;
434						mediatek,smi = <&smi_common>;
435						#power-domain-cells = <0>;
436					};
437
438					power-domain@MT8183_POWER_DOMAIN_VDEC {
439						reg = <MT8183_POWER_DOMAIN_VDEC>;
440						mediatek,smi = <&smi_common>;
441						#power-domain-cells = <0>;
442					};
443
444					power-domain@MT8183_POWER_DOMAIN_VENC {
445						reg = <MT8183_POWER_DOMAIN_VENC>;
446						mediatek,smi = <&smi_common>;
447						#power-domain-cells = <0>;
448					};
449
450					power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
451						reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
452						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
453							 <&topckgen CLK_TOP_MUX_DSP>,
454							 <&ipu_conn CLK_IPU_CONN_IPU>,
455							 <&ipu_conn CLK_IPU_CONN_AHB>,
456							 <&ipu_conn CLK_IPU_CONN_AXI>,
457							 <&ipu_conn CLK_IPU_CONN_ISP>,
458							 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
459							 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
460						clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
461							      "vpu-2", "vpu-3", "vpu-4", "vpu-5";
462						mediatek,infracfg = <&infracfg>;
463						mediatek,smi = <&smi_common>;
464						#address-cells = <1>;
465						#size-cells = <0>;
466						#power-domain-cells = <1>;
467
468						power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
469							reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
470							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
471							clock-names = "vpu2";
472							mediatek,infracfg = <&infracfg>;
473							#power-domain-cells = <0>;
474						};
475
476						power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
477							reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
478							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
479							clock-names = "vpu3";
480							mediatek,infracfg = <&infracfg>;
481							#power-domain-cells = <0>;
482						};
483					};
484				};
485			};
486		};
487
488		watchdog: watchdog@10007000 {
489			compatible = "mediatek,mt8183-wdt";
490			reg = <0 0x10007000 0 0x100>;
491			#reset-cells = <1>;
492		};
493
494		apmixedsys: syscon@1000c000 {
495			compatible = "mediatek,mt8183-apmixedsys", "syscon";
496			reg = <0 0x1000c000 0 0x1000>;
497			#clock-cells = <1>;
498		};
499
500		pwrap: pwrap@1000d000 {
501			compatible = "mediatek,mt8183-pwrap";
502			reg = <0 0x1000d000 0 0x1000>;
503			reg-names = "pwrap";
504			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
505			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
506				 <&infracfg CLK_INFRA_PMIC_AP>;
507			clock-names = "spi", "wrap";
508		};
509
510		scp: scp@10500000 {
511			compatible = "mediatek,mt8183-scp";
512			reg = <0 0x10500000 0 0x80000>,
513			      <0 0x105c0000 0 0x19080>;
514			reg-names = "sram", "cfg";
515			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
516			clocks = <&infracfg CLK_INFRA_SCPSYS>;
517			clock-names = "main";
518			memory-region = <&scp_mem_reserved>;
519			status = "disabled";
520		};
521
522		systimer: timer@10017000 {
523			compatible = "mediatek,mt8183-timer",
524				     "mediatek,mt6765-timer";
525			reg = <0 0x10017000 0 0x1000>;
526			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
527			clocks = <&topckgen CLK_TOP_CLK13M>;
528			clock-names = "clk13m";
529		};
530
531		iommu: iommu@10205000 {
532			compatible = "mediatek,mt8183-m4u";
533			reg = <0 0x10205000 0 0x1000>;
534			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
535			mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
536					  &larb4 &larb5 &larb6>;
537			#iommu-cells = <1>;
538		};
539
540		gce: mailbox@10238000 {
541			compatible = "mediatek,mt8183-gce";
542			reg = <0 0x10238000 0 0x4000>;
543			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
544			#mbox-cells = <2>;
545			clocks = <&infracfg CLK_INFRA_GCE>;
546			clock-names = "gce";
547		};
548
549		auxadc: auxadc@11001000 {
550			compatible = "mediatek,mt8183-auxadc",
551				     "mediatek,mt8173-auxadc";
552			reg = <0 0x11001000 0 0x1000>;
553			clocks = <&infracfg CLK_INFRA_AUXADC>;
554			clock-names = "main";
555			#io-channel-cells = <1>;
556			status = "disabled";
557		};
558
559		uart0: serial@11002000 {
560			compatible = "mediatek,mt8183-uart",
561				     "mediatek,mt6577-uart";
562			reg = <0 0x11002000 0 0x1000>;
563			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
564			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
565			clock-names = "baud", "bus";
566			status = "disabled";
567		};
568
569		uart1: serial@11003000 {
570			compatible = "mediatek,mt8183-uart",
571				     "mediatek,mt6577-uart";
572			reg = <0 0x11003000 0 0x1000>;
573			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
574			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
575			clock-names = "baud", "bus";
576			status = "disabled";
577		};
578
579		uart2: serial@11004000 {
580			compatible = "mediatek,mt8183-uart",
581				     "mediatek,mt6577-uart";
582			reg = <0 0x11004000 0 0x1000>;
583			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
584			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
585			clock-names = "baud", "bus";
586			status = "disabled";
587		};
588
589		i2c6: i2c@11005000 {
590			compatible = "mediatek,mt8183-i2c";
591			reg = <0 0x11005000 0 0x1000>,
592			      <0 0x11000600 0 0x80>;
593			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
594			clocks = <&infracfg CLK_INFRA_I2C6>,
595				 <&infracfg CLK_INFRA_AP_DMA>;
596			clock-names = "main", "dma";
597			clock-div = <1>;
598			#address-cells = <1>;
599			#size-cells = <0>;
600			status = "disabled";
601		};
602
603		i2c0: i2c@11007000 {
604			compatible = "mediatek,mt8183-i2c";
605			reg = <0 0x11007000 0 0x1000>,
606			      <0 0x11000080 0 0x80>;
607			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
608			clocks = <&infracfg CLK_INFRA_I2C0>,
609				 <&infracfg CLK_INFRA_AP_DMA>;
610			clock-names = "main", "dma";
611			clock-div = <1>;
612			#address-cells = <1>;
613			#size-cells = <0>;
614			status = "disabled";
615		};
616
617		i2c4: i2c@11008000 {
618			compatible = "mediatek,mt8183-i2c";
619			reg = <0 0x11008000 0 0x1000>,
620			      <0 0x11000100 0 0x80>;
621			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
622			clocks = <&infracfg CLK_INFRA_I2C1>,
623				 <&infracfg CLK_INFRA_AP_DMA>,
624				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
625			clock-names = "main", "dma","arb";
626			clock-div = <1>;
627			#address-cells = <1>;
628			#size-cells = <0>;
629			status = "disabled";
630		};
631
632		i2c2: i2c@11009000 {
633			compatible = "mediatek,mt8183-i2c";
634			reg = <0 0x11009000 0 0x1000>,
635			      <0 0x11000280 0 0x80>;
636			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
637			clocks = <&infracfg CLK_INFRA_I2C2>,
638				 <&infracfg CLK_INFRA_AP_DMA>,
639				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
640			clock-names = "main", "dma", "arb";
641			clock-div = <1>;
642			#address-cells = <1>;
643			#size-cells = <0>;
644			status = "disabled";
645		};
646
647		spi0: spi@1100a000 {
648			compatible = "mediatek,mt8183-spi";
649			#address-cells = <1>;
650			#size-cells = <0>;
651			reg = <0 0x1100a000 0 0x1000>;
652			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
653			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
654				 <&topckgen CLK_TOP_MUX_SPI>,
655				 <&infracfg CLK_INFRA_SPI0>;
656			clock-names = "parent-clk", "sel-clk", "spi-clk";
657			status = "disabled";
658		};
659
660		pwm0: pwm@1100e000 {
661			compatible = "mediatek,mt8183-disp-pwm";
662			reg = <0 0x1100e000 0 0x1000>;
663			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
664			#pwm-cells = <2>;
665			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
666					<&infracfg CLK_INFRA_DISP_PWM>;
667			clock-names = "main", "mm";
668		};
669
670		i2c3: i2c@1100f000 {
671			compatible = "mediatek,mt8183-i2c";
672			reg = <0 0x1100f000 0 0x1000>,
673			      <0 0x11000400 0 0x80>;
674			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
675			clocks = <&infracfg CLK_INFRA_I2C3>,
676				 <&infracfg CLK_INFRA_AP_DMA>;
677			clock-names = "main", "dma";
678			clock-div = <1>;
679			#address-cells = <1>;
680			#size-cells = <0>;
681			status = "disabled";
682		};
683
684		spi1: spi@11010000 {
685			compatible = "mediatek,mt8183-spi";
686			#address-cells = <1>;
687			#size-cells = <0>;
688			reg = <0 0x11010000 0 0x1000>;
689			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
690			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
691				 <&topckgen CLK_TOP_MUX_SPI>,
692				 <&infracfg CLK_INFRA_SPI1>;
693			clock-names = "parent-clk", "sel-clk", "spi-clk";
694			status = "disabled";
695		};
696
697		i2c1: i2c@11011000 {
698			compatible = "mediatek,mt8183-i2c";
699			reg = <0 0x11011000 0 0x1000>,
700			      <0 0x11000480 0 0x80>;
701			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
702			clocks = <&infracfg CLK_INFRA_I2C4>,
703				 <&infracfg CLK_INFRA_AP_DMA>;
704			clock-names = "main", "dma";
705			clock-div = <1>;
706			#address-cells = <1>;
707			#size-cells = <0>;
708			status = "disabled";
709		};
710
711		spi2: spi@11012000 {
712			compatible = "mediatek,mt8183-spi";
713			#address-cells = <1>;
714			#size-cells = <0>;
715			reg = <0 0x11012000 0 0x1000>;
716			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
717			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
718				 <&topckgen CLK_TOP_MUX_SPI>,
719				 <&infracfg CLK_INFRA_SPI2>;
720			clock-names = "parent-clk", "sel-clk", "spi-clk";
721			status = "disabled";
722		};
723
724		spi3: spi@11013000 {
725			compatible = "mediatek,mt8183-spi";
726			#address-cells = <1>;
727			#size-cells = <0>;
728			reg = <0 0x11013000 0 0x1000>;
729			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
730			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
731				 <&topckgen CLK_TOP_MUX_SPI>,
732				 <&infracfg CLK_INFRA_SPI3>;
733			clock-names = "parent-clk", "sel-clk", "spi-clk";
734			status = "disabled";
735		};
736
737		i2c9: i2c@11014000 {
738			compatible = "mediatek,mt8183-i2c";
739			reg = <0 0x11014000 0 0x1000>,
740			      <0 0x11000180 0 0x80>;
741			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
742			clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
743				 <&infracfg CLK_INFRA_AP_DMA>,
744				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
745			clock-names = "main", "dma", "arb";
746			clock-div = <1>;
747			#address-cells = <1>;
748			#size-cells = <0>;
749			status = "disabled";
750		};
751
752		i2c10: i2c@11015000 {
753			compatible = "mediatek,mt8183-i2c";
754			reg = <0 0x11015000 0 0x1000>,
755			      <0 0x11000300 0 0x80>;
756			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
757			clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
758				 <&infracfg CLK_INFRA_AP_DMA>,
759				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
760			clock-names = "main", "dma", "arb";
761			clock-div = <1>;
762			#address-cells = <1>;
763			#size-cells = <0>;
764			status = "disabled";
765		};
766
767		i2c5: i2c@11016000 {
768			compatible = "mediatek,mt8183-i2c";
769			reg = <0 0x11016000 0 0x1000>,
770			      <0 0x11000500 0 0x80>;
771			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
772			clocks = <&infracfg CLK_INFRA_I2C5>,
773				 <&infracfg CLK_INFRA_AP_DMA>,
774				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
775			clock-names = "main", "dma", "arb";
776			clock-div = <1>;
777			#address-cells = <1>;
778			#size-cells = <0>;
779			status = "disabled";
780		};
781
782		i2c11: i2c@11017000 {
783			compatible = "mediatek,mt8183-i2c";
784			reg = <0 0x11017000 0 0x1000>,
785			      <0 0x11000580 0 0x80>;
786			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
787			clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
788				 <&infracfg CLK_INFRA_AP_DMA>,
789				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
790			clock-names = "main", "dma", "arb";
791			clock-div = <1>;
792			#address-cells = <1>;
793			#size-cells = <0>;
794			status = "disabled";
795		};
796
797		spi4: spi@11018000 {
798			compatible = "mediatek,mt8183-spi";
799			#address-cells = <1>;
800			#size-cells = <0>;
801			reg = <0 0x11018000 0 0x1000>;
802			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
803			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
804				 <&topckgen CLK_TOP_MUX_SPI>,
805				 <&infracfg CLK_INFRA_SPI4>;
806			clock-names = "parent-clk", "sel-clk", "spi-clk";
807			status = "disabled";
808		};
809
810		spi5: spi@11019000 {
811			compatible = "mediatek,mt8183-spi";
812			#address-cells = <1>;
813			#size-cells = <0>;
814			reg = <0 0x11019000 0 0x1000>;
815			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
816			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
817				 <&topckgen CLK_TOP_MUX_SPI>,
818				 <&infracfg CLK_INFRA_SPI5>;
819			clock-names = "parent-clk", "sel-clk", "spi-clk";
820			status = "disabled";
821		};
822
823		i2c7: i2c@1101a000 {
824			compatible = "mediatek,mt8183-i2c";
825			reg = <0 0x1101a000 0 0x1000>,
826			      <0 0x11000680 0 0x80>;
827			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
828			clocks = <&infracfg CLK_INFRA_I2C7>,
829				 <&infracfg CLK_INFRA_AP_DMA>;
830			clock-names = "main", "dma";
831			clock-div = <1>;
832			#address-cells = <1>;
833			#size-cells = <0>;
834			status = "disabled";
835		};
836
837		i2c8: i2c@1101b000 {
838			compatible = "mediatek,mt8183-i2c";
839			reg = <0 0x1101b000 0 0x1000>,
840			      <0 0x11000700 0 0x80>;
841			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
842			clocks = <&infracfg CLK_INFRA_I2C8>,
843				 <&infracfg CLK_INFRA_AP_DMA>;
844			clock-names = "main", "dma";
845			clock-div = <1>;
846			#address-cells = <1>;
847			#size-cells = <0>;
848			status = "disabled";
849		};
850
851		ssusb: usb@11201000 {
852			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
853			reg = <0 0x11201000 0 0x2e00>,
854			      <0 0x11203e00 0 0x0100>;
855			reg-names = "mac", "ippc";
856			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
857			phys = <&u2port0 PHY_TYPE_USB2>,
858			       <&u3port0 PHY_TYPE_USB3>;
859			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
860				 <&infracfg CLK_INFRA_USB>;
861			clock-names = "sys_ck", "ref_ck";
862			mediatek,syscon-wakeup = <&pericfg 0x400 0>;
863			#address-cells = <2>;
864			#size-cells = <2>;
865			ranges;
866			status = "disabled";
867
868			usb_host: xhci@11200000 {
869				compatible = "mediatek,mt8183-xhci",
870					     "mediatek,mtk-xhci";
871				reg = <0 0x11200000 0 0x1000>;
872				reg-names = "mac";
873				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
874				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
875					 <&infracfg CLK_INFRA_USB>;
876				clock-names = "sys_ck", "ref_ck";
877				status = "disabled";
878			};
879		};
880
881		audiosys: syscon@11220000 {
882			compatible = "mediatek,mt8183-audiosys", "syscon";
883			reg = <0 0x11220000 0 0x1000>;
884			#clock-cells = <1>;
885		};
886
887		mmc0: mmc@11230000 {
888			compatible = "mediatek,mt8183-mmc";
889			reg = <0 0x11230000 0 0x1000>,
890			      <0 0x11f50000 0 0x1000>;
891			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
892			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
893				 <&infracfg CLK_INFRA_MSDC0>,
894				 <&infracfg CLK_INFRA_MSDC0_SCK>;
895			clock-names = "source", "hclk", "source_cg";
896			status = "disabled";
897		};
898
899		mmc1: mmc@11240000 {
900			compatible = "mediatek,mt8183-mmc";
901			reg = <0 0x11240000 0 0x1000>,
902			      <0 0x11e10000 0 0x1000>;
903			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
904			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
905				 <&infracfg CLK_INFRA_MSDC1>,
906				 <&infracfg CLK_INFRA_MSDC1_SCK>;
907			clock-names = "source", "hclk", "source_cg";
908			status = "disabled";
909		};
910
911		mipi_tx0: mipi-dphy@11e50000 {
912			compatible = "mediatek,mt8183-mipi-tx";
913			reg = <0 0x11e50000 0 0x1000>;
914			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
915			clock-names = "ref_clk";
916			#clock-cells = <0>;
917			#phy-cells = <0>;
918			clock-output-names = "mipi_tx0_pll";
919			nvmem-cells = <&mipi_tx_calibration>;
920			nvmem-cell-names = "calibration-data";
921		};
922
923		efuse: efuse@11f10000 {
924			compatible = "mediatek,mt8183-efuse",
925				     "mediatek,efuse";
926			reg = <0 0x11f10000 0 0x1000>;
927			#address-cells = <1>;
928			#size-cells = <1>;
929			mipi_tx_calibration: calib@190 {
930				reg = <0x190 0xc>;
931			};
932		};
933
934		u3phy: usb-phy@11f40000 {
935			compatible = "mediatek,mt8183-tphy",
936				     "mediatek,generic-tphy-v2";
937			#address-cells = <1>;
938			#phy-cells = <1>;
939			#size-cells = <1>;
940			ranges = <0 0 0x11f40000 0x1000>;
941			status = "okay";
942
943			u2port0: usb-phy@0 {
944				reg = <0x0 0x700>;
945				clocks = <&clk26m>;
946				clock-names = "ref";
947				#phy-cells = <1>;
948				mediatek,discth = <15>;
949				status = "okay";
950			};
951
952			u3port0: usb-phy@0700 {
953				reg = <0x0700 0x900>;
954				clocks = <&clk26m>;
955				clock-names = "ref";
956				#phy-cells = <1>;
957				status = "okay";
958			};
959		};
960
961		mfgcfg: syscon@13000000 {
962			compatible = "mediatek,mt8183-mfgcfg", "syscon";
963			reg = <0 0x13000000 0 0x1000>;
964			#clock-cells = <1>;
965		};
966
967		mmsys: syscon@14000000 {
968			compatible = "mediatek,mt8183-mmsys", "syscon";
969			reg = <0 0x14000000 0 0x1000>;
970			#clock-cells = <1>;
971		};
972
973		ovl0: ovl@14008000 {
974			compatible = "mediatek,mt8183-disp-ovl";
975			reg = <0 0x14008000 0 0x1000>;
976			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
977			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
978			clocks = <&mmsys CLK_MM_DISP_OVL0>;
979			iommus = <&iommu M4U_PORT_DISP_OVL0>;
980			mediatek,larb = <&larb0>;
981			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
982		};
983
984		ovl_2l0: ovl@14009000 {
985			compatible = "mediatek,mt8183-disp-ovl-2l";
986			reg = <0 0x14009000 0 0x1000>;
987			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
988			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
989			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
990			iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
991			mediatek,larb = <&larb0>;
992			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
993		};
994
995		ovl_2l1: ovl@1400a000 {
996			compatible = "mediatek,mt8183-disp-ovl-2l";
997			reg = <0 0x1400a000 0 0x1000>;
998			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
999			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1000			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1001			iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
1002			mediatek,larb = <&larb0>;
1003			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1004		};
1005
1006		rdma0: rdma@1400b000 {
1007			compatible = "mediatek,mt8183-disp-rdma";
1008			reg = <0 0x1400b000 0 0x1000>;
1009			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
1010			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1011			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1012			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1013			mediatek,larb = <&larb0>;
1014			mediatek,rdma_fifo_size = <5120>;
1015			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1016		};
1017
1018		rdma1: rdma@1400c000 {
1019			compatible = "mediatek,mt8183-disp-rdma";
1020			reg = <0 0x1400c000 0 0x1000>;
1021			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
1022			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1023			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1024			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1025			mediatek,larb = <&larb0>;
1026			mediatek,rdma_fifo_size = <2048>;
1027			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1028		};
1029
1030		color0: color@1400e000 {
1031			compatible = "mediatek,mt8183-disp-color",
1032				     "mediatek,mt8173-disp-color";
1033			reg = <0 0x1400e000 0 0x1000>;
1034			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
1035			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1036			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1037			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1038		};
1039
1040		ccorr0: ccorr@1400f000 {
1041			compatible = "mediatek,mt8183-disp-ccorr";
1042			reg = <0 0x1400f000 0 0x1000>;
1043			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
1044			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1045			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1046		};
1047
1048		aal0: aal@14010000 {
1049			compatible = "mediatek,mt8183-disp-aal",
1050				     "mediatek,mt8173-disp-aal";
1051			reg = <0 0x14010000 0 0x1000>;
1052			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
1053			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1054			clocks = <&mmsys CLK_MM_DISP_AAL0>;
1055		};
1056
1057		gamma0: gamma@14011000 {
1058			compatible = "mediatek,mt8183-disp-gamma",
1059				     "mediatek,mt8173-disp-gamma";
1060			reg = <0 0x14011000 0 0x1000>;
1061			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
1062			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1063			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1064		};
1065
1066		dither0: dither@14012000 {
1067			compatible = "mediatek,mt8183-disp-dither";
1068			reg = <0 0x14012000 0 0x1000>;
1069			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
1070			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1071			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1072		};
1073
1074		dsi0: dsi@14014000 {
1075			compatible = "mediatek,mt8183-dsi";
1076			reg = <0 0x14014000 0 0x1000>;
1077			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
1078			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1079			mediatek,syscon-dsi = <&mmsys 0x140>;
1080			clocks = <&mmsys CLK_MM_DSI0_MM>,
1081				 <&mmsys CLK_MM_DSI0_IF>,
1082				 <&mipi_tx0>;
1083			clock-names = "engine", "digital", "hs";
1084			phys = <&mipi_tx0>;
1085			phy-names = "dphy";
1086		};
1087
1088		mutex: mutex@14016000 {
1089			compatible = "mediatek,mt8183-disp-mutex";
1090			reg = <0 0x14016000 0 0x1000>;
1091			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
1092			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1093		};
1094
1095		larb0: larb@14017000 {
1096			compatible = "mediatek,mt8183-smi-larb";
1097			reg = <0 0x14017000 0 0x1000>;
1098			mediatek,smi = <&smi_common>;
1099			clocks = <&mmsys CLK_MM_SMI_LARB0>,
1100				 <&mmsys CLK_MM_SMI_LARB0>;
1101			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1102			clock-names = "apb", "smi";
1103		};
1104
1105		smi_common: smi@14019000 {
1106			compatible = "mediatek,mt8183-smi-common", "syscon";
1107			reg = <0 0x14019000 0 0x1000>;
1108			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1109				 <&mmsys CLK_MM_SMI_COMMON>,
1110				 <&mmsys CLK_MM_GALS_COMM0>,
1111				 <&mmsys CLK_MM_GALS_COMM1>;
1112			clock-names = "apb", "smi", "gals0", "gals1";
1113		};
1114
1115		imgsys: syscon@15020000 {
1116			compatible = "mediatek,mt8183-imgsys", "syscon";
1117			reg = <0 0x15020000 0 0x1000>;
1118			#clock-cells = <1>;
1119		};
1120
1121		larb5: larb@15021000 {
1122			compatible = "mediatek,mt8183-smi-larb";
1123			reg = <0 0x15021000 0 0x1000>;
1124			mediatek,smi = <&smi_common>;
1125			clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
1126				 <&mmsys CLK_MM_GALS_IMG2MM>;
1127			clock-names = "apb", "smi", "gals";
1128			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1129		};
1130
1131		larb2: larb@1502f000 {
1132			compatible = "mediatek,mt8183-smi-larb";
1133			reg = <0 0x1502f000 0 0x1000>;
1134			mediatek,smi = <&smi_common>;
1135			clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
1136				 <&mmsys CLK_MM_GALS_IPU2MM>;
1137			clock-names = "apb", "smi", "gals";
1138			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1139		};
1140
1141		vdecsys: syscon@16000000 {
1142			compatible = "mediatek,mt8183-vdecsys", "syscon";
1143			reg = <0 0x16000000 0 0x1000>;
1144			#clock-cells = <1>;
1145		};
1146
1147		larb1: larb@16010000 {
1148			compatible = "mediatek,mt8183-smi-larb";
1149			reg = <0 0x16010000 0 0x1000>;
1150			mediatek,smi = <&smi_common>;
1151			clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
1152			clock-names = "apb", "smi";
1153			power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1154		};
1155
1156		vencsys: syscon@17000000 {
1157			compatible = "mediatek,mt8183-vencsys", "syscon";
1158			reg = <0 0x17000000 0 0x1000>;
1159			#clock-cells = <1>;
1160		};
1161
1162		larb4: larb@17010000 {
1163			compatible = "mediatek,mt8183-smi-larb";
1164			reg = <0 0x17010000 0 0x1000>;
1165			mediatek,smi = <&smi_common>;
1166			clocks = <&vencsys CLK_VENC_LARB>,
1167				 <&vencsys CLK_VENC_LARB>;
1168			clock-names = "apb", "smi";
1169			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1170		};
1171
1172		ipu_conn: syscon@19000000 {
1173			compatible = "mediatek,mt8183-ipu_conn", "syscon";
1174			reg = <0 0x19000000 0 0x1000>;
1175			#clock-cells = <1>;
1176		};
1177
1178		ipu_adl: syscon@19010000 {
1179			compatible = "mediatek,mt8183-ipu_adl", "syscon";
1180			reg = <0 0x19010000 0 0x1000>;
1181			#clock-cells = <1>;
1182		};
1183
1184		ipu_core0: syscon@19180000 {
1185			compatible = "mediatek,mt8183-ipu_core0", "syscon";
1186			reg = <0 0x19180000 0 0x1000>;
1187			#clock-cells = <1>;
1188		};
1189
1190		ipu_core1: syscon@19280000 {
1191			compatible = "mediatek,mt8183-ipu_core1", "syscon";
1192			reg = <0 0x19280000 0 0x1000>;
1193			#clock-cells = <1>;
1194		};
1195
1196		camsys: syscon@1a000000 {
1197			compatible = "mediatek,mt8183-camsys", "syscon";
1198			reg = <0 0x1a000000 0 0x1000>;
1199			#clock-cells = <1>;
1200		};
1201
1202		larb6: larb@1a001000 {
1203			compatible = "mediatek,mt8183-smi-larb";
1204			reg = <0 0x1a001000 0 0x1000>;
1205			mediatek,smi = <&smi_common>;
1206			clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
1207				 <&mmsys CLK_MM_GALS_CAM2MM>;
1208			clock-names = "apb", "smi", "gals";
1209			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1210		};
1211
1212		larb3: larb@1a002000 {
1213			compatible = "mediatek,mt8183-smi-larb";
1214			reg = <0 0x1a002000 0 0x1000>;
1215			mediatek,smi = <&smi_common>;
1216			clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
1217				 <&mmsys CLK_MM_GALS_IPU12MM>;
1218			clock-names = "apb", "smi", "gals";
1219			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1220		};
1221	};
1222};
1223