1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include "mt8183-pinfunc.h"
12
13/ {
14	compatible = "mediatek,mt8183";
15	interrupt-parent = <&sysirq>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu-map {
24			cluster0 {
25				core0 {
26					cpu = <&cpu0>;
27				};
28				core1 {
29					cpu = <&cpu1>;
30				};
31				core2 {
32					cpu = <&cpu2>;
33				};
34				core3 {
35					cpu = <&cpu3>;
36				};
37			};
38
39			cluster1 {
40				core0 {
41					cpu = <&cpu4>;
42				};
43				core1 {
44					cpu = <&cpu5>;
45				};
46				core2 {
47					cpu = <&cpu6>;
48				};
49				core3 {
50					cpu = <&cpu7>;
51				};
52			};
53		};
54
55		cpu0: cpu@0 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			reg = <0x000>;
59			enable-method = "psci";
60			capacity-dmips-mhz = <741>;
61		};
62
63		cpu1: cpu@1 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53";
66			reg = <0x001>;
67			enable-method = "psci";
68			capacity-dmips-mhz = <741>;
69		};
70
71		cpu2: cpu@2 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a53";
74			reg = <0x002>;
75			enable-method = "psci";
76			capacity-dmips-mhz = <741>;
77		};
78
79		cpu3: cpu@3 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a53";
82			reg = <0x003>;
83			enable-method = "psci";
84			capacity-dmips-mhz = <741>;
85		};
86
87		cpu4: cpu@100 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a73";
90			reg = <0x100>;
91			enable-method = "psci";
92			capacity-dmips-mhz = <1024>;
93		};
94
95		cpu5: cpu@101 {
96			device_type = "cpu";
97			compatible = "arm,cortex-a73";
98			reg = <0x101>;
99			enable-method = "psci";
100			capacity-dmips-mhz = <1024>;
101		};
102
103		cpu6: cpu@102 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a73";
106			reg = <0x102>;
107			enable-method = "psci";
108			capacity-dmips-mhz = <1024>;
109		};
110
111		cpu7: cpu@103 {
112			device_type = "cpu";
113			compatible = "arm,cortex-a73";
114			reg = <0x103>;
115			enable-method = "psci";
116			capacity-dmips-mhz = <1024>;
117		};
118	};
119
120	pmu-a53 {
121		compatible = "arm,cortex-a53-pmu";
122		interrupt-parent = <&gic>;
123		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
124	};
125
126	pmu-a73 {
127		compatible = "arm,cortex-a73-pmu";
128		interrupt-parent = <&gic>;
129		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
130	};
131
132	psci {
133		compatible      = "arm,psci-1.0";
134		method          = "smc";
135	};
136
137	clk26m: oscillator {
138		compatible = "fixed-clock";
139		#clock-cells = <0>;
140		clock-frequency = <26000000>;
141		clock-output-names = "clk26m";
142	};
143
144	timer {
145		compatible = "arm,armv8-timer";
146		interrupt-parent = <&gic>;
147		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
148			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
149			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
150			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
151	};
152
153	soc {
154		#address-cells = <2>;
155		#size-cells = <2>;
156		compatible = "simple-bus";
157		ranges;
158
159		gic: interrupt-controller@c000000 {
160			compatible = "arm,gic-v3";
161			#interrupt-cells = <4>;
162			interrupt-parent = <&gic>;
163			interrupt-controller;
164			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
165			      <0 0x0c100000 0 0x200000>, /* GICR */
166			      <0 0x0c400000 0 0x2000>,   /* GICC */
167			      <0 0x0c410000 0 0x1000>,   /* GICH */
168			      <0 0x0c420000 0 0x2000>;   /* GICV */
169
170			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
171			ppi-partitions {
172				ppi_cluster0: interrupt-partition-0 {
173					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
174				};
175				ppi_cluster1: interrupt-partition-1 {
176					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
177				};
178			};
179		};
180
181		mcucfg: syscon@c530000 {
182			compatible = "mediatek,mt8183-mcucfg", "syscon";
183			reg = <0 0x0c530000 0 0x1000>;
184			#clock-cells = <1>;
185		};
186
187		sysirq: interrupt-controller@c530a80 {
188			compatible = "mediatek,mt8183-sysirq",
189				     "mediatek,mt6577-sysirq";
190			interrupt-controller;
191			#interrupt-cells = <3>;
192			interrupt-parent = <&gic>;
193			reg = <0 0x0c530a80 0 0x50>;
194		};
195
196		topckgen: syscon@10000000 {
197			compatible = "mediatek,mt8183-topckgen", "syscon";
198			reg = <0 0x10000000 0 0x1000>;
199			#clock-cells = <1>;
200		};
201
202		infracfg: syscon@10001000 {
203			compatible = "mediatek,mt8183-infracfg", "syscon";
204			reg = <0 0x10001000 0 0x1000>;
205			#clock-cells = <1>;
206		};
207
208		pio: pinctrl@10005000 {
209			compatible = "mediatek,mt8183-pinctrl";
210			reg = <0 0x10005000 0 0x1000>,
211			      <0 0x11f20000 0 0x1000>,
212			      <0 0x11e80000 0 0x1000>,
213			      <0 0x11e70000 0 0x1000>,
214			      <0 0x11e90000 0 0x1000>,
215			      <0 0x11d30000 0 0x1000>,
216			      <0 0x11d20000 0 0x1000>,
217			      <0 0x11c50000 0 0x1000>,
218			      <0 0x11f30000 0 0x1000>,
219			      <0 0x1000b000 0 0x1000>;
220			reg-names = "iocfg0", "iocfg1", "iocfg2",
221				    "iocfg3", "iocfg4", "iocfg5",
222				    "iocfg6", "iocfg7", "iocfg8",
223				    "eint";
224			gpio-controller;
225			#gpio-cells = <2>;
226			gpio-ranges = <&pio 0 0 192>;
227			interrupt-controller;
228			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
229			#interrupt-cells = <2>;
230		};
231
232		apmixedsys: syscon@1000c000 {
233			compatible = "mediatek,mt8183-apmixedsys", "syscon";
234			reg = <0 0x1000c000 0 0x1000>;
235			#clock-cells = <1>;
236		};
237
238		pwrap: pwrap@1000d000 {
239			compatible = "mediatek,mt8183-pwrap";
240			reg = <0 0x1000d000 0 0x1000>;
241			reg-names = "pwrap";
242			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
243			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
244				 <&infracfg CLK_INFRA_PMIC_AP>;
245			clock-names = "spi", "wrap";
246		};
247
248		auxadc: auxadc@11001000 {
249			compatible = "mediatek,mt8183-auxadc",
250				     "mediatek,mt8173-auxadc";
251			reg = <0 0x11001000 0 0x1000>;
252			clocks = <&infracfg CLK_INFRA_AUXADC>;
253			clock-names = "main";
254			#io-channel-cells = <1>;
255			status = "disabled";
256		};
257
258		uart0: serial@11002000 {
259			compatible = "mediatek,mt8183-uart",
260				     "mediatek,mt6577-uart";
261			reg = <0 0x11002000 0 0x1000>;
262			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
263			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
264			clock-names = "baud", "bus";
265			status = "disabled";
266		};
267
268		uart1: serial@11003000 {
269			compatible = "mediatek,mt8183-uart",
270				     "mediatek,mt6577-uart";
271			reg = <0 0x11003000 0 0x1000>;
272			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
273			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
274			clock-names = "baud", "bus";
275			status = "disabled";
276		};
277
278		uart2: serial@11004000 {
279			compatible = "mediatek,mt8183-uart",
280				     "mediatek,mt6577-uart";
281			reg = <0 0x11004000 0 0x1000>;
282			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
283			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
284			clock-names = "baud", "bus";
285			status = "disabled";
286		};
287
288		spi0: spi@1100a000 {
289			compatible = "mediatek,mt8183-spi";
290			#address-cells = <1>;
291			#size-cells = <0>;
292			reg = <0 0x1100a000 0 0x1000>;
293			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
294			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
295				 <&topckgen CLK_TOP_MUX_SPI>,
296				 <&infracfg CLK_INFRA_SPI0>;
297			clock-names = "parent-clk", "sel-clk", "spi-clk";
298			status = "disabled";
299		};
300
301		spi1: spi@11010000 {
302			compatible = "mediatek,mt8183-spi";
303			#address-cells = <1>;
304			#size-cells = <0>;
305			reg = <0 0x11010000 0 0x1000>;
306			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
307			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
308				 <&topckgen CLK_TOP_MUX_SPI>,
309				 <&infracfg CLK_INFRA_SPI1>;
310			clock-names = "parent-clk", "sel-clk", "spi-clk";
311			status = "disabled";
312		};
313
314		spi2: spi@11012000 {
315			compatible = "mediatek,mt8183-spi";
316			#address-cells = <1>;
317			#size-cells = <0>;
318			reg = <0 0x11012000 0 0x1000>;
319			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
320			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
321				 <&topckgen CLK_TOP_MUX_SPI>,
322				 <&infracfg CLK_INFRA_SPI2>;
323			clock-names = "parent-clk", "sel-clk", "spi-clk";
324			status = "disabled";
325		};
326
327		spi3: spi@11013000 {
328			compatible = "mediatek,mt8183-spi";
329			#address-cells = <1>;
330			#size-cells = <0>;
331			reg = <0 0x11013000 0 0x1000>;
332			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
333			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
334				 <&topckgen CLK_TOP_MUX_SPI>,
335				 <&infracfg CLK_INFRA_SPI3>;
336			clock-names = "parent-clk", "sel-clk", "spi-clk";
337			status = "disabled";
338		};
339
340		spi4: spi@11018000 {
341			compatible = "mediatek,mt8183-spi";
342			#address-cells = <1>;
343			#size-cells = <0>;
344			reg = <0 0x11018000 0 0x1000>;
345			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
346			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
347				 <&topckgen CLK_TOP_MUX_SPI>,
348				 <&infracfg CLK_INFRA_SPI4>;
349			clock-names = "parent-clk", "sel-clk", "spi-clk";
350			status = "disabled";
351		};
352
353		spi5: spi@11019000 {
354			compatible = "mediatek,mt8183-spi";
355			#address-cells = <1>;
356			#size-cells = <0>;
357			reg = <0 0x11019000 0 0x1000>;
358			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
359			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
360				 <&topckgen CLK_TOP_MUX_SPI>,
361				 <&infracfg CLK_INFRA_SPI5>;
362			clock-names = "parent-clk", "sel-clk", "spi-clk";
363			status = "disabled";
364		};
365
366		audiosys: syscon@11220000 {
367			compatible = "mediatek,mt8183-audiosys", "syscon";
368			reg = <0 0x11220000 0 0x1000>;
369			#clock-cells = <1>;
370		};
371
372		mfgcfg: syscon@13000000 {
373			compatible = "mediatek,mt8183-mfgcfg", "syscon";
374			reg = <0 0x13000000 0 0x1000>;
375			#clock-cells = <1>;
376		};
377
378		mmsys: syscon@14000000 {
379			compatible = "mediatek,mt8183-mmsys", "syscon";
380			reg = <0 0x14000000 0 0x1000>;
381			#clock-cells = <1>;
382		};
383
384		imgsys: syscon@15020000 {
385			compatible = "mediatek,mt8183-imgsys", "syscon";
386			reg = <0 0x15020000 0 0x1000>;
387			#clock-cells = <1>;
388		};
389
390		vdecsys: syscon@16000000 {
391			compatible = "mediatek,mt8183-vdecsys", "syscon";
392			reg = <0 0x16000000 0 0x1000>;
393			#clock-cells = <1>;
394		};
395
396		vencsys: syscon@17000000 {
397			compatible = "mediatek,mt8183-vencsys", "syscon";
398			reg = <0 0x17000000 0 0x1000>;
399			#clock-cells = <1>;
400		};
401
402		ipu_conn: syscon@19000000 {
403			compatible = "mediatek,mt8183-ipu_conn", "syscon";
404			reg = <0 0x19000000 0 0x1000>;
405			#clock-cells = <1>;
406		};
407
408		ipu_adl: syscon@19010000 {
409			compatible = "mediatek,mt8183-ipu_adl", "syscon";
410			reg = <0 0x19010000 0 0x1000>;
411			#clock-cells = <1>;
412		};
413
414		ipu_core0: syscon@19180000 {
415			compatible = "mediatek,mt8183-ipu_core0", "syscon";
416			reg = <0 0x19180000 0 0x1000>;
417			#clock-cells = <1>;
418		};
419
420		ipu_core1: syscon@19280000 {
421			compatible = "mediatek,mt8183-ipu_core1", "syscon";
422			reg = <0 0x19280000 0 0x1000>;
423			#clock-cells = <1>;
424		};
425
426		camsys: syscon@1a000000 {
427			compatible = "mediatek,mt8183-camsys", "syscon";
428			reg = <0 0x1a000000 0 0x1000>;
429			#clock-cells = <1>;
430		};
431	};
432};
433