1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/mt8183-power.h> 12#include <dt-bindings/reset-controller/mt8183-resets.h> 13#include <dt-bindings/phy/phy.h> 14#include "mt8183-pinfunc.h" 15 16/ { 17 compatible = "mediatek,mt8183"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 i2c10 = &i2c10; 34 i2c11 = &i2c11; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpu0>; 45 }; 46 core1 { 47 cpu = <&cpu1>; 48 }; 49 core2 { 50 cpu = <&cpu2>; 51 }; 52 core3 { 53 cpu = <&cpu3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&cpu4>; 60 }; 61 core1 { 62 cpu = <&cpu5>; 63 }; 64 core2 { 65 cpu = <&cpu6>; 66 }; 67 core3 { 68 cpu = <&cpu7>; 69 }; 70 }; 71 }; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x000>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <741>; 79 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 80 dynamic-power-coefficient = <84>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu1: cpu@1 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x001>; 88 enable-method = "psci"; 89 capacity-dmips-mhz = <741>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 91 dynamic-power-coefficient = <84>; 92 #cooling-cells = <2>; 93 }; 94 95 cpu2: cpu@2 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53"; 98 reg = <0x002>; 99 enable-method = "psci"; 100 capacity-dmips-mhz = <741>; 101 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 102 dynamic-power-coefficient = <84>; 103 #cooling-cells = <2>; 104 }; 105 106 cpu3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x003>; 110 enable-method = "psci"; 111 capacity-dmips-mhz = <741>; 112 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 113 dynamic-power-coefficient = <84>; 114 #cooling-cells = <2>; 115 }; 116 117 cpu4: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a73"; 120 reg = <0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 124 dynamic-power-coefficient = <211>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu5: cpu@101 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a73"; 131 reg = <0x101>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 135 dynamic-power-coefficient = <211>; 136 #cooling-cells = <2>; 137 }; 138 139 cpu6: cpu@102 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a73"; 142 reg = <0x102>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 146 dynamic-power-coefficient = <211>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu7: cpu@103 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a73"; 153 reg = <0x103>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 157 dynamic-power-coefficient = <211>; 158 #cooling-cells = <2>; 159 }; 160 161 idle-states { 162 entry-method = "psci"; 163 164 CPU_SLEEP: cpu-sleep { 165 compatible = "arm,idle-state"; 166 local-timer-stop; 167 arm,psci-suspend-param = <0x00010001>; 168 entry-latency-us = <200>; 169 exit-latency-us = <200>; 170 min-residency-us = <800>; 171 }; 172 173 CLUSTER_SLEEP0: cluster-sleep-0 { 174 compatible = "arm,idle-state"; 175 local-timer-stop; 176 arm,psci-suspend-param = <0x01010001>; 177 entry-latency-us = <250>; 178 exit-latency-us = <400>; 179 min-residency-us = <1000>; 180 }; 181 CLUSTER_SLEEP1: cluster-sleep-1 { 182 compatible = "arm,idle-state"; 183 local-timer-stop; 184 arm,psci-suspend-param = <0x01010001>; 185 entry-latency-us = <250>; 186 exit-latency-us = <400>; 187 min-residency-us = <1300>; 188 }; 189 }; 190 }; 191 192 pmu-a53 { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupt-parent = <&gic>; 195 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 196 }; 197 198 pmu-a73 { 199 compatible = "arm,cortex-a73-pmu"; 200 interrupt-parent = <&gic>; 201 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 202 }; 203 204 psci { 205 compatible = "arm,psci-1.0"; 206 method = "smc"; 207 }; 208 209 clk26m: oscillator { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <26000000>; 213 clock-output-names = "clk26m"; 214 }; 215 216 timer { 217 compatible = "arm,armv8-timer"; 218 interrupt-parent = <&gic>; 219 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 220 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 221 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 222 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 223 }; 224 225 soc { 226 #address-cells = <2>; 227 #size-cells = <2>; 228 compatible = "simple-bus"; 229 ranges; 230 231 soc_data: soc_data@8000000 { 232 compatible = "mediatek,mt8183-efuse", 233 "mediatek,efuse"; 234 reg = <0 0x08000000 0 0x0010>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 status = "disabled"; 238 }; 239 240 gic: interrupt-controller@c000000 { 241 compatible = "arm,gic-v3"; 242 #interrupt-cells = <4>; 243 interrupt-parent = <&gic>; 244 interrupt-controller; 245 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 246 <0 0x0c100000 0 0x200000>, /* GICR */ 247 <0 0x0c400000 0 0x2000>, /* GICC */ 248 <0 0x0c410000 0 0x1000>, /* GICH */ 249 <0 0x0c420000 0 0x2000>; /* GICV */ 250 251 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 252 ppi-partitions { 253 ppi_cluster0: interrupt-partition-0 { 254 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 255 }; 256 ppi_cluster1: interrupt-partition-1 { 257 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 258 }; 259 }; 260 }; 261 262 mcucfg: syscon@c530000 { 263 compatible = "mediatek,mt8183-mcucfg", "syscon"; 264 reg = <0 0x0c530000 0 0x1000>; 265 #clock-cells = <1>; 266 }; 267 268 sysirq: interrupt-controller@c530a80 { 269 compatible = "mediatek,mt8183-sysirq", 270 "mediatek,mt6577-sysirq"; 271 interrupt-controller; 272 #interrupt-cells = <3>; 273 interrupt-parent = <&gic>; 274 reg = <0 0x0c530a80 0 0x50>; 275 }; 276 277 topckgen: syscon@10000000 { 278 compatible = "mediatek,mt8183-topckgen", "syscon"; 279 reg = <0 0x10000000 0 0x1000>; 280 #clock-cells = <1>; 281 }; 282 283 infracfg: syscon@10001000 { 284 compatible = "mediatek,mt8183-infracfg", "syscon"; 285 reg = <0 0x10001000 0 0x1000>; 286 #clock-cells = <1>; 287 #reset-cells = <1>; 288 }; 289 290 pericfg: syscon@10003000 { 291 compatible = "mediatek,mt8183-pericfg", "syscon"; 292 reg = <0 0x10003000 0 0x1000>; 293 #clock-cells = <1>; 294 }; 295 296 pio: pinctrl@10005000 { 297 compatible = "mediatek,mt8183-pinctrl"; 298 reg = <0 0x10005000 0 0x1000>, 299 <0 0x11f20000 0 0x1000>, 300 <0 0x11e80000 0 0x1000>, 301 <0 0x11e70000 0 0x1000>, 302 <0 0x11e90000 0 0x1000>, 303 <0 0x11d30000 0 0x1000>, 304 <0 0x11d20000 0 0x1000>, 305 <0 0x11c50000 0 0x1000>, 306 <0 0x11f30000 0 0x1000>, 307 <0 0x1000b000 0 0x1000>; 308 reg-names = "iocfg0", "iocfg1", "iocfg2", 309 "iocfg3", "iocfg4", "iocfg5", 310 "iocfg6", "iocfg7", "iocfg8", 311 "eint"; 312 gpio-controller; 313 #gpio-cells = <2>; 314 gpio-ranges = <&pio 0 0 192>; 315 interrupt-controller; 316 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 317 #interrupt-cells = <2>; 318 }; 319 320 scpsys: syscon@10006000 { 321 compatible = "syscon", "simple-mfd"; 322 reg = <0 0x10006000 0 0x1000>; 323 #power-domain-cells = <1>; 324 325 /* System Power Manager */ 326 spm: power-controller { 327 compatible = "mediatek,mt8183-power-controller"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 #power-domain-cells = <1>; 331 332 /* power domain of the SoC */ 333 power-domain@MT8183_POWER_DOMAIN_AUDIO { 334 reg = <MT8183_POWER_DOMAIN_AUDIO>; 335 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 336 <&infracfg CLK_INFRA_AUDIO>, 337 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 338 clock-names = "audio", "audio1", "audio2"; 339 #power-domain-cells = <0>; 340 }; 341 342 power-domain@MT8183_POWER_DOMAIN_CONN { 343 reg = <MT8183_POWER_DOMAIN_CONN>; 344 mediatek,infracfg = <&infracfg>; 345 #power-domain-cells = <0>; 346 }; 347 348 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 349 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 350 clocks = <&topckgen CLK_TOP_MUX_MFG>; 351 clock-names = "mfg"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 #power-domain-cells = <1>; 355 356 power-domain@MT8183_POWER_DOMAIN_MFG { 357 reg = <MT8183_POWER_DOMAIN_MFG>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 #power-domain-cells = <1>; 361 362 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 363 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 364 #power-domain-cells = <0>; 365 }; 366 367 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 368 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 369 #power-domain-cells = <0>; 370 }; 371 372 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 373 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 374 mediatek,infracfg = <&infracfg>; 375 #power-domain-cells = <0>; 376 }; 377 }; 378 }; 379 380 power-domain@MT8183_POWER_DOMAIN_DISP { 381 reg = <MT8183_POWER_DOMAIN_DISP>; 382 clocks = <&topckgen CLK_TOP_MUX_MM>, 383 <&mmsys CLK_MM_SMI_COMMON>, 384 <&mmsys CLK_MM_SMI_LARB0>, 385 <&mmsys CLK_MM_SMI_LARB1>, 386 <&mmsys CLK_MM_GALS_COMM0>, 387 <&mmsys CLK_MM_GALS_COMM1>, 388 <&mmsys CLK_MM_GALS_CCU2MM>, 389 <&mmsys CLK_MM_GALS_IPU12MM>, 390 <&mmsys CLK_MM_GALS_IMG2MM>, 391 <&mmsys CLK_MM_GALS_CAM2MM>, 392 <&mmsys CLK_MM_GALS_IPU2MM>; 393 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 394 "mm-4", "mm-5", "mm-6", "mm-7", 395 "mm-8", "mm-9"; 396 mediatek,infracfg = <&infracfg>; 397 mediatek,smi = <&smi_common>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 #power-domain-cells = <1>; 401 402 power-domain@MT8183_POWER_DOMAIN_CAM { 403 reg = <MT8183_POWER_DOMAIN_CAM>; 404 clocks = <&topckgen CLK_TOP_MUX_CAM>, 405 <&camsys CLK_CAM_LARB6>, 406 <&camsys CLK_CAM_LARB3>, 407 <&camsys CLK_CAM_SENINF>, 408 <&camsys CLK_CAM_CAMSV0>, 409 <&camsys CLK_CAM_CAMSV1>, 410 <&camsys CLK_CAM_CAMSV2>, 411 <&camsys CLK_CAM_CCU>; 412 clock-names = "cam", "cam-0", "cam-1", 413 "cam-2", "cam-3", "cam-4", 414 "cam-5", "cam-6"; 415 mediatek,infracfg = <&infracfg>; 416 mediatek,smi = <&smi_common>; 417 #power-domain-cells = <0>; 418 }; 419 420 power-domain@MT8183_POWER_DOMAIN_ISP { 421 reg = <MT8183_POWER_DOMAIN_ISP>; 422 clocks = <&topckgen CLK_TOP_MUX_IMG>, 423 <&imgsys CLK_IMG_LARB5>, 424 <&imgsys CLK_IMG_LARB2>; 425 clock-names = "isp", "isp-0", "isp-1"; 426 mediatek,infracfg = <&infracfg>; 427 mediatek,smi = <&smi_common>; 428 #power-domain-cells = <0>; 429 }; 430 431 power-domain@MT8183_POWER_DOMAIN_VDEC { 432 reg = <MT8183_POWER_DOMAIN_VDEC>; 433 mediatek,smi = <&smi_common>; 434 #power-domain-cells = <0>; 435 }; 436 437 power-domain@MT8183_POWER_DOMAIN_VENC { 438 reg = <MT8183_POWER_DOMAIN_VENC>; 439 mediatek,smi = <&smi_common>; 440 #power-domain-cells = <0>; 441 }; 442 443 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 444 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 445 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 446 <&topckgen CLK_TOP_MUX_DSP>, 447 <&ipu_conn CLK_IPU_CONN_IPU>, 448 <&ipu_conn CLK_IPU_CONN_AHB>, 449 <&ipu_conn CLK_IPU_CONN_AXI>, 450 <&ipu_conn CLK_IPU_CONN_ISP>, 451 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 452 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 453 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 454 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 455 mediatek,infracfg = <&infracfg>; 456 mediatek,smi = <&smi_common>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 #power-domain-cells = <1>; 460 461 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 462 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 463 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 464 clock-names = "vpu2"; 465 mediatek,infracfg = <&infracfg>; 466 #power-domain-cells = <0>; 467 }; 468 469 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 470 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 471 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 472 clock-names = "vpu3"; 473 mediatek,infracfg = <&infracfg>; 474 #power-domain-cells = <0>; 475 }; 476 }; 477 }; 478 }; 479 }; 480 481 watchdog: watchdog@10007000 { 482 compatible = "mediatek,mt8183-wdt"; 483 reg = <0 0x10007000 0 0x100>; 484 #reset-cells = <1>; 485 }; 486 487 apmixedsys: syscon@1000c000 { 488 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 489 reg = <0 0x1000c000 0 0x1000>; 490 #clock-cells = <1>; 491 }; 492 493 pwrap: pwrap@1000d000 { 494 compatible = "mediatek,mt8183-pwrap"; 495 reg = <0 0x1000d000 0 0x1000>; 496 reg-names = "pwrap"; 497 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 499 <&infracfg CLK_INFRA_PMIC_AP>; 500 clock-names = "spi", "wrap"; 501 }; 502 503 scp: scp@10500000 { 504 compatible = "mediatek,mt8183-scp"; 505 reg = <0 0x10500000 0 0x80000>, 506 <0 0x105c0000 0 0x19080>; 507 reg-names = "sram", "cfg"; 508 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&infracfg CLK_INFRA_SCPSYS>; 510 clock-names = "main"; 511 memory-region = <&scp_mem_reserved>; 512 status = "disabled"; 513 }; 514 515 systimer: timer@10017000 { 516 compatible = "mediatek,mt8183-timer", 517 "mediatek,mt6765-timer"; 518 reg = <0 0x10017000 0 0x1000>; 519 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&topckgen CLK_TOP_CLK13M>; 521 clock-names = "clk13m"; 522 }; 523 524 gce: mailbox@10238000 { 525 compatible = "mediatek,mt8183-gce"; 526 reg = <0 0x10238000 0 0x4000>; 527 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 528 #mbox-cells = <2>; 529 clocks = <&infracfg CLK_INFRA_GCE>; 530 clock-names = "gce"; 531 }; 532 533 auxadc: auxadc@11001000 { 534 compatible = "mediatek,mt8183-auxadc", 535 "mediatek,mt8173-auxadc"; 536 reg = <0 0x11001000 0 0x1000>; 537 clocks = <&infracfg CLK_INFRA_AUXADC>; 538 clock-names = "main"; 539 #io-channel-cells = <1>; 540 status = "disabled"; 541 }; 542 543 uart0: serial@11002000 { 544 compatible = "mediatek,mt8183-uart", 545 "mediatek,mt6577-uart"; 546 reg = <0 0x11002000 0 0x1000>; 547 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 548 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 549 clock-names = "baud", "bus"; 550 status = "disabled"; 551 }; 552 553 uart1: serial@11003000 { 554 compatible = "mediatek,mt8183-uart", 555 "mediatek,mt6577-uart"; 556 reg = <0 0x11003000 0 0x1000>; 557 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 558 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 559 clock-names = "baud", "bus"; 560 status = "disabled"; 561 }; 562 563 uart2: serial@11004000 { 564 compatible = "mediatek,mt8183-uart", 565 "mediatek,mt6577-uart"; 566 reg = <0 0x11004000 0 0x1000>; 567 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 568 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 569 clock-names = "baud", "bus"; 570 status = "disabled"; 571 }; 572 573 i2c6: i2c@11005000 { 574 compatible = "mediatek,mt8183-i2c"; 575 reg = <0 0x11005000 0 0x1000>, 576 <0 0x11000600 0 0x80>; 577 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 578 clocks = <&infracfg CLK_INFRA_I2C6>, 579 <&infracfg CLK_INFRA_AP_DMA>; 580 clock-names = "main", "dma"; 581 clock-div = <1>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 i2c0: i2c@11007000 { 588 compatible = "mediatek,mt8183-i2c"; 589 reg = <0 0x11007000 0 0x1000>, 590 <0 0x11000080 0 0x80>; 591 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 592 clocks = <&infracfg CLK_INFRA_I2C0>, 593 <&infracfg CLK_INFRA_AP_DMA>; 594 clock-names = "main", "dma"; 595 clock-div = <1>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 i2c4: i2c@11008000 { 602 compatible = "mediatek,mt8183-i2c"; 603 reg = <0 0x11008000 0 0x1000>, 604 <0 0x11000100 0 0x80>; 605 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 606 clocks = <&infracfg CLK_INFRA_I2C1>, 607 <&infracfg CLK_INFRA_AP_DMA>, 608 <&infracfg CLK_INFRA_I2C1_ARBITER>; 609 clock-names = "main", "dma","arb"; 610 clock-div = <1>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 i2c2: i2c@11009000 { 617 compatible = "mediatek,mt8183-i2c"; 618 reg = <0 0x11009000 0 0x1000>, 619 <0 0x11000280 0 0x80>; 620 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 621 clocks = <&infracfg CLK_INFRA_I2C2>, 622 <&infracfg CLK_INFRA_AP_DMA>, 623 <&infracfg CLK_INFRA_I2C2_ARBITER>; 624 clock-names = "main", "dma", "arb"; 625 clock-div = <1>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 spi0: spi@1100a000 { 632 compatible = "mediatek,mt8183-spi"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <0 0x1100a000 0 0x1000>; 636 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 637 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 638 <&topckgen CLK_TOP_MUX_SPI>, 639 <&infracfg CLK_INFRA_SPI0>; 640 clock-names = "parent-clk", "sel-clk", "spi-clk"; 641 status = "disabled"; 642 }; 643 644 pwm0: pwm@1100e000 { 645 compatible = "mediatek,mt8183-disp-pwm"; 646 reg = <0 0x1100e000 0 0x1000>; 647 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 648 #pwm-cells = <2>; 649 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 650 <&infracfg CLK_INFRA_DISP_PWM>; 651 clock-names = "main", "mm"; 652 }; 653 654 i2c3: i2c@1100f000 { 655 compatible = "mediatek,mt8183-i2c"; 656 reg = <0 0x1100f000 0 0x1000>, 657 <0 0x11000400 0 0x80>; 658 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 659 clocks = <&infracfg CLK_INFRA_I2C3>, 660 <&infracfg CLK_INFRA_AP_DMA>; 661 clock-names = "main", "dma"; 662 clock-div = <1>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 spi1: spi@11010000 { 669 compatible = "mediatek,mt8183-spi"; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 reg = <0 0x11010000 0 0x1000>; 673 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 674 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 675 <&topckgen CLK_TOP_MUX_SPI>, 676 <&infracfg CLK_INFRA_SPI1>; 677 clock-names = "parent-clk", "sel-clk", "spi-clk"; 678 status = "disabled"; 679 }; 680 681 i2c1: i2c@11011000 { 682 compatible = "mediatek,mt8183-i2c"; 683 reg = <0 0x11011000 0 0x1000>, 684 <0 0x11000480 0 0x80>; 685 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 686 clocks = <&infracfg CLK_INFRA_I2C4>, 687 <&infracfg CLK_INFRA_AP_DMA>; 688 clock-names = "main", "dma"; 689 clock-div = <1>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 status = "disabled"; 693 }; 694 695 spi2: spi@11012000 { 696 compatible = "mediatek,mt8183-spi"; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 reg = <0 0x11012000 0 0x1000>; 700 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 701 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 702 <&topckgen CLK_TOP_MUX_SPI>, 703 <&infracfg CLK_INFRA_SPI2>; 704 clock-names = "parent-clk", "sel-clk", "spi-clk"; 705 status = "disabled"; 706 }; 707 708 spi3: spi@11013000 { 709 compatible = "mediatek,mt8183-spi"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 reg = <0 0x11013000 0 0x1000>; 713 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 714 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 715 <&topckgen CLK_TOP_MUX_SPI>, 716 <&infracfg CLK_INFRA_SPI3>; 717 clock-names = "parent-clk", "sel-clk", "spi-clk"; 718 status = "disabled"; 719 }; 720 721 i2c9: i2c@11014000 { 722 compatible = "mediatek,mt8183-i2c"; 723 reg = <0 0x11014000 0 0x1000>, 724 <0 0x11000180 0 0x80>; 725 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 726 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 727 <&infracfg CLK_INFRA_AP_DMA>, 728 <&infracfg CLK_INFRA_I2C1_ARBITER>; 729 clock-names = "main", "dma", "arb"; 730 clock-div = <1>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 i2c10: i2c@11015000 { 737 compatible = "mediatek,mt8183-i2c"; 738 reg = <0 0x11015000 0 0x1000>, 739 <0 0x11000300 0 0x80>; 740 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 741 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 742 <&infracfg CLK_INFRA_AP_DMA>, 743 <&infracfg CLK_INFRA_I2C2_ARBITER>; 744 clock-names = "main", "dma", "arb"; 745 clock-div = <1>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 status = "disabled"; 749 }; 750 751 i2c5: i2c@11016000 { 752 compatible = "mediatek,mt8183-i2c"; 753 reg = <0 0x11016000 0 0x1000>, 754 <0 0x11000500 0 0x80>; 755 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 756 clocks = <&infracfg CLK_INFRA_I2C5>, 757 <&infracfg CLK_INFRA_AP_DMA>, 758 <&infracfg CLK_INFRA_I2C5_ARBITER>; 759 clock-names = "main", "dma", "arb"; 760 clock-div = <1>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 i2c11: i2c@11017000 { 767 compatible = "mediatek,mt8183-i2c"; 768 reg = <0 0x11017000 0 0x1000>, 769 <0 0x11000580 0 0x80>; 770 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 771 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 772 <&infracfg CLK_INFRA_AP_DMA>, 773 <&infracfg CLK_INFRA_I2C5_ARBITER>; 774 clock-names = "main", "dma", "arb"; 775 clock-div = <1>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 status = "disabled"; 779 }; 780 781 spi4: spi@11018000 { 782 compatible = "mediatek,mt8183-spi"; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 reg = <0 0x11018000 0 0x1000>; 786 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 787 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 788 <&topckgen CLK_TOP_MUX_SPI>, 789 <&infracfg CLK_INFRA_SPI4>; 790 clock-names = "parent-clk", "sel-clk", "spi-clk"; 791 status = "disabled"; 792 }; 793 794 spi5: spi@11019000 { 795 compatible = "mediatek,mt8183-spi"; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 reg = <0 0x11019000 0 0x1000>; 799 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 800 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 801 <&topckgen CLK_TOP_MUX_SPI>, 802 <&infracfg CLK_INFRA_SPI5>; 803 clock-names = "parent-clk", "sel-clk", "spi-clk"; 804 status = "disabled"; 805 }; 806 807 i2c7: i2c@1101a000 { 808 compatible = "mediatek,mt8183-i2c"; 809 reg = <0 0x1101a000 0 0x1000>, 810 <0 0x11000680 0 0x80>; 811 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 812 clocks = <&infracfg CLK_INFRA_I2C7>, 813 <&infracfg CLK_INFRA_AP_DMA>; 814 clock-names = "main", "dma"; 815 clock-div = <1>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 status = "disabled"; 819 }; 820 821 i2c8: i2c@1101b000 { 822 compatible = "mediatek,mt8183-i2c"; 823 reg = <0 0x1101b000 0 0x1000>, 824 <0 0x11000700 0 0x80>; 825 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 826 clocks = <&infracfg CLK_INFRA_I2C8>, 827 <&infracfg CLK_INFRA_AP_DMA>; 828 clock-names = "main", "dma"; 829 clock-div = <1>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 status = "disabled"; 833 }; 834 835 ssusb: usb@11201000 { 836 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 837 reg = <0 0x11201000 0 0x2e00>, 838 <0 0x11203e00 0 0x0100>; 839 reg-names = "mac", "ippc"; 840 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 841 phys = <&u2port0 PHY_TYPE_USB2>, 842 <&u3port0 PHY_TYPE_USB3>; 843 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 844 <&infracfg CLK_INFRA_USB>; 845 clock-names = "sys_ck", "ref_ck"; 846 mediatek,syscon-wakeup = <&pericfg 0x400 0>; 847 #address-cells = <2>; 848 #size-cells = <2>; 849 ranges; 850 status = "disabled"; 851 852 usb_host: xhci@11200000 { 853 compatible = "mediatek,mt8183-xhci", 854 "mediatek,mtk-xhci"; 855 reg = <0 0x11200000 0 0x1000>; 856 reg-names = "mac"; 857 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 858 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 859 <&infracfg CLK_INFRA_USB>; 860 clock-names = "sys_ck", "ref_ck"; 861 status = "disabled"; 862 }; 863 }; 864 865 audiosys: syscon@11220000 { 866 compatible = "mediatek,mt8183-audiosys", "syscon"; 867 reg = <0 0x11220000 0 0x1000>; 868 #clock-cells = <1>; 869 }; 870 871 mmc0: mmc@11230000 { 872 compatible = "mediatek,mt8183-mmc"; 873 reg = <0 0x11230000 0 0x1000>, 874 <0 0x11f50000 0 0x1000>; 875 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 876 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 877 <&infracfg CLK_INFRA_MSDC0>, 878 <&infracfg CLK_INFRA_MSDC0_SCK>; 879 clock-names = "source", "hclk", "source_cg"; 880 status = "disabled"; 881 }; 882 883 mmc1: mmc@11240000 { 884 compatible = "mediatek,mt8183-mmc"; 885 reg = <0 0x11240000 0 0x1000>, 886 <0 0x11e10000 0 0x1000>; 887 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 888 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 889 <&infracfg CLK_INFRA_MSDC1>, 890 <&infracfg CLK_INFRA_MSDC1_SCK>; 891 clock-names = "source", "hclk", "source_cg"; 892 status = "disabled"; 893 }; 894 895 mipi_tx0: mipi-dphy@11e50000 { 896 compatible = "mediatek,mt8183-mipi-tx"; 897 reg = <0 0x11e50000 0 0x1000>; 898 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 899 clock-names = "ref_clk"; 900 #clock-cells = <0>; 901 #phy-cells = <0>; 902 clock-output-names = "mipi_tx0_pll"; 903 nvmem-cells = <&mipi_tx_calibration>; 904 nvmem-cell-names = "calibration-data"; 905 }; 906 907 efuse: efuse@11f10000 { 908 compatible = "mediatek,mt8183-efuse", 909 "mediatek,efuse"; 910 reg = <0 0x11f10000 0 0x1000>; 911 #address-cells = <1>; 912 #size-cells = <1>; 913 mipi_tx_calibration: calib@190 { 914 reg = <0x190 0xc>; 915 }; 916 }; 917 918 u3phy: usb-phy@11f40000 { 919 compatible = "mediatek,mt8183-tphy", 920 "mediatek,generic-tphy-v2"; 921 #address-cells = <1>; 922 #phy-cells = <1>; 923 #size-cells = <1>; 924 ranges = <0 0 0x11f40000 0x1000>; 925 status = "okay"; 926 927 u2port0: usb-phy@0 { 928 reg = <0x0 0x700>; 929 clocks = <&clk26m>; 930 clock-names = "ref"; 931 #phy-cells = <1>; 932 mediatek,discth = <15>; 933 status = "okay"; 934 }; 935 936 u3port0: usb-phy@0700 { 937 reg = <0x0700 0x900>; 938 clocks = <&clk26m>; 939 clock-names = "ref"; 940 #phy-cells = <1>; 941 status = "okay"; 942 }; 943 }; 944 945 mfgcfg: syscon@13000000 { 946 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 947 reg = <0 0x13000000 0 0x1000>; 948 #clock-cells = <1>; 949 }; 950 951 mmsys: syscon@14000000 { 952 compatible = "mediatek,mt8183-mmsys", "syscon"; 953 reg = <0 0x14000000 0 0x1000>; 954 #clock-cells = <1>; 955 }; 956 957 dsi0: dsi@14014000 { 958 compatible = "mediatek,mt8183-dsi"; 959 reg = <0 0x14014000 0 0x1000>; 960 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 961 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 962 mediatek,syscon-dsi = <&mmsys 0x140>; 963 clocks = <&mmsys CLK_MM_DSI0_MM>, 964 <&mmsys CLK_MM_DSI0_IF>, 965 <&mipi_tx0>; 966 clock-names = "engine", "digital", "hs"; 967 phys = <&mipi_tx0>; 968 phy-names = "dphy"; 969 }; 970 971 smi_common: smi@14019000 { 972 compatible = "mediatek,mt8183-smi-common", "syscon"; 973 reg = <0 0x14019000 0 0x1000>; 974 clocks = <&mmsys CLK_MM_SMI_COMMON>, 975 <&mmsys CLK_MM_SMI_COMMON>, 976 <&mmsys CLK_MM_GALS_COMM0>, 977 <&mmsys CLK_MM_GALS_COMM1>; 978 clock-names = "apb", "smi", "gals0", "gals1"; 979 }; 980 981 imgsys: syscon@15020000 { 982 compatible = "mediatek,mt8183-imgsys", "syscon"; 983 reg = <0 0x15020000 0 0x1000>; 984 #clock-cells = <1>; 985 }; 986 987 vdecsys: syscon@16000000 { 988 compatible = "mediatek,mt8183-vdecsys", "syscon"; 989 reg = <0 0x16000000 0 0x1000>; 990 #clock-cells = <1>; 991 }; 992 993 vencsys: syscon@17000000 { 994 compatible = "mediatek,mt8183-vencsys", "syscon"; 995 reg = <0 0x17000000 0 0x1000>; 996 #clock-cells = <1>; 997 }; 998 999 ipu_conn: syscon@19000000 { 1000 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1001 reg = <0 0x19000000 0 0x1000>; 1002 #clock-cells = <1>; 1003 }; 1004 1005 ipu_adl: syscon@19010000 { 1006 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1007 reg = <0 0x19010000 0 0x1000>; 1008 #clock-cells = <1>; 1009 }; 1010 1011 ipu_core0: syscon@19180000 { 1012 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1013 reg = <0 0x19180000 0 0x1000>; 1014 #clock-cells = <1>; 1015 }; 1016 1017 ipu_core1: syscon@19280000 { 1018 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1019 reg = <0 0x19280000 0 0x1000>; 1020 #clock-cells = <1>; 1021 }; 1022 1023 camsys: syscon@1a000000 { 1024 compatible = "mediatek,mt8183-camsys", "syscon"; 1025 reg = <0 0x1a000000 0 0x1000>; 1026 #clock-cells = <1>; 1027 }; 1028 }; 1029}; 1030