1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/gce/mt8183-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8183-larb-port.h>
13#include <dt-bindings/power/mt8183-power.h>
14#include <dt-bindings/reset/mt8183-resets.h>
15#include <dt-bindings/phy/phy.h>
16#include <dt-bindings/thermal/thermal.h>
17#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
18
19/ {
20	compatible = "mediatek,mt8183";
21	interrupt-parent = <&sysirq>;
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	aliases {
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		i2c2 = &i2c2;
29		i2c3 = &i2c3;
30		i2c4 = &i2c4;
31		i2c5 = &i2c5;
32		i2c6 = &i2c6;
33		i2c7 = &i2c7;
34		i2c8 = &i2c8;
35		i2c9 = &i2c9;
36		i2c10 = &i2c10;
37		i2c11 = &i2c11;
38		ovl0 = &ovl0;
39		ovl-2l0 = &ovl_2l0;
40		ovl-2l1 = &ovl_2l1;
41		rdma0 = &rdma0;
42		rdma1 = &rdma1;
43	};
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		cpu-map {
50			cluster0 {
51				core0 {
52					cpu = <&cpu0>;
53				};
54				core1 {
55					cpu = <&cpu1>;
56				};
57				core2 {
58					cpu = <&cpu2>;
59				};
60				core3 {
61					cpu = <&cpu3>;
62				};
63			};
64
65			cluster1 {
66				core0 {
67					cpu = <&cpu4>;
68				};
69				core1 {
70					cpu = <&cpu5>;
71				};
72				core2 {
73					cpu = <&cpu6>;
74				};
75				core3 {
76					cpu = <&cpu7>;
77				};
78			};
79		};
80
81		cpu0: cpu@0 {
82			device_type = "cpu";
83			compatible = "arm,cortex-a53";
84			reg = <0x000>;
85			enable-method = "psci";
86			capacity-dmips-mhz = <741>;
87			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
88			dynamic-power-coefficient = <84>;
89			#cooling-cells = <2>;
90		};
91
92		cpu1: cpu@1 {
93			device_type = "cpu";
94			compatible = "arm,cortex-a53";
95			reg = <0x001>;
96			enable-method = "psci";
97			capacity-dmips-mhz = <741>;
98			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
99			dynamic-power-coefficient = <84>;
100			#cooling-cells = <2>;
101		};
102
103		cpu2: cpu@2 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a53";
106			reg = <0x002>;
107			enable-method = "psci";
108			capacity-dmips-mhz = <741>;
109			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
110			dynamic-power-coefficient = <84>;
111			#cooling-cells = <2>;
112		};
113
114		cpu3: cpu@3 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a53";
117			reg = <0x003>;
118			enable-method = "psci";
119			capacity-dmips-mhz = <741>;
120			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
121			dynamic-power-coefficient = <84>;
122			#cooling-cells = <2>;
123		};
124
125		cpu4: cpu@100 {
126			device_type = "cpu";
127			compatible = "arm,cortex-a73";
128			reg = <0x100>;
129			enable-method = "psci";
130			capacity-dmips-mhz = <1024>;
131			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
132			dynamic-power-coefficient = <211>;
133			#cooling-cells = <2>;
134		};
135
136		cpu5: cpu@101 {
137			device_type = "cpu";
138			compatible = "arm,cortex-a73";
139			reg = <0x101>;
140			enable-method = "psci";
141			capacity-dmips-mhz = <1024>;
142			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
143			dynamic-power-coefficient = <211>;
144			#cooling-cells = <2>;
145		};
146
147		cpu6: cpu@102 {
148			device_type = "cpu";
149			compatible = "arm,cortex-a73";
150			reg = <0x102>;
151			enable-method = "psci";
152			capacity-dmips-mhz = <1024>;
153			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
154			dynamic-power-coefficient = <211>;
155			#cooling-cells = <2>;
156		};
157
158		cpu7: cpu@103 {
159			device_type = "cpu";
160			compatible = "arm,cortex-a73";
161			reg = <0x103>;
162			enable-method = "psci";
163			capacity-dmips-mhz = <1024>;
164			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
165			dynamic-power-coefficient = <211>;
166			#cooling-cells = <2>;
167		};
168
169		idle-states {
170			entry-method = "psci";
171
172			CPU_SLEEP: cpu-sleep {
173				compatible = "arm,idle-state";
174				local-timer-stop;
175				arm,psci-suspend-param = <0x00010001>;
176				entry-latency-us = <200>;
177				exit-latency-us = <200>;
178				min-residency-us = <800>;
179			};
180
181			CLUSTER_SLEEP0: cluster-sleep-0 {
182				compatible = "arm,idle-state";
183				local-timer-stop;
184				arm,psci-suspend-param = <0x01010001>;
185				entry-latency-us = <250>;
186				exit-latency-us = <400>;
187				min-residency-us = <1000>;
188			};
189			CLUSTER_SLEEP1: cluster-sleep-1 {
190				compatible = "arm,idle-state";
191				local-timer-stop;
192				arm,psci-suspend-param = <0x01010001>;
193				entry-latency-us = <250>;
194				exit-latency-us = <400>;
195				min-residency-us = <1300>;
196			};
197		};
198	};
199
200	gpu_opp_table: opp_table0 {
201		compatible = "operating-points-v2";
202		opp-shared;
203
204		opp-300000000 {
205			opp-hz = /bits/ 64 <300000000>;
206			opp-microvolt = <625000>, <850000>;
207		};
208
209		opp-320000000 {
210			opp-hz = /bits/ 64 <320000000>;
211			opp-microvolt = <631250>, <850000>;
212		};
213
214		opp-340000000 {
215			opp-hz = /bits/ 64 <340000000>;
216			opp-microvolt = <637500>, <850000>;
217		};
218
219		opp-360000000 {
220			opp-hz = /bits/ 64 <360000000>;
221			opp-microvolt = <643750>, <850000>;
222		};
223
224		opp-380000000 {
225			opp-hz = /bits/ 64 <380000000>;
226			opp-microvolt = <650000>, <850000>;
227		};
228
229		opp-400000000 {
230			opp-hz = /bits/ 64 <400000000>;
231			opp-microvolt = <656250>, <850000>;
232		};
233
234		opp-420000000 {
235			opp-hz = /bits/ 64 <420000000>;
236			opp-microvolt = <662500>, <850000>;
237		};
238
239		opp-460000000 {
240			opp-hz = /bits/ 64 <460000000>;
241			opp-microvolt = <675000>, <850000>;
242		};
243
244		opp-500000000 {
245			opp-hz = /bits/ 64 <500000000>;
246			opp-microvolt = <687500>, <850000>;
247		};
248
249		opp-540000000 {
250			opp-hz = /bits/ 64 <540000000>;
251			opp-microvolt = <700000>, <850000>;
252		};
253
254		opp-580000000 {
255			opp-hz = /bits/ 64 <580000000>;
256			opp-microvolt = <712500>, <850000>;
257		};
258
259		opp-620000000 {
260			opp-hz = /bits/ 64 <620000000>;
261			opp-microvolt = <725000>, <850000>;
262		};
263
264		opp-653000000 {
265			opp-hz = /bits/ 64 <653000000>;
266			opp-microvolt = <743750>, <850000>;
267		};
268
269		opp-698000000 {
270			opp-hz = /bits/ 64 <698000000>;
271			opp-microvolt = <768750>, <868750>;
272		};
273
274		opp-743000000 {
275			opp-hz = /bits/ 64 <743000000>;
276			opp-microvolt = <793750>, <893750>;
277		};
278
279		opp-800000000 {
280			opp-hz = /bits/ 64 <800000000>;
281			opp-microvolt = <825000>, <925000>;
282		};
283	};
284
285	pmu-a53 {
286		compatible = "arm,cortex-a53-pmu";
287		interrupt-parent = <&gic>;
288		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
289	};
290
291	pmu-a73 {
292		compatible = "arm,cortex-a73-pmu";
293		interrupt-parent = <&gic>;
294		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
295	};
296
297	psci {
298		compatible      = "arm,psci-1.0";
299		method          = "smc";
300	};
301
302	clk26m: oscillator {
303		compatible = "fixed-clock";
304		#clock-cells = <0>;
305		clock-frequency = <26000000>;
306		clock-output-names = "clk26m";
307	};
308
309	timer {
310		compatible = "arm,armv8-timer";
311		interrupt-parent = <&gic>;
312		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
313			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
314			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
315			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
316	};
317
318	soc {
319		#address-cells = <2>;
320		#size-cells = <2>;
321		compatible = "simple-bus";
322		ranges;
323
324		soc_data: soc_data@8000000 {
325			compatible = "mediatek,mt8183-efuse",
326				     "mediatek,efuse";
327			reg = <0 0x08000000 0 0x0010>;
328			#address-cells = <1>;
329			#size-cells = <1>;
330			status = "disabled";
331		};
332
333		gic: interrupt-controller@c000000 {
334			compatible = "arm,gic-v3";
335			#interrupt-cells = <4>;
336			interrupt-parent = <&gic>;
337			interrupt-controller;
338			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
339			      <0 0x0c100000 0 0x200000>, /* GICR */
340			      <0 0x0c400000 0 0x2000>,   /* GICC */
341			      <0 0x0c410000 0 0x1000>,   /* GICH */
342			      <0 0x0c420000 0 0x2000>;   /* GICV */
343
344			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
345			ppi-partitions {
346				ppi_cluster0: interrupt-partition-0 {
347					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
348				};
349				ppi_cluster1: interrupt-partition-1 {
350					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
351				};
352			};
353		};
354
355		mcucfg: syscon@c530000 {
356			compatible = "mediatek,mt8183-mcucfg", "syscon";
357			reg = <0 0x0c530000 0 0x1000>;
358			#clock-cells = <1>;
359		};
360
361		sysirq: interrupt-controller@c530a80 {
362			compatible = "mediatek,mt8183-sysirq",
363				     "mediatek,mt6577-sysirq";
364			interrupt-controller;
365			#interrupt-cells = <3>;
366			interrupt-parent = <&gic>;
367			reg = <0 0x0c530a80 0 0x50>;
368		};
369
370		cpu_debug0: cpu-debug@d410000 {
371			compatible = "arm,coresight-cpu-debug", "arm,primecell";
372			reg = <0x0 0xd410000 0x0 0x1000>;
373			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
374			clock-names = "apb_pclk";
375			cpu = <&cpu0>;
376		};
377
378		cpu_debug1: cpu-debug@d510000 {
379			compatible = "arm,coresight-cpu-debug", "arm,primecell";
380			reg = <0x0 0xd510000 0x0 0x1000>;
381			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
382			clock-names = "apb_pclk";
383			cpu = <&cpu1>;
384		};
385
386		cpu_debug2: cpu-debug@d610000 {
387			compatible = "arm,coresight-cpu-debug", "arm,primecell";
388			reg = <0x0 0xd610000 0x0 0x1000>;
389			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
390			clock-names = "apb_pclk";
391			cpu = <&cpu2>;
392		};
393
394		cpu_debug3: cpu-debug@d710000 {
395			compatible = "arm,coresight-cpu-debug", "arm,primecell";
396			reg = <0x0 0xd710000 0x0 0x1000>;
397			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
398			clock-names = "apb_pclk";
399			cpu = <&cpu3>;
400		};
401
402		cpu_debug4: cpu-debug@d810000 {
403			compatible = "arm,coresight-cpu-debug", "arm,primecell";
404			reg = <0x0 0xd810000 0x0 0x1000>;
405			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
406			clock-names = "apb_pclk";
407			cpu = <&cpu4>;
408		};
409
410		cpu_debug5: cpu-debug@d910000 {
411			compatible = "arm,coresight-cpu-debug", "arm,primecell";
412			reg = <0x0 0xd910000 0x0 0x1000>;
413			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
414			clock-names = "apb_pclk";
415			cpu = <&cpu5>;
416		};
417
418		cpu_debug6: cpu-debug@da10000 {
419			compatible = "arm,coresight-cpu-debug", "arm,primecell";
420			reg = <0x0 0xda10000 0x0 0x1000>;
421			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
422			clock-names = "apb_pclk";
423			cpu = <&cpu6>;
424		};
425
426		cpu_debug7: cpu-debug@db10000 {
427			compatible = "arm,coresight-cpu-debug", "arm,primecell";
428			reg = <0x0 0xdb10000 0x0 0x1000>;
429			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
430			clock-names = "apb_pclk";
431			cpu = <&cpu7>;
432		};
433
434		topckgen: syscon@10000000 {
435			compatible = "mediatek,mt8183-topckgen", "syscon";
436			reg = <0 0x10000000 0 0x1000>;
437			#clock-cells = <1>;
438		};
439
440		infracfg: syscon@10001000 {
441			compatible = "mediatek,mt8183-infracfg", "syscon";
442			reg = <0 0x10001000 0 0x1000>;
443			#clock-cells = <1>;
444			#reset-cells = <1>;
445		};
446
447		pericfg: syscon@10003000 {
448			compatible = "mediatek,mt8183-pericfg", "syscon";
449			reg = <0 0x10003000 0 0x1000>;
450			#clock-cells = <1>;
451		};
452
453		pio: pinctrl@10005000 {
454			compatible = "mediatek,mt8183-pinctrl";
455			reg = <0 0x10005000 0 0x1000>,
456			      <0 0x11f20000 0 0x1000>,
457			      <0 0x11e80000 0 0x1000>,
458			      <0 0x11e70000 0 0x1000>,
459			      <0 0x11e90000 0 0x1000>,
460			      <0 0x11d30000 0 0x1000>,
461			      <0 0x11d20000 0 0x1000>,
462			      <0 0x11c50000 0 0x1000>,
463			      <0 0x11f30000 0 0x1000>,
464			      <0 0x1000b000 0 0x1000>;
465			reg-names = "iocfg0", "iocfg1", "iocfg2",
466				    "iocfg3", "iocfg4", "iocfg5",
467				    "iocfg6", "iocfg7", "iocfg8",
468				    "eint";
469			gpio-controller;
470			#gpio-cells = <2>;
471			gpio-ranges = <&pio 0 0 192>;
472			interrupt-controller;
473			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
474			#interrupt-cells = <2>;
475		};
476
477		scpsys: syscon@10006000 {
478			compatible = "syscon", "simple-mfd";
479			reg = <0 0x10006000 0 0x1000>;
480			#power-domain-cells = <1>;
481
482			/* System Power Manager */
483			spm: power-controller {
484				compatible = "mediatek,mt8183-power-controller";
485				#address-cells = <1>;
486				#size-cells = <0>;
487				#power-domain-cells = <1>;
488
489				/* power domain of the SoC */
490				power-domain@MT8183_POWER_DOMAIN_AUDIO {
491					reg = <MT8183_POWER_DOMAIN_AUDIO>;
492					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
493						 <&infracfg CLK_INFRA_AUDIO>,
494						 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
495					clock-names = "audio", "audio1", "audio2";
496					#power-domain-cells = <0>;
497				};
498
499				power-domain@MT8183_POWER_DOMAIN_CONN {
500					reg = <MT8183_POWER_DOMAIN_CONN>;
501					mediatek,infracfg = <&infracfg>;
502					#power-domain-cells = <0>;
503				};
504
505				power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
506					reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
507					clocks =  <&topckgen CLK_TOP_MUX_MFG>;
508					clock-names = "mfg";
509					#address-cells = <1>;
510					#size-cells = <0>;
511					#power-domain-cells = <1>;
512
513					mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
514						reg = <MT8183_POWER_DOMAIN_MFG>;
515						#address-cells = <1>;
516						#size-cells = <0>;
517						#power-domain-cells = <1>;
518
519						power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
520							reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
521							#power-domain-cells = <0>;
522						};
523
524						power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
525							reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
526							#power-domain-cells = <0>;
527						};
528
529						power-domain@MT8183_POWER_DOMAIN_MFG_2D {
530							reg = <MT8183_POWER_DOMAIN_MFG_2D>;
531							mediatek,infracfg = <&infracfg>;
532							#power-domain-cells = <0>;
533						};
534					};
535				};
536
537				power-domain@MT8183_POWER_DOMAIN_DISP {
538					reg = <MT8183_POWER_DOMAIN_DISP>;
539					clocks = <&topckgen CLK_TOP_MUX_MM>,
540						 <&mmsys CLK_MM_SMI_COMMON>,
541						 <&mmsys CLK_MM_SMI_LARB0>,
542						 <&mmsys CLK_MM_SMI_LARB1>,
543						 <&mmsys CLK_MM_GALS_COMM0>,
544						 <&mmsys CLK_MM_GALS_COMM1>,
545						 <&mmsys CLK_MM_GALS_CCU2MM>,
546						 <&mmsys CLK_MM_GALS_IPU12MM>,
547						 <&mmsys CLK_MM_GALS_IMG2MM>,
548						 <&mmsys CLK_MM_GALS_CAM2MM>,
549						 <&mmsys CLK_MM_GALS_IPU2MM>;
550					clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
551						      "mm-4", "mm-5", "mm-6", "mm-7",
552						      "mm-8", "mm-9";
553					mediatek,infracfg = <&infracfg>;
554					mediatek,smi = <&smi_common>;
555					#address-cells = <1>;
556					#size-cells = <0>;
557					#power-domain-cells = <1>;
558
559					power-domain@MT8183_POWER_DOMAIN_CAM {
560						reg = <MT8183_POWER_DOMAIN_CAM>;
561						clocks = <&topckgen CLK_TOP_MUX_CAM>,
562							 <&camsys CLK_CAM_LARB6>,
563							 <&camsys CLK_CAM_LARB3>,
564							 <&camsys CLK_CAM_SENINF>,
565							 <&camsys CLK_CAM_CAMSV0>,
566							 <&camsys CLK_CAM_CAMSV1>,
567							 <&camsys CLK_CAM_CAMSV2>,
568							 <&camsys CLK_CAM_CCU>;
569						clock-names = "cam", "cam-0", "cam-1",
570							      "cam-2", "cam-3", "cam-4",
571							      "cam-5", "cam-6";
572						mediatek,infracfg = <&infracfg>;
573						mediatek,smi = <&smi_common>;
574						#power-domain-cells = <0>;
575					};
576
577					power-domain@MT8183_POWER_DOMAIN_ISP {
578						reg = <MT8183_POWER_DOMAIN_ISP>;
579						clocks = <&topckgen CLK_TOP_MUX_IMG>,
580							 <&imgsys CLK_IMG_LARB5>,
581							 <&imgsys CLK_IMG_LARB2>;
582						clock-names = "isp", "isp-0", "isp-1";
583						mediatek,infracfg = <&infracfg>;
584						mediatek,smi = <&smi_common>;
585						#power-domain-cells = <0>;
586					};
587
588					power-domain@MT8183_POWER_DOMAIN_VDEC {
589						reg = <MT8183_POWER_DOMAIN_VDEC>;
590						mediatek,smi = <&smi_common>;
591						#power-domain-cells = <0>;
592					};
593
594					power-domain@MT8183_POWER_DOMAIN_VENC {
595						reg = <MT8183_POWER_DOMAIN_VENC>;
596						mediatek,smi = <&smi_common>;
597						#power-domain-cells = <0>;
598					};
599
600					power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
601						reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
602						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
603							 <&topckgen CLK_TOP_MUX_DSP>,
604							 <&ipu_conn CLK_IPU_CONN_IPU>,
605							 <&ipu_conn CLK_IPU_CONN_AHB>,
606							 <&ipu_conn CLK_IPU_CONN_AXI>,
607							 <&ipu_conn CLK_IPU_CONN_ISP>,
608							 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
609							 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
610						clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
611							      "vpu-2", "vpu-3", "vpu-4", "vpu-5";
612						mediatek,infracfg = <&infracfg>;
613						mediatek,smi = <&smi_common>;
614						#address-cells = <1>;
615						#size-cells = <0>;
616						#power-domain-cells = <1>;
617
618						power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
619							reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
620							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
621							clock-names = "vpu2";
622							mediatek,infracfg = <&infracfg>;
623							#power-domain-cells = <0>;
624						};
625
626						power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
627							reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
628							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
629							clock-names = "vpu3";
630							mediatek,infracfg = <&infracfg>;
631							#power-domain-cells = <0>;
632						};
633					};
634				};
635			};
636		};
637
638		watchdog: watchdog@10007000 {
639			compatible = "mediatek,mt8183-wdt";
640			reg = <0 0x10007000 0 0x100>;
641			#reset-cells = <1>;
642		};
643
644		apmixedsys: syscon@1000c000 {
645			compatible = "mediatek,mt8183-apmixedsys", "syscon";
646			reg = <0 0x1000c000 0 0x1000>;
647			#clock-cells = <1>;
648		};
649
650		pwrap: pwrap@1000d000 {
651			compatible = "mediatek,mt8183-pwrap";
652			reg = <0 0x1000d000 0 0x1000>;
653			reg-names = "pwrap";
654			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
655			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
656				 <&infracfg CLK_INFRA_PMIC_AP>;
657			clock-names = "spi", "wrap";
658		};
659
660		scp: scp@10500000 {
661			compatible = "mediatek,mt8183-scp";
662			reg = <0 0x10500000 0 0x80000>,
663			      <0 0x105c0000 0 0x19080>;
664			reg-names = "sram", "cfg";
665			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
666			clocks = <&infracfg CLK_INFRA_SCPSYS>;
667			clock-names = "main";
668			memory-region = <&scp_mem_reserved>;
669			status = "disabled";
670		};
671
672		systimer: timer@10017000 {
673			compatible = "mediatek,mt8183-timer",
674				     "mediatek,mt6765-timer";
675			reg = <0 0x10017000 0 0x1000>;
676			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
677			clocks = <&topckgen CLK_TOP_CLK13M>;
678			clock-names = "clk13m";
679		};
680
681		iommu: iommu@10205000 {
682			compatible = "mediatek,mt8183-m4u";
683			reg = <0 0x10205000 0 0x1000>;
684			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
685			mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
686					  &larb4 &larb5 &larb6>;
687			#iommu-cells = <1>;
688		};
689
690		gce: mailbox@10238000 {
691			compatible = "mediatek,mt8183-gce";
692			reg = <0 0x10238000 0 0x4000>;
693			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
694			#mbox-cells = <2>;
695			clocks = <&infracfg CLK_INFRA_GCE>;
696			clock-names = "gce";
697		};
698
699		auxadc: auxadc@11001000 {
700			compatible = "mediatek,mt8183-auxadc",
701				     "mediatek,mt8173-auxadc";
702			reg = <0 0x11001000 0 0x1000>;
703			clocks = <&infracfg CLK_INFRA_AUXADC>;
704			clock-names = "main";
705			#io-channel-cells = <1>;
706			status = "disabled";
707		};
708
709		uart0: serial@11002000 {
710			compatible = "mediatek,mt8183-uart",
711				     "mediatek,mt6577-uart";
712			reg = <0 0x11002000 0 0x1000>;
713			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
714			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
715			clock-names = "baud", "bus";
716			status = "disabled";
717		};
718
719		uart1: serial@11003000 {
720			compatible = "mediatek,mt8183-uart",
721				     "mediatek,mt6577-uart";
722			reg = <0 0x11003000 0 0x1000>;
723			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
724			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
725			clock-names = "baud", "bus";
726			status = "disabled";
727		};
728
729		uart2: serial@11004000 {
730			compatible = "mediatek,mt8183-uart",
731				     "mediatek,mt6577-uart";
732			reg = <0 0x11004000 0 0x1000>;
733			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
734			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
735			clock-names = "baud", "bus";
736			status = "disabled";
737		};
738
739		i2c6: i2c@11005000 {
740			compatible = "mediatek,mt8183-i2c";
741			reg = <0 0x11005000 0 0x1000>,
742			      <0 0x11000600 0 0x80>;
743			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
744			clocks = <&infracfg CLK_INFRA_I2C6>,
745				 <&infracfg CLK_INFRA_AP_DMA>;
746			clock-names = "main", "dma";
747			clock-div = <1>;
748			#address-cells = <1>;
749			#size-cells = <0>;
750			status = "disabled";
751		};
752
753		i2c0: i2c@11007000 {
754			compatible = "mediatek,mt8183-i2c";
755			reg = <0 0x11007000 0 0x1000>,
756			      <0 0x11000080 0 0x80>;
757			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
758			clocks = <&infracfg CLK_INFRA_I2C0>,
759				 <&infracfg CLK_INFRA_AP_DMA>;
760			clock-names = "main", "dma";
761			clock-div = <1>;
762			#address-cells = <1>;
763			#size-cells = <0>;
764			status = "disabled";
765		};
766
767		i2c4: i2c@11008000 {
768			compatible = "mediatek,mt8183-i2c";
769			reg = <0 0x11008000 0 0x1000>,
770			      <0 0x11000100 0 0x80>;
771			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
772			clocks = <&infracfg CLK_INFRA_I2C1>,
773				 <&infracfg CLK_INFRA_AP_DMA>,
774				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
775			clock-names = "main", "dma","arb";
776			clock-div = <1>;
777			#address-cells = <1>;
778			#size-cells = <0>;
779			status = "disabled";
780		};
781
782		i2c2: i2c@11009000 {
783			compatible = "mediatek,mt8183-i2c";
784			reg = <0 0x11009000 0 0x1000>,
785			      <0 0x11000280 0 0x80>;
786			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
787			clocks = <&infracfg CLK_INFRA_I2C2>,
788				 <&infracfg CLK_INFRA_AP_DMA>,
789				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
790			clock-names = "main", "dma", "arb";
791			clock-div = <1>;
792			#address-cells = <1>;
793			#size-cells = <0>;
794			status = "disabled";
795		};
796
797		spi0: spi@1100a000 {
798			compatible = "mediatek,mt8183-spi";
799			#address-cells = <1>;
800			#size-cells = <0>;
801			reg = <0 0x1100a000 0 0x1000>;
802			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
803			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
804				 <&topckgen CLK_TOP_MUX_SPI>,
805				 <&infracfg CLK_INFRA_SPI0>;
806			clock-names = "parent-clk", "sel-clk", "spi-clk";
807			status = "disabled";
808		};
809
810		thermal: thermal@1100b000 {
811			#thermal-sensor-cells = <1>;
812			compatible = "mediatek,mt8183-thermal";
813			reg = <0 0x1100b000 0 0x1000>;
814			clocks = <&infracfg CLK_INFRA_THERM>,
815				 <&infracfg CLK_INFRA_AUXADC>;
816			clock-names = "therm", "auxadc";
817			resets = <&infracfg  MT8183_INFRACFG_AO_THERM_SW_RST>;
818			interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
819			mediatek,auxadc = <&auxadc>;
820			mediatek,apmixedsys = <&apmixedsys>;
821			nvmem-cells = <&thermal_calibration>;
822			nvmem-cell-names = "calibration-data";
823		};
824
825		thermal_zones: thermal-zones {
826			cpu_thermal: cpu_thermal {
827				polling-delay-passive = <100>;
828				polling-delay = <500>;
829				thermal-sensors = <&thermal 0>;
830				sustainable-power = <5000>;
831
832				trips {
833					threshold: trip-point0 {
834						temperature = <68000>;
835						hysteresis = <2000>;
836						type = "passive";
837					};
838
839					target: trip-point1 {
840						temperature = <80000>;
841						hysteresis = <2000>;
842						type = "passive";
843					};
844
845					cpu_crit: cpu-crit {
846						temperature = <115000>;
847						hysteresis = <2000>;
848						type = "critical";
849					};
850				};
851
852				cooling-maps {
853					map0 {
854						trip = <&target>;
855						cooling-device = <&cpu0
856							THERMAL_NO_LIMIT
857							THERMAL_NO_LIMIT>,
858								 <&cpu1
859							THERMAL_NO_LIMIT
860							THERMAL_NO_LIMIT>,
861								 <&cpu2
862							THERMAL_NO_LIMIT
863							THERMAL_NO_LIMIT>,
864								 <&cpu3
865							THERMAL_NO_LIMIT
866							THERMAL_NO_LIMIT>;
867						contribution = <3072>;
868					};
869					map1 {
870						trip = <&target>;
871						cooling-device = <&cpu4
872							THERMAL_NO_LIMIT
873							THERMAL_NO_LIMIT>,
874								 <&cpu5
875							THERMAL_NO_LIMIT
876							THERMAL_NO_LIMIT>,
877								 <&cpu6
878							THERMAL_NO_LIMIT
879							THERMAL_NO_LIMIT>,
880								 <&cpu7
881							THERMAL_NO_LIMIT
882							THERMAL_NO_LIMIT>;
883						contribution = <1024>;
884					};
885				};
886			};
887
888			/* The tzts1 ~ tzts6 don't need to polling */
889			/* The tzts1 ~ tzts6 don't need to thermal throttle */
890
891			tzts1: tzts1 {
892				polling-delay-passive = <0>;
893				polling-delay = <0>;
894				thermal-sensors = <&thermal 1>;
895				sustainable-power = <5000>;
896				trips {};
897				cooling-maps {};
898			};
899
900			tzts2: tzts2 {
901				polling-delay-passive = <0>;
902				polling-delay = <0>;
903				thermal-sensors = <&thermal 2>;
904				sustainable-power = <5000>;
905				trips {};
906				cooling-maps {};
907			};
908
909			tzts3: tzts3 {
910				polling-delay-passive = <0>;
911				polling-delay = <0>;
912				thermal-sensors = <&thermal 3>;
913				sustainable-power = <5000>;
914				trips {};
915				cooling-maps {};
916			};
917
918			tzts4: tzts4 {
919				polling-delay-passive = <0>;
920				polling-delay = <0>;
921				thermal-sensors = <&thermal 4>;
922				sustainable-power = <5000>;
923				trips {};
924				cooling-maps {};
925			};
926
927			tzts5: tzts5 {
928				polling-delay-passive = <0>;
929				polling-delay = <0>;
930				thermal-sensors = <&thermal 5>;
931				sustainable-power = <5000>;
932				trips {};
933				cooling-maps {};
934			};
935
936			tztsABB: tztsABB {
937				polling-delay-passive = <0>;
938				polling-delay = <0>;
939				thermal-sensors = <&thermal 6>;
940				sustainable-power = <5000>;
941				trips {};
942				cooling-maps {};
943			};
944		};
945
946		pwm0: pwm@1100e000 {
947			compatible = "mediatek,mt8183-disp-pwm";
948			reg = <0 0x1100e000 0 0x1000>;
949			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
950			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
951			#pwm-cells = <2>;
952			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
953					<&infracfg CLK_INFRA_DISP_PWM>;
954			clock-names = "main", "mm";
955		};
956
957		pwm1: pwm@11006000 {
958			compatible = "mediatek,mt8183-pwm";
959			reg = <0 0x11006000 0 0x1000>;
960			#pwm-cells = <2>;
961			clocks = <&infracfg CLK_INFRA_PWM>,
962				 <&infracfg CLK_INFRA_PWM_HCLK>,
963				 <&infracfg CLK_INFRA_PWM1>,
964				 <&infracfg CLK_INFRA_PWM2>,
965				 <&infracfg CLK_INFRA_PWM3>,
966				 <&infracfg CLK_INFRA_PWM4>;
967			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
968				      "pwm4";
969		};
970
971		i2c3: i2c@1100f000 {
972			compatible = "mediatek,mt8183-i2c";
973			reg = <0 0x1100f000 0 0x1000>,
974			      <0 0x11000400 0 0x80>;
975			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
976			clocks = <&infracfg CLK_INFRA_I2C3>,
977				 <&infracfg CLK_INFRA_AP_DMA>;
978			clock-names = "main", "dma";
979			clock-div = <1>;
980			#address-cells = <1>;
981			#size-cells = <0>;
982			status = "disabled";
983		};
984
985		spi1: spi@11010000 {
986			compatible = "mediatek,mt8183-spi";
987			#address-cells = <1>;
988			#size-cells = <0>;
989			reg = <0 0x11010000 0 0x1000>;
990			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
991			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
992				 <&topckgen CLK_TOP_MUX_SPI>,
993				 <&infracfg CLK_INFRA_SPI1>;
994			clock-names = "parent-clk", "sel-clk", "spi-clk";
995			status = "disabled";
996		};
997
998		i2c1: i2c@11011000 {
999			compatible = "mediatek,mt8183-i2c";
1000			reg = <0 0x11011000 0 0x1000>,
1001			      <0 0x11000480 0 0x80>;
1002			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
1003			clocks = <&infracfg CLK_INFRA_I2C4>,
1004				 <&infracfg CLK_INFRA_AP_DMA>;
1005			clock-names = "main", "dma";
1006			clock-div = <1>;
1007			#address-cells = <1>;
1008			#size-cells = <0>;
1009			status = "disabled";
1010		};
1011
1012		spi2: spi@11012000 {
1013			compatible = "mediatek,mt8183-spi";
1014			#address-cells = <1>;
1015			#size-cells = <0>;
1016			reg = <0 0x11012000 0 0x1000>;
1017			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
1018			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1019				 <&topckgen CLK_TOP_MUX_SPI>,
1020				 <&infracfg CLK_INFRA_SPI2>;
1021			clock-names = "parent-clk", "sel-clk", "spi-clk";
1022			status = "disabled";
1023		};
1024
1025		spi3: spi@11013000 {
1026			compatible = "mediatek,mt8183-spi";
1027			#address-cells = <1>;
1028			#size-cells = <0>;
1029			reg = <0 0x11013000 0 0x1000>;
1030			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
1031			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1032				 <&topckgen CLK_TOP_MUX_SPI>,
1033				 <&infracfg CLK_INFRA_SPI3>;
1034			clock-names = "parent-clk", "sel-clk", "spi-clk";
1035			status = "disabled";
1036		};
1037
1038		i2c9: i2c@11014000 {
1039			compatible = "mediatek,mt8183-i2c";
1040			reg = <0 0x11014000 0 0x1000>,
1041			      <0 0x11000180 0 0x80>;
1042			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
1043			clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1044				 <&infracfg CLK_INFRA_AP_DMA>,
1045				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1046			clock-names = "main", "dma", "arb";
1047			clock-div = <1>;
1048			#address-cells = <1>;
1049			#size-cells = <0>;
1050			status = "disabled";
1051		};
1052
1053		i2c10: i2c@11015000 {
1054			compatible = "mediatek,mt8183-i2c";
1055			reg = <0 0x11015000 0 0x1000>,
1056			      <0 0x11000300 0 0x80>;
1057			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
1058			clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1059				 <&infracfg CLK_INFRA_AP_DMA>,
1060				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1061			clock-names = "main", "dma", "arb";
1062			clock-div = <1>;
1063			#address-cells = <1>;
1064			#size-cells = <0>;
1065			status = "disabled";
1066		};
1067
1068		i2c5: i2c@11016000 {
1069			compatible = "mediatek,mt8183-i2c";
1070			reg = <0 0x11016000 0 0x1000>,
1071			      <0 0x11000500 0 0x80>;
1072			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
1073			clocks = <&infracfg CLK_INFRA_I2C5>,
1074				 <&infracfg CLK_INFRA_AP_DMA>,
1075				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1076			clock-names = "main", "dma", "arb";
1077			clock-div = <1>;
1078			#address-cells = <1>;
1079			#size-cells = <0>;
1080			status = "disabled";
1081		};
1082
1083		i2c11: i2c@11017000 {
1084			compatible = "mediatek,mt8183-i2c";
1085			reg = <0 0x11017000 0 0x1000>,
1086			      <0 0x11000580 0 0x80>;
1087			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
1088			clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1089				 <&infracfg CLK_INFRA_AP_DMA>,
1090				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1091			clock-names = "main", "dma", "arb";
1092			clock-div = <1>;
1093			#address-cells = <1>;
1094			#size-cells = <0>;
1095			status = "disabled";
1096		};
1097
1098		spi4: spi@11018000 {
1099			compatible = "mediatek,mt8183-spi";
1100			#address-cells = <1>;
1101			#size-cells = <0>;
1102			reg = <0 0x11018000 0 0x1000>;
1103			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
1104			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1105				 <&topckgen CLK_TOP_MUX_SPI>,
1106				 <&infracfg CLK_INFRA_SPI4>;
1107			clock-names = "parent-clk", "sel-clk", "spi-clk";
1108			status = "disabled";
1109		};
1110
1111		spi5: spi@11019000 {
1112			compatible = "mediatek,mt8183-spi";
1113			#address-cells = <1>;
1114			#size-cells = <0>;
1115			reg = <0 0x11019000 0 0x1000>;
1116			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
1117			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1118				 <&topckgen CLK_TOP_MUX_SPI>,
1119				 <&infracfg CLK_INFRA_SPI5>;
1120			clock-names = "parent-clk", "sel-clk", "spi-clk";
1121			status = "disabled";
1122		};
1123
1124		i2c7: i2c@1101a000 {
1125			compatible = "mediatek,mt8183-i2c";
1126			reg = <0 0x1101a000 0 0x1000>,
1127			      <0 0x11000680 0 0x80>;
1128			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
1129			clocks = <&infracfg CLK_INFRA_I2C7>,
1130				 <&infracfg CLK_INFRA_AP_DMA>;
1131			clock-names = "main", "dma";
1132			clock-div = <1>;
1133			#address-cells = <1>;
1134			#size-cells = <0>;
1135			status = "disabled";
1136		};
1137
1138		i2c8: i2c@1101b000 {
1139			compatible = "mediatek,mt8183-i2c";
1140			reg = <0 0x1101b000 0 0x1000>,
1141			      <0 0x11000700 0 0x80>;
1142			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
1143			clocks = <&infracfg CLK_INFRA_I2C8>,
1144				 <&infracfg CLK_INFRA_AP_DMA>;
1145			clock-names = "main", "dma";
1146			clock-div = <1>;
1147			#address-cells = <1>;
1148			#size-cells = <0>;
1149			status = "disabled";
1150		};
1151
1152		ssusb: usb@11201000 {
1153			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
1154			reg = <0 0x11201000 0 0x2e00>,
1155			      <0 0x11203e00 0 0x0100>;
1156			reg-names = "mac", "ippc";
1157			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
1158			phys = <&u2port0 PHY_TYPE_USB2>,
1159			       <&u3port0 PHY_TYPE_USB3>;
1160			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1161				 <&infracfg CLK_INFRA_USB>;
1162			clock-names = "sys_ck", "ref_ck";
1163			mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1164			#address-cells = <2>;
1165			#size-cells = <2>;
1166			ranges;
1167			status = "disabled";
1168
1169			usb_host: usb@11200000 {
1170				compatible = "mediatek,mt8183-xhci",
1171					     "mediatek,mtk-xhci";
1172				reg = <0 0x11200000 0 0x1000>;
1173				reg-names = "mac";
1174				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
1175				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1176					 <&infracfg CLK_INFRA_USB>;
1177				clock-names = "sys_ck", "ref_ck";
1178				status = "disabled";
1179			};
1180		};
1181
1182		audiosys: audio-controller@11220000 {
1183			compatible = "mediatek,mt8183-audiosys", "syscon";
1184			reg = <0 0x11220000 0 0x1000>;
1185			#clock-cells = <1>;
1186			afe: mt8183-afe-pcm {
1187				compatible = "mediatek,mt8183-audio";
1188				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
1189				resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
1190				reset-names = "audiosys";
1191				power-domains =
1192					<&spm MT8183_POWER_DOMAIN_AUDIO>;
1193				clocks = <&audiosys CLK_AUDIO_AFE>,
1194					 <&audiosys CLK_AUDIO_DAC>,
1195					 <&audiosys CLK_AUDIO_DAC_PREDIS>,
1196					 <&audiosys CLK_AUDIO_ADC>,
1197					 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
1198					 <&audiosys CLK_AUDIO_22M>,
1199					 <&audiosys CLK_AUDIO_24M>,
1200					 <&audiosys CLK_AUDIO_APLL_TUNER>,
1201					 <&audiosys CLK_AUDIO_APLL2_TUNER>,
1202					 <&audiosys CLK_AUDIO_I2S1>,
1203					 <&audiosys CLK_AUDIO_I2S2>,
1204					 <&audiosys CLK_AUDIO_I2S3>,
1205					 <&audiosys CLK_AUDIO_I2S4>,
1206					 <&audiosys CLK_AUDIO_TDM>,
1207					 <&audiosys CLK_AUDIO_TML>,
1208					 <&infracfg CLK_INFRA_AUDIO>,
1209					 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1210					 <&topckgen CLK_TOP_MUX_AUDIO>,
1211					 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1212					 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1213					 <&topckgen CLK_TOP_MUX_AUD_1>,
1214					 <&topckgen CLK_TOP_APLL1_CK>,
1215					 <&topckgen CLK_TOP_MUX_AUD_2>,
1216					 <&topckgen CLK_TOP_APLL2_CK>,
1217					 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1218					 <&topckgen CLK_TOP_APLL1_D8>,
1219					 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1220					 <&topckgen CLK_TOP_APLL2_D8>,
1221					 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1222					 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1223					 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1224					 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1225					 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1226					 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1227					 <&topckgen CLK_TOP_APLL12_DIV0>,
1228					 <&topckgen CLK_TOP_APLL12_DIV1>,
1229					 <&topckgen CLK_TOP_APLL12_DIV2>,
1230					 <&topckgen CLK_TOP_APLL12_DIV3>,
1231					 <&topckgen CLK_TOP_APLL12_DIV4>,
1232					 <&topckgen CLK_TOP_APLL12_DIVB>,
1233					 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1234					 <&clk26m>;
1235				clock-names = "aud_afe_clk",
1236						  "aud_dac_clk",
1237						  "aud_dac_predis_clk",
1238						  "aud_adc_clk",
1239						  "aud_adc_adda6_clk",
1240						  "aud_apll22m_clk",
1241						  "aud_apll24m_clk",
1242						  "aud_apll1_tuner_clk",
1243						  "aud_apll2_tuner_clk",
1244						  "aud_i2s1_bclk_sw",
1245						  "aud_i2s2_bclk_sw",
1246						  "aud_i2s3_bclk_sw",
1247						  "aud_i2s4_bclk_sw",
1248						  "aud_tdm_clk",
1249						  "aud_tml_clk",
1250						  "aud_infra_clk",
1251						  "mtkaif_26m_clk",
1252						  "top_mux_audio",
1253						  "top_mux_aud_intbus",
1254						  "top_syspll_d2_d4",
1255						  "top_mux_aud_1",
1256						  "top_apll1_ck",
1257						  "top_mux_aud_2",
1258						  "top_apll2_ck",
1259						  "top_mux_aud_eng1",
1260						  "top_apll1_d8",
1261						  "top_mux_aud_eng2",
1262						  "top_apll2_d8",
1263						  "top_i2s0_m_sel",
1264						  "top_i2s1_m_sel",
1265						  "top_i2s2_m_sel",
1266						  "top_i2s3_m_sel",
1267						  "top_i2s4_m_sel",
1268						  "top_i2s5_m_sel",
1269						  "top_apll12_div0",
1270						  "top_apll12_div1",
1271						  "top_apll12_div2",
1272						  "top_apll12_div3",
1273						  "top_apll12_div4",
1274						  "top_apll12_divb",
1275						  /*"top_apll12_div5",*/
1276						  "top_clk26m_clk";
1277			};
1278		};
1279
1280		mmc0: mmc@11230000 {
1281			compatible = "mediatek,mt8183-mmc";
1282			reg = <0 0x11230000 0 0x1000>,
1283			      <0 0x11f50000 0 0x1000>;
1284			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
1285			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1286				 <&infracfg CLK_INFRA_MSDC0>,
1287				 <&infracfg CLK_INFRA_MSDC0_SCK>;
1288			clock-names = "source", "hclk", "source_cg";
1289			status = "disabled";
1290		};
1291
1292		mmc1: mmc@11240000 {
1293			compatible = "mediatek,mt8183-mmc";
1294			reg = <0 0x11240000 0 0x1000>,
1295			      <0 0x11e10000 0 0x1000>;
1296			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
1297			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1298				 <&infracfg CLK_INFRA_MSDC1>,
1299				 <&infracfg CLK_INFRA_MSDC1_SCK>;
1300			clock-names = "source", "hclk", "source_cg";
1301			status = "disabled";
1302		};
1303
1304		mipi_tx0: dsi-phy@11e50000 {
1305			compatible = "mediatek,mt8183-mipi-tx";
1306			reg = <0 0x11e50000 0 0x1000>;
1307			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
1308			#clock-cells = <0>;
1309			#phy-cells = <0>;
1310			clock-output-names = "mipi_tx0_pll";
1311			nvmem-cells = <&mipi_tx_calibration>;
1312			nvmem-cell-names = "calibration-data";
1313		};
1314
1315		efuse: efuse@11f10000 {
1316			compatible = "mediatek,mt8183-efuse",
1317				     "mediatek,efuse";
1318			reg = <0 0x11f10000 0 0x1000>;
1319			#address-cells = <1>;
1320			#size-cells = <1>;
1321			thermal_calibration: calib@180 {
1322				reg = <0x180 0xc>;
1323			};
1324
1325			mipi_tx_calibration: calib@190 {
1326				reg = <0x190 0xc>;
1327			};
1328		};
1329
1330		u3phy: t-phy@11f40000 {
1331			compatible = "mediatek,mt8183-tphy",
1332				     "mediatek,generic-tphy-v2";
1333			#address-cells = <1>;
1334			#size-cells = <1>;
1335			ranges = <0 0 0x11f40000 0x1000>;
1336			status = "okay";
1337
1338			u2port0: usb-phy@0 {
1339				reg = <0x0 0x700>;
1340				clocks = <&clk26m>;
1341				clock-names = "ref";
1342				#phy-cells = <1>;
1343				mediatek,discth = <15>;
1344				status = "okay";
1345			};
1346
1347			u3port0: usb-phy@700 {
1348				reg = <0x0700 0x900>;
1349				clocks = <&clk26m>;
1350				clock-names = "ref";
1351				#phy-cells = <1>;
1352				status = "okay";
1353			};
1354		};
1355
1356		mfgcfg: syscon@13000000 {
1357			compatible = "mediatek,mt8183-mfgcfg", "syscon";
1358			reg = <0 0x13000000 0 0x1000>;
1359			#clock-cells = <1>;
1360		};
1361
1362		gpu: gpu@13040000 {
1363			compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
1364			reg = <0 0x13040000 0 0x4000>;
1365			interrupts =
1366				<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
1367				<GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
1368				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
1369			interrupt-names = "job", "mmu", "gpu";
1370
1371			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
1372
1373			power-domains =
1374				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
1375				<&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
1376				<&spm MT8183_POWER_DOMAIN_MFG_2D>;
1377			power-domain-names = "core0", "core1", "core2";
1378
1379			operating-points-v2 = <&gpu_opp_table>;
1380		};
1381
1382		mmsys: syscon@14000000 {
1383			compatible = "mediatek,mt8183-mmsys", "syscon";
1384			reg = <0 0x14000000 0 0x1000>;
1385			#clock-cells = <1>;
1386			#reset-cells = <1>;
1387			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1388				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1389			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1390		};
1391
1392		ovl0: ovl@14008000 {
1393			compatible = "mediatek,mt8183-disp-ovl";
1394			reg = <0 0x14008000 0 0x1000>;
1395			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
1396			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1397			clocks = <&mmsys CLK_MM_DISP_OVL0>;
1398			iommus = <&iommu M4U_PORT_DISP_OVL0>;
1399			mediatek,larb = <&larb0>;
1400			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1401		};
1402
1403		ovl_2l0: ovl@14009000 {
1404			compatible = "mediatek,mt8183-disp-ovl-2l";
1405			reg = <0 0x14009000 0 0x1000>;
1406			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
1407			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1408			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1409			iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
1410			mediatek,larb = <&larb0>;
1411			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1412		};
1413
1414		ovl_2l1: ovl@1400a000 {
1415			compatible = "mediatek,mt8183-disp-ovl-2l";
1416			reg = <0 0x1400a000 0 0x1000>;
1417			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
1418			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1419			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1420			iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
1421			mediatek,larb = <&larb0>;
1422			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1423		};
1424
1425		rdma0: rdma@1400b000 {
1426			compatible = "mediatek,mt8183-disp-rdma";
1427			reg = <0 0x1400b000 0 0x1000>;
1428			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
1429			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1430			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1431			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1432			mediatek,larb = <&larb0>;
1433			mediatek,rdma-fifo-size = <5120>;
1434			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1435		};
1436
1437		rdma1: rdma@1400c000 {
1438			compatible = "mediatek,mt8183-disp-rdma";
1439			reg = <0 0x1400c000 0 0x1000>;
1440			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
1441			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1442			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1443			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1444			mediatek,larb = <&larb0>;
1445			mediatek,rdma-fifo-size = <2048>;
1446			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1447		};
1448
1449		color0: color@1400e000 {
1450			compatible = "mediatek,mt8183-disp-color",
1451				     "mediatek,mt8173-disp-color";
1452			reg = <0 0x1400e000 0 0x1000>;
1453			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
1454			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1455			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1456			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1457		};
1458
1459		ccorr0: ccorr@1400f000 {
1460			compatible = "mediatek,mt8183-disp-ccorr";
1461			reg = <0 0x1400f000 0 0x1000>;
1462			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
1463			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1464			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1465			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1466		};
1467
1468		aal0: aal@14010000 {
1469			compatible = "mediatek,mt8183-disp-aal",
1470				     "mediatek,mt8173-disp-aal";
1471			reg = <0 0x14010000 0 0x1000>;
1472			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
1473			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1474			clocks = <&mmsys CLK_MM_DISP_AAL0>;
1475			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1476		};
1477
1478		gamma0: gamma@14011000 {
1479			compatible = "mediatek,mt8183-disp-gamma";
1480			reg = <0 0x14011000 0 0x1000>;
1481			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
1482			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1483			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1484			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1485		};
1486
1487		dither0: dither@14012000 {
1488			compatible = "mediatek,mt8183-disp-dither";
1489			reg = <0 0x14012000 0 0x1000>;
1490			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
1491			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1492			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1493			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1494		};
1495
1496		dsi0: dsi@14014000 {
1497			compatible = "mediatek,mt8183-dsi";
1498			reg = <0 0x14014000 0 0x1000>;
1499			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
1500			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1501			clocks = <&mmsys CLK_MM_DSI0_MM>,
1502				 <&mmsys CLK_MM_DSI0_IF>,
1503				 <&mipi_tx0>;
1504			clock-names = "engine", "digital", "hs";
1505			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
1506			phys = <&mipi_tx0>;
1507			phy-names = "dphy";
1508		};
1509
1510		mutex: mutex@14016000 {
1511			compatible = "mediatek,mt8183-disp-mutex";
1512			reg = <0 0x14016000 0 0x1000>;
1513			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
1514			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1515			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1516					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
1517		};
1518
1519		larb0: larb@14017000 {
1520			compatible = "mediatek,mt8183-smi-larb";
1521			reg = <0 0x14017000 0 0x1000>;
1522			mediatek,smi = <&smi_common>;
1523			clocks = <&mmsys CLK_MM_SMI_LARB0>,
1524				 <&mmsys CLK_MM_SMI_LARB0>;
1525			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1526			clock-names = "apb", "smi";
1527		};
1528
1529		smi_common: smi@14019000 {
1530			compatible = "mediatek,mt8183-smi-common";
1531			reg = <0 0x14019000 0 0x1000>;
1532			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1533				 <&mmsys CLK_MM_SMI_COMMON>,
1534				 <&mmsys CLK_MM_GALS_COMM0>,
1535				 <&mmsys CLK_MM_GALS_COMM1>;
1536			clock-names = "apb", "smi", "gals0", "gals1";
1537			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1538		};
1539
1540		imgsys: syscon@15020000 {
1541			compatible = "mediatek,mt8183-imgsys", "syscon";
1542			reg = <0 0x15020000 0 0x1000>;
1543			#clock-cells = <1>;
1544		};
1545
1546		larb5: larb@15021000 {
1547			compatible = "mediatek,mt8183-smi-larb";
1548			reg = <0 0x15021000 0 0x1000>;
1549			mediatek,smi = <&smi_common>;
1550			clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
1551				 <&mmsys CLK_MM_GALS_IMG2MM>;
1552			clock-names = "apb", "smi", "gals";
1553			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1554		};
1555
1556		larb2: larb@1502f000 {
1557			compatible = "mediatek,mt8183-smi-larb";
1558			reg = <0 0x1502f000 0 0x1000>;
1559			mediatek,smi = <&smi_common>;
1560			clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
1561				 <&mmsys CLK_MM_GALS_IPU2MM>;
1562			clock-names = "apb", "smi", "gals";
1563			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1564		};
1565
1566		vdecsys: syscon@16000000 {
1567			compatible = "mediatek,mt8183-vdecsys", "syscon";
1568			reg = <0 0x16000000 0 0x1000>;
1569			#clock-cells = <1>;
1570		};
1571
1572		larb1: larb@16010000 {
1573			compatible = "mediatek,mt8183-smi-larb";
1574			reg = <0 0x16010000 0 0x1000>;
1575			mediatek,smi = <&smi_common>;
1576			clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
1577			clock-names = "apb", "smi";
1578			power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1579		};
1580
1581		vencsys: syscon@17000000 {
1582			compatible = "mediatek,mt8183-vencsys", "syscon";
1583			reg = <0 0x17000000 0 0x1000>;
1584			#clock-cells = <1>;
1585		};
1586
1587		larb4: larb@17010000 {
1588			compatible = "mediatek,mt8183-smi-larb";
1589			reg = <0 0x17010000 0 0x1000>;
1590			mediatek,smi = <&smi_common>;
1591			clocks = <&vencsys CLK_VENC_LARB>,
1592				 <&vencsys CLK_VENC_LARB>;
1593			clock-names = "apb", "smi";
1594			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1595		};
1596
1597		ipu_conn: syscon@19000000 {
1598			compatible = "mediatek,mt8183-ipu_conn", "syscon";
1599			reg = <0 0x19000000 0 0x1000>;
1600			#clock-cells = <1>;
1601		};
1602
1603		ipu_adl: syscon@19010000 {
1604			compatible = "mediatek,mt8183-ipu_adl", "syscon";
1605			reg = <0 0x19010000 0 0x1000>;
1606			#clock-cells = <1>;
1607		};
1608
1609		ipu_core0: syscon@19180000 {
1610			compatible = "mediatek,mt8183-ipu_core0", "syscon";
1611			reg = <0 0x19180000 0 0x1000>;
1612			#clock-cells = <1>;
1613		};
1614
1615		ipu_core1: syscon@19280000 {
1616			compatible = "mediatek,mt8183-ipu_core1", "syscon";
1617			reg = <0 0x19280000 0 0x1000>;
1618			#clock-cells = <1>;
1619		};
1620
1621		camsys: syscon@1a000000 {
1622			compatible = "mediatek,mt8183-camsys", "syscon";
1623			reg = <0 0x1a000000 0 0x1000>;
1624			#clock-cells = <1>;
1625		};
1626
1627		larb6: larb@1a001000 {
1628			compatible = "mediatek,mt8183-smi-larb";
1629			reg = <0 0x1a001000 0 0x1000>;
1630			mediatek,smi = <&smi_common>;
1631			clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
1632				 <&mmsys CLK_MM_GALS_CAM2MM>;
1633			clock-names = "apb", "smi", "gals";
1634			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1635		};
1636
1637		larb3: larb@1a002000 {
1638			compatible = "mediatek,mt8183-smi-larb";
1639			reg = <0 0x1a002000 0 0x1000>;
1640			mediatek,smi = <&smi_common>;
1641			clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
1642				 <&mmsys CLK_MM_GALS_IPU12MM>;
1643			clock-names = "apb", "smi", "gals";
1644			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1645		};
1646	};
1647};
1648