1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include "mt8183-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt8183"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c7; 29 i2c8 = &i2c8; 30 i2c9 = &i2c9; 31 i2c10 = &i2c10; 32 i2c11 = &i2c11; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 core1 { 45 cpu = <&cpu1>; 46 }; 47 core2 { 48 cpu = <&cpu2>; 49 }; 50 core3 { 51 cpu = <&cpu3>; 52 }; 53 }; 54 55 cluster1 { 56 core0 { 57 cpu = <&cpu4>; 58 }; 59 core1 { 60 cpu = <&cpu5>; 61 }; 62 core2 { 63 cpu = <&cpu6>; 64 }; 65 core3 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x000>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <741>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 78 }; 79 80 cpu1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x001>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <741>; 86 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 87 }; 88 89 cpu2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x002>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <741>; 95 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 96 }; 97 98 cpu3: cpu@3 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x003>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <741>; 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 105 }; 106 107 cpu4: cpu@100 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a73"; 110 reg = <0x100>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 114 }; 115 116 cpu5: cpu@101 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a73"; 119 reg = <0x101>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 123 }; 124 125 cpu6: cpu@102 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a73"; 128 reg = <0x102>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 132 }; 133 134 cpu7: cpu@103 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a73"; 137 reg = <0x103>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 141 }; 142 143 idle-states { 144 entry-method = "psci"; 145 146 CPU_SLEEP: cpu-sleep { 147 compatible = "arm,idle-state"; 148 local-timer-stop; 149 arm,psci-suspend-param = <0x00010001>; 150 entry-latency-us = <200>; 151 exit-latency-us = <200>; 152 min-residency-us = <800>; 153 }; 154 155 CLUSTER_SLEEP: cluster-sleep { 156 compatible = "arm,idle-state"; 157 local-timer-stop; 158 arm,psci-suspend-param = <0x01010001>; 159 entry-latency-us = <250>; 160 exit-latency-us = <400>; 161 min-residency-us = <1300>; 162 }; 163 }; 164 }; 165 166 pmu-a53 { 167 compatible = "arm,cortex-a53-pmu"; 168 interrupt-parent = <&gic>; 169 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 170 }; 171 172 pmu-a73 { 173 compatible = "arm,cortex-a73-pmu"; 174 interrupt-parent = <&gic>; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 clk26m: oscillator { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <26000000>; 187 clock-output-names = "clk26m"; 188 }; 189 190 timer { 191 compatible = "arm,armv8-timer"; 192 interrupt-parent = <&gic>; 193 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 194 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 195 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 196 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 197 }; 198 199 soc { 200 #address-cells = <2>; 201 #size-cells = <2>; 202 compatible = "simple-bus"; 203 ranges; 204 205 soc_data: soc_data@8000000 { 206 compatible = "mediatek,mt8183-efuse", 207 "mediatek,efuse"; 208 reg = <0 0x08000000 0 0x0010>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 status = "disabled"; 212 }; 213 214 gic: interrupt-controller@c000000 { 215 compatible = "arm,gic-v3"; 216 #interrupt-cells = <4>; 217 interrupt-parent = <&gic>; 218 interrupt-controller; 219 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 220 <0 0x0c100000 0 0x200000>, /* GICR */ 221 <0 0x0c400000 0 0x2000>, /* GICC */ 222 <0 0x0c410000 0 0x1000>, /* GICH */ 223 <0 0x0c420000 0 0x2000>; /* GICV */ 224 225 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 226 ppi-partitions { 227 ppi_cluster0: interrupt-partition-0 { 228 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 229 }; 230 ppi_cluster1: interrupt-partition-1 { 231 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 232 }; 233 }; 234 }; 235 236 mcucfg: syscon@c530000 { 237 compatible = "mediatek,mt8183-mcucfg", "syscon"; 238 reg = <0 0x0c530000 0 0x1000>; 239 #clock-cells = <1>; 240 }; 241 242 sysirq: interrupt-controller@c530a80 { 243 compatible = "mediatek,mt8183-sysirq", 244 "mediatek,mt6577-sysirq"; 245 interrupt-controller; 246 #interrupt-cells = <3>; 247 interrupt-parent = <&gic>; 248 reg = <0 0x0c530a80 0 0x50>; 249 }; 250 251 topckgen: syscon@10000000 { 252 compatible = "mediatek,mt8183-topckgen", "syscon"; 253 reg = <0 0x10000000 0 0x1000>; 254 #clock-cells = <1>; 255 }; 256 257 infracfg: syscon@10001000 { 258 compatible = "mediatek,mt8183-infracfg", "syscon"; 259 reg = <0 0x10001000 0 0x1000>; 260 #clock-cells = <1>; 261 #reset-cells = <1>; 262 }; 263 264 pio: pinctrl@10005000 { 265 compatible = "mediatek,mt8183-pinctrl"; 266 reg = <0 0x10005000 0 0x1000>, 267 <0 0x11f20000 0 0x1000>, 268 <0 0x11e80000 0 0x1000>, 269 <0 0x11e70000 0 0x1000>, 270 <0 0x11e90000 0 0x1000>, 271 <0 0x11d30000 0 0x1000>, 272 <0 0x11d20000 0 0x1000>, 273 <0 0x11c50000 0 0x1000>, 274 <0 0x11f30000 0 0x1000>, 275 <0 0x1000b000 0 0x1000>; 276 reg-names = "iocfg0", "iocfg1", "iocfg2", 277 "iocfg3", "iocfg4", "iocfg5", 278 "iocfg6", "iocfg7", "iocfg8", 279 "eint"; 280 gpio-controller; 281 #gpio-cells = <2>; 282 gpio-ranges = <&pio 0 0 192>; 283 interrupt-controller; 284 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 285 #interrupt-cells = <2>; 286 }; 287 288 apmixedsys: syscon@1000c000 { 289 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 290 reg = <0 0x1000c000 0 0x1000>; 291 #clock-cells = <1>; 292 }; 293 294 pwrap: pwrap@1000d000 { 295 compatible = "mediatek,mt8183-pwrap"; 296 reg = <0 0x1000d000 0 0x1000>; 297 reg-names = "pwrap"; 298 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 300 <&infracfg CLK_INFRA_PMIC_AP>; 301 clock-names = "spi", "wrap"; 302 }; 303 304 systimer: timer@10017000 { 305 compatible = "mediatek,mt8183-timer", 306 "mediatek,mt6765-timer"; 307 reg = <0 0x10017000 0 0x1000>; 308 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&topckgen CLK_TOP_CLK13M>; 310 clock-names = "clk13m"; 311 }; 312 313 gce: mailbox@10238000 { 314 compatible = "mediatek,mt8183-gce"; 315 reg = <0 0x10238000 0 0x4000>; 316 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 317 #mbox-cells = <3>; 318 clocks = <&infracfg CLK_INFRA_GCE>; 319 clock-names = "gce"; 320 }; 321 322 auxadc: auxadc@11001000 { 323 compatible = "mediatek,mt8183-auxadc", 324 "mediatek,mt8173-auxadc"; 325 reg = <0 0x11001000 0 0x1000>; 326 clocks = <&infracfg CLK_INFRA_AUXADC>; 327 clock-names = "main"; 328 #io-channel-cells = <1>; 329 status = "disabled"; 330 }; 331 332 uart0: serial@11002000 { 333 compatible = "mediatek,mt8183-uart", 334 "mediatek,mt6577-uart"; 335 reg = <0 0x11002000 0 0x1000>; 336 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 337 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 338 clock-names = "baud", "bus"; 339 status = "disabled"; 340 }; 341 342 uart1: serial@11003000 { 343 compatible = "mediatek,mt8183-uart", 344 "mediatek,mt6577-uart"; 345 reg = <0 0x11003000 0 0x1000>; 346 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 347 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 348 clock-names = "baud", "bus"; 349 status = "disabled"; 350 }; 351 352 uart2: serial@11004000 { 353 compatible = "mediatek,mt8183-uart", 354 "mediatek,mt6577-uart"; 355 reg = <0 0x11004000 0 0x1000>; 356 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 357 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 358 clock-names = "baud", "bus"; 359 status = "disabled"; 360 }; 361 362 i2c6: i2c@11005000 { 363 compatible = "mediatek,mt8183-i2c"; 364 reg = <0 0x11005000 0 0x1000>, 365 <0 0x11000600 0 0x80>; 366 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 367 clocks = <&infracfg CLK_INFRA_I2C6>, 368 <&infracfg CLK_INFRA_AP_DMA>; 369 clock-names = "main", "dma"; 370 clock-div = <1>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 status = "disabled"; 374 }; 375 376 i2c0: i2c@11007000 { 377 compatible = "mediatek,mt8183-i2c"; 378 reg = <0 0x11007000 0 0x1000>, 379 <0 0x11000080 0 0x80>; 380 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 381 clocks = <&infracfg CLK_INFRA_I2C0>, 382 <&infracfg CLK_INFRA_AP_DMA>; 383 clock-names = "main", "dma"; 384 clock-div = <1>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 status = "disabled"; 388 }; 389 390 i2c4: i2c@11008000 { 391 compatible = "mediatek,mt8183-i2c"; 392 reg = <0 0x11008000 0 0x1000>, 393 <0 0x11000100 0 0x80>; 394 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 395 clocks = <&infracfg CLK_INFRA_I2C1>, 396 <&infracfg CLK_INFRA_AP_DMA>, 397 <&infracfg CLK_INFRA_I2C1_ARBITER>; 398 clock-names = "main", "dma","arb"; 399 clock-div = <1>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 i2c2: i2c@11009000 { 406 compatible = "mediatek,mt8183-i2c"; 407 reg = <0 0x11009000 0 0x1000>, 408 <0 0x11000280 0 0x80>; 409 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 410 clocks = <&infracfg CLK_INFRA_I2C2>, 411 <&infracfg CLK_INFRA_AP_DMA>, 412 <&infracfg CLK_INFRA_I2C2_ARBITER>; 413 clock-names = "main", "dma", "arb"; 414 clock-div = <1>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 spi0: spi@1100a000 { 421 compatible = "mediatek,mt8183-spi"; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 reg = <0 0x1100a000 0 0x1000>; 425 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 426 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 427 <&topckgen CLK_TOP_MUX_SPI>, 428 <&infracfg CLK_INFRA_SPI0>; 429 clock-names = "parent-clk", "sel-clk", "spi-clk"; 430 status = "disabled"; 431 }; 432 433 i2c3: i2c@1100f000 { 434 compatible = "mediatek,mt8183-i2c"; 435 reg = <0 0x1100f000 0 0x1000>, 436 <0 0x11000400 0 0x80>; 437 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 438 clocks = <&infracfg CLK_INFRA_I2C3>, 439 <&infracfg CLK_INFRA_AP_DMA>; 440 clock-names = "main", "dma"; 441 clock-div = <1>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 spi1: spi@11010000 { 448 compatible = "mediatek,mt8183-spi"; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 reg = <0 0x11010000 0 0x1000>; 452 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 453 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 454 <&topckgen CLK_TOP_MUX_SPI>, 455 <&infracfg CLK_INFRA_SPI1>; 456 clock-names = "parent-clk", "sel-clk", "spi-clk"; 457 status = "disabled"; 458 }; 459 460 i2c1: i2c@11011000 { 461 compatible = "mediatek,mt8183-i2c"; 462 reg = <0 0x11011000 0 0x1000>, 463 <0 0x11000480 0 0x80>; 464 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 465 clocks = <&infracfg CLK_INFRA_I2C4>, 466 <&infracfg CLK_INFRA_AP_DMA>; 467 clock-names = "main", "dma"; 468 clock-div = <1>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 status = "disabled"; 472 }; 473 474 spi2: spi@11012000 { 475 compatible = "mediatek,mt8183-spi"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <0 0x11012000 0 0x1000>; 479 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 480 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 481 <&topckgen CLK_TOP_MUX_SPI>, 482 <&infracfg CLK_INFRA_SPI2>; 483 clock-names = "parent-clk", "sel-clk", "spi-clk"; 484 status = "disabled"; 485 }; 486 487 spi3: spi@11013000 { 488 compatible = "mediatek,mt8183-spi"; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 reg = <0 0x11013000 0 0x1000>; 492 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 493 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 494 <&topckgen CLK_TOP_MUX_SPI>, 495 <&infracfg CLK_INFRA_SPI3>; 496 clock-names = "parent-clk", "sel-clk", "spi-clk"; 497 status = "disabled"; 498 }; 499 500 i2c9: i2c@11014000 { 501 compatible = "mediatek,mt8183-i2c"; 502 reg = <0 0x11014000 0 0x1000>, 503 <0 0x11000180 0 0x80>; 504 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 505 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 506 <&infracfg CLK_INFRA_AP_DMA>, 507 <&infracfg CLK_INFRA_I2C1_ARBITER>; 508 clock-names = "main", "dma", "arb"; 509 clock-div = <1>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 status = "disabled"; 513 }; 514 515 i2c10: i2c@11015000 { 516 compatible = "mediatek,mt8183-i2c"; 517 reg = <0 0x11015000 0 0x1000>, 518 <0 0x11000300 0 0x80>; 519 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 520 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 521 <&infracfg CLK_INFRA_AP_DMA>, 522 <&infracfg CLK_INFRA_I2C2_ARBITER>; 523 clock-names = "main", "dma", "arb"; 524 clock-div = <1>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 status = "disabled"; 528 }; 529 530 i2c5: i2c@11016000 { 531 compatible = "mediatek,mt8183-i2c"; 532 reg = <0 0x11016000 0 0x1000>, 533 <0 0x11000500 0 0x80>; 534 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 535 clocks = <&infracfg CLK_INFRA_I2C5>, 536 <&infracfg CLK_INFRA_AP_DMA>, 537 <&infracfg CLK_INFRA_I2C5_ARBITER>; 538 clock-names = "main", "dma", "arb"; 539 clock-div = <1>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 status = "disabled"; 543 }; 544 545 i2c11: i2c@11017000 { 546 compatible = "mediatek,mt8183-i2c"; 547 reg = <0 0x11017000 0 0x1000>, 548 <0 0x11000580 0 0x80>; 549 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 550 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 551 <&infracfg CLK_INFRA_AP_DMA>, 552 <&infracfg CLK_INFRA_I2C5_ARBITER>; 553 clock-names = "main", "dma", "arb"; 554 clock-div = <1>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 spi4: spi@11018000 { 561 compatible = "mediatek,mt8183-spi"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <0 0x11018000 0 0x1000>; 565 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 566 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 567 <&topckgen CLK_TOP_MUX_SPI>, 568 <&infracfg CLK_INFRA_SPI4>; 569 clock-names = "parent-clk", "sel-clk", "spi-clk"; 570 status = "disabled"; 571 }; 572 573 spi5: spi@11019000 { 574 compatible = "mediatek,mt8183-spi"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <0 0x11019000 0 0x1000>; 578 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 579 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 580 <&topckgen CLK_TOP_MUX_SPI>, 581 <&infracfg CLK_INFRA_SPI5>; 582 clock-names = "parent-clk", "sel-clk", "spi-clk"; 583 status = "disabled"; 584 }; 585 586 i2c7: i2c@1101a000 { 587 compatible = "mediatek,mt8183-i2c"; 588 reg = <0 0x1101a000 0 0x1000>, 589 <0 0x11000680 0 0x80>; 590 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 591 clocks = <&infracfg CLK_INFRA_I2C7>, 592 <&infracfg CLK_INFRA_AP_DMA>; 593 clock-names = "main", "dma"; 594 clock-div = <1>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 status = "disabled"; 598 }; 599 600 i2c8: i2c@1101b000 { 601 compatible = "mediatek,mt8183-i2c"; 602 reg = <0 0x1101b000 0 0x1000>, 603 <0 0x11000700 0 0x80>; 604 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 605 clocks = <&infracfg CLK_INFRA_I2C8>, 606 <&infracfg CLK_INFRA_AP_DMA>; 607 clock-names = "main", "dma"; 608 clock-div = <1>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "disabled"; 612 }; 613 614 audiosys: syscon@11220000 { 615 compatible = "mediatek,mt8183-audiosys", "syscon"; 616 reg = <0 0x11220000 0 0x1000>; 617 #clock-cells = <1>; 618 }; 619 620 efuse: efuse@11f10000 { 621 compatible = "mediatek,mt8183-efuse", 622 "mediatek,efuse"; 623 reg = <0 0x11f10000 0 0x1000>; 624 }; 625 626 mfgcfg: syscon@13000000 { 627 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 628 reg = <0 0x13000000 0 0x1000>; 629 #clock-cells = <1>; 630 }; 631 632 mmsys: syscon@14000000 { 633 compatible = "mediatek,mt8183-mmsys", "syscon"; 634 reg = <0 0x14000000 0 0x1000>; 635 #clock-cells = <1>; 636 }; 637 638 imgsys: syscon@15020000 { 639 compatible = "mediatek,mt8183-imgsys", "syscon"; 640 reg = <0 0x15020000 0 0x1000>; 641 #clock-cells = <1>; 642 }; 643 644 vdecsys: syscon@16000000 { 645 compatible = "mediatek,mt8183-vdecsys", "syscon"; 646 reg = <0 0x16000000 0 0x1000>; 647 #clock-cells = <1>; 648 }; 649 650 vencsys: syscon@17000000 { 651 compatible = "mediatek,mt8183-vencsys", "syscon"; 652 reg = <0 0x17000000 0 0x1000>; 653 #clock-cells = <1>; 654 }; 655 656 ipu_conn: syscon@19000000 { 657 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 658 reg = <0 0x19000000 0 0x1000>; 659 #clock-cells = <1>; 660 }; 661 662 ipu_adl: syscon@19010000 { 663 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 664 reg = <0 0x19010000 0 0x1000>; 665 #clock-cells = <1>; 666 }; 667 668 ipu_core0: syscon@19180000 { 669 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 670 reg = <0 0x19180000 0 0x1000>; 671 #clock-cells = <1>; 672 }; 673 674 ipu_core1: syscon@19280000 { 675 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 676 reg = <0 0x19280000 0 0x1000>; 677 #clock-cells = <1>; 678 }; 679 680 camsys: syscon@1a000000 { 681 compatible = "mediatek,mt8183-camsys", "syscon"; 682 reg = <0 0x1a000000 0 0x1000>; 683 #clock-cells = <1>; 684 }; 685 }; 686}; 687