1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include <dt-bindings/phy/phy.h> 13#include "mt8183-pinfunc.h" 14 15/ { 16 compatible = "mediatek,mt8183"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 i2c9 = &i2c9; 32 i2c10 = &i2c10; 33 i2c11 = &i2c11; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&cpu0>; 44 }; 45 core1 { 46 cpu = <&cpu1>; 47 }; 48 core2 { 49 cpu = <&cpu2>; 50 }; 51 core3 { 52 cpu = <&cpu3>; 53 }; 54 }; 55 56 cluster1 { 57 core0 { 58 cpu = <&cpu4>; 59 }; 60 core1 { 61 cpu = <&cpu5>; 62 }; 63 core2 { 64 cpu = <&cpu6>; 65 }; 66 core3 { 67 cpu = <&cpu7>; 68 }; 69 }; 70 }; 71 72 cpu0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x000>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <741>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 79 dynamic-power-coefficient = <84>; 80 #cooling-cells = <2>; 81 }; 82 83 cpu1: cpu@1 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x001>; 87 enable-method = "psci"; 88 capacity-dmips-mhz = <741>; 89 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 90 dynamic-power-coefficient = <84>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x002>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <741>; 100 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 101 dynamic-power-coefficient = <84>; 102 #cooling-cells = <2>; 103 }; 104 105 cpu3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x003>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <741>; 111 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 112 dynamic-power-coefficient = <84>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu4: cpu@100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a73"; 119 reg = <0x100>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 123 dynamic-power-coefficient = <211>; 124 #cooling-cells = <2>; 125 }; 126 127 cpu5: cpu@101 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a73"; 130 reg = <0x101>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <1024>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 134 dynamic-power-coefficient = <211>; 135 #cooling-cells = <2>; 136 }; 137 138 cpu6: cpu@102 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a73"; 141 reg = <0x102>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 145 dynamic-power-coefficient = <211>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu7: cpu@103 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a73"; 152 reg = <0x103>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 156 dynamic-power-coefficient = <211>; 157 #cooling-cells = <2>; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 CPU_SLEEP: cpu-sleep { 164 compatible = "arm,idle-state"; 165 local-timer-stop; 166 arm,psci-suspend-param = <0x00010001>; 167 entry-latency-us = <200>; 168 exit-latency-us = <200>; 169 min-residency-us = <800>; 170 }; 171 172 CLUSTER_SLEEP0: cluster-sleep-0 { 173 compatible = "arm,idle-state"; 174 local-timer-stop; 175 arm,psci-suspend-param = <0x01010001>; 176 entry-latency-us = <250>; 177 exit-latency-us = <400>; 178 min-residency-us = <1000>; 179 }; 180 CLUSTER_SLEEP1: cluster-sleep-1 { 181 compatible = "arm,idle-state"; 182 local-timer-stop; 183 arm,psci-suspend-param = <0x01010001>; 184 entry-latency-us = <250>; 185 exit-latency-us = <400>; 186 min-residency-us = <1300>; 187 }; 188 }; 189 }; 190 191 pmu-a53 { 192 compatible = "arm,cortex-a53-pmu"; 193 interrupt-parent = <&gic>; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 195 }; 196 197 pmu-a73 { 198 compatible = "arm,cortex-a73-pmu"; 199 interrupt-parent = <&gic>; 200 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 201 }; 202 203 psci { 204 compatible = "arm,psci-1.0"; 205 method = "smc"; 206 }; 207 208 clk26m: oscillator { 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <26000000>; 212 clock-output-names = "clk26m"; 213 }; 214 215 timer { 216 compatible = "arm,armv8-timer"; 217 interrupt-parent = <&gic>; 218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 222 }; 223 224 soc { 225 #address-cells = <2>; 226 #size-cells = <2>; 227 compatible = "simple-bus"; 228 ranges; 229 230 soc_data: soc_data@8000000 { 231 compatible = "mediatek,mt8183-efuse", 232 "mediatek,efuse"; 233 reg = <0 0x08000000 0 0x0010>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 status = "disabled"; 237 }; 238 239 gic: interrupt-controller@c000000 { 240 compatible = "arm,gic-v3"; 241 #interrupt-cells = <4>; 242 interrupt-parent = <&gic>; 243 interrupt-controller; 244 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 245 <0 0x0c100000 0 0x200000>, /* GICR */ 246 <0 0x0c400000 0 0x2000>, /* GICC */ 247 <0 0x0c410000 0 0x1000>, /* GICH */ 248 <0 0x0c420000 0 0x2000>; /* GICV */ 249 250 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 251 ppi-partitions { 252 ppi_cluster0: interrupt-partition-0 { 253 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 254 }; 255 ppi_cluster1: interrupt-partition-1 { 256 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 257 }; 258 }; 259 }; 260 261 mcucfg: syscon@c530000 { 262 compatible = "mediatek,mt8183-mcucfg", "syscon"; 263 reg = <0 0x0c530000 0 0x1000>; 264 #clock-cells = <1>; 265 }; 266 267 sysirq: interrupt-controller@c530a80 { 268 compatible = "mediatek,mt8183-sysirq", 269 "mediatek,mt6577-sysirq"; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 interrupt-parent = <&gic>; 273 reg = <0 0x0c530a80 0 0x50>; 274 }; 275 276 topckgen: syscon@10000000 { 277 compatible = "mediatek,mt8183-topckgen", "syscon"; 278 reg = <0 0x10000000 0 0x1000>; 279 #clock-cells = <1>; 280 }; 281 282 infracfg: syscon@10001000 { 283 compatible = "mediatek,mt8183-infracfg", "syscon"; 284 reg = <0 0x10001000 0 0x1000>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 }; 288 289 pericfg: syscon@10003000 { 290 compatible = "mediatek,mt8183-pericfg", "syscon"; 291 reg = <0 0x10003000 0 0x1000>; 292 #clock-cells = <1>; 293 }; 294 295 pio: pinctrl@10005000 { 296 compatible = "mediatek,mt8183-pinctrl"; 297 reg = <0 0x10005000 0 0x1000>, 298 <0 0x11f20000 0 0x1000>, 299 <0 0x11e80000 0 0x1000>, 300 <0 0x11e70000 0 0x1000>, 301 <0 0x11e90000 0 0x1000>, 302 <0 0x11d30000 0 0x1000>, 303 <0 0x11d20000 0 0x1000>, 304 <0 0x11c50000 0 0x1000>, 305 <0 0x11f30000 0 0x1000>, 306 <0 0x1000b000 0 0x1000>; 307 reg-names = "iocfg0", "iocfg1", "iocfg2", 308 "iocfg3", "iocfg4", "iocfg5", 309 "iocfg6", "iocfg7", "iocfg8", 310 "eint"; 311 gpio-controller; 312 #gpio-cells = <2>; 313 gpio-ranges = <&pio 0 0 192>; 314 interrupt-controller; 315 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 316 #interrupt-cells = <2>; 317 }; 318 319 watchdog: watchdog@10007000 { 320 compatible = "mediatek,mt8183-wdt", 321 "mediatek,mt6589-wdt"; 322 reg = <0 0x10007000 0 0x100>; 323 #reset-cells = <1>; 324 }; 325 326 apmixedsys: syscon@1000c000 { 327 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 328 reg = <0 0x1000c000 0 0x1000>; 329 #clock-cells = <1>; 330 }; 331 332 pwrap: pwrap@1000d000 { 333 compatible = "mediatek,mt8183-pwrap"; 334 reg = <0 0x1000d000 0 0x1000>; 335 reg-names = "pwrap"; 336 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 338 <&infracfg CLK_INFRA_PMIC_AP>; 339 clock-names = "spi", "wrap"; 340 }; 341 342 systimer: timer@10017000 { 343 compatible = "mediatek,mt8183-timer", 344 "mediatek,mt6765-timer"; 345 reg = <0 0x10017000 0 0x1000>; 346 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&topckgen CLK_TOP_CLK13M>; 348 clock-names = "clk13m"; 349 }; 350 351 gce: mailbox@10238000 { 352 compatible = "mediatek,mt8183-gce"; 353 reg = <0 0x10238000 0 0x4000>; 354 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 355 #mbox-cells = <3>; 356 clocks = <&infracfg CLK_INFRA_GCE>; 357 clock-names = "gce"; 358 }; 359 360 auxadc: auxadc@11001000 { 361 compatible = "mediatek,mt8183-auxadc", 362 "mediatek,mt8173-auxadc"; 363 reg = <0 0x11001000 0 0x1000>; 364 clocks = <&infracfg CLK_INFRA_AUXADC>; 365 clock-names = "main"; 366 #io-channel-cells = <1>; 367 status = "disabled"; 368 }; 369 370 uart0: serial@11002000 { 371 compatible = "mediatek,mt8183-uart", 372 "mediatek,mt6577-uart"; 373 reg = <0 0x11002000 0 0x1000>; 374 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 375 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 376 clock-names = "baud", "bus"; 377 status = "disabled"; 378 }; 379 380 uart1: serial@11003000 { 381 compatible = "mediatek,mt8183-uart", 382 "mediatek,mt6577-uart"; 383 reg = <0 0x11003000 0 0x1000>; 384 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 385 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 386 clock-names = "baud", "bus"; 387 status = "disabled"; 388 }; 389 390 uart2: serial@11004000 { 391 compatible = "mediatek,mt8183-uart", 392 "mediatek,mt6577-uart"; 393 reg = <0 0x11004000 0 0x1000>; 394 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 395 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 396 clock-names = "baud", "bus"; 397 status = "disabled"; 398 }; 399 400 i2c6: i2c@11005000 { 401 compatible = "mediatek,mt8183-i2c"; 402 reg = <0 0x11005000 0 0x1000>, 403 <0 0x11000600 0 0x80>; 404 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 405 clocks = <&infracfg CLK_INFRA_I2C6>, 406 <&infracfg CLK_INFRA_AP_DMA>; 407 clock-names = "main", "dma"; 408 clock-div = <1>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c0: i2c@11007000 { 415 compatible = "mediatek,mt8183-i2c"; 416 reg = <0 0x11007000 0 0x1000>, 417 <0 0x11000080 0 0x80>; 418 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 419 clocks = <&infracfg CLK_INFRA_I2C0>, 420 <&infracfg CLK_INFRA_AP_DMA>; 421 clock-names = "main", "dma"; 422 clock-div = <1>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c4: i2c@11008000 { 429 compatible = "mediatek,mt8183-i2c"; 430 reg = <0 0x11008000 0 0x1000>, 431 <0 0x11000100 0 0x80>; 432 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 433 clocks = <&infracfg CLK_INFRA_I2C1>, 434 <&infracfg CLK_INFRA_AP_DMA>, 435 <&infracfg CLK_INFRA_I2C1_ARBITER>; 436 clock-names = "main", "dma","arb"; 437 clock-div = <1>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 i2c2: i2c@11009000 { 444 compatible = "mediatek,mt8183-i2c"; 445 reg = <0 0x11009000 0 0x1000>, 446 <0 0x11000280 0 0x80>; 447 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 448 clocks = <&infracfg CLK_INFRA_I2C2>, 449 <&infracfg CLK_INFRA_AP_DMA>, 450 <&infracfg CLK_INFRA_I2C2_ARBITER>; 451 clock-names = "main", "dma", "arb"; 452 clock-div = <1>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 spi0: spi@1100a000 { 459 compatible = "mediatek,mt8183-spi"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 reg = <0 0x1100a000 0 0x1000>; 463 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 464 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 465 <&topckgen CLK_TOP_MUX_SPI>, 466 <&infracfg CLK_INFRA_SPI0>; 467 clock-names = "parent-clk", "sel-clk", "spi-clk"; 468 status = "disabled"; 469 }; 470 471 i2c3: i2c@1100f000 { 472 compatible = "mediatek,mt8183-i2c"; 473 reg = <0 0x1100f000 0 0x1000>, 474 <0 0x11000400 0 0x80>; 475 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 476 clocks = <&infracfg CLK_INFRA_I2C3>, 477 <&infracfg CLK_INFRA_AP_DMA>; 478 clock-names = "main", "dma"; 479 clock-div = <1>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 spi1: spi@11010000 { 486 compatible = "mediatek,mt8183-spi"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 reg = <0 0x11010000 0 0x1000>; 490 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 491 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 492 <&topckgen CLK_TOP_MUX_SPI>, 493 <&infracfg CLK_INFRA_SPI1>; 494 clock-names = "parent-clk", "sel-clk", "spi-clk"; 495 status = "disabled"; 496 }; 497 498 i2c1: i2c@11011000 { 499 compatible = "mediatek,mt8183-i2c"; 500 reg = <0 0x11011000 0 0x1000>, 501 <0 0x11000480 0 0x80>; 502 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 503 clocks = <&infracfg CLK_INFRA_I2C4>, 504 <&infracfg CLK_INFRA_AP_DMA>; 505 clock-names = "main", "dma"; 506 clock-div = <1>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 spi2: spi@11012000 { 513 compatible = "mediatek,mt8183-spi"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <0 0x11012000 0 0x1000>; 517 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 518 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 519 <&topckgen CLK_TOP_MUX_SPI>, 520 <&infracfg CLK_INFRA_SPI2>; 521 clock-names = "parent-clk", "sel-clk", "spi-clk"; 522 status = "disabled"; 523 }; 524 525 spi3: spi@11013000 { 526 compatible = "mediatek,mt8183-spi"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <0 0x11013000 0 0x1000>; 530 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 531 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 532 <&topckgen CLK_TOP_MUX_SPI>, 533 <&infracfg CLK_INFRA_SPI3>; 534 clock-names = "parent-clk", "sel-clk", "spi-clk"; 535 status = "disabled"; 536 }; 537 538 i2c9: i2c@11014000 { 539 compatible = "mediatek,mt8183-i2c"; 540 reg = <0 0x11014000 0 0x1000>, 541 <0 0x11000180 0 0x80>; 542 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 543 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 544 <&infracfg CLK_INFRA_AP_DMA>, 545 <&infracfg CLK_INFRA_I2C1_ARBITER>; 546 clock-names = "main", "dma", "arb"; 547 clock-div = <1>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c10: i2c@11015000 { 554 compatible = "mediatek,mt8183-i2c"; 555 reg = <0 0x11015000 0 0x1000>, 556 <0 0x11000300 0 0x80>; 557 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 558 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 559 <&infracfg CLK_INFRA_AP_DMA>, 560 <&infracfg CLK_INFRA_I2C2_ARBITER>; 561 clock-names = "main", "dma", "arb"; 562 clock-div = <1>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 i2c5: i2c@11016000 { 569 compatible = "mediatek,mt8183-i2c"; 570 reg = <0 0x11016000 0 0x1000>, 571 <0 0x11000500 0 0x80>; 572 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 573 clocks = <&infracfg CLK_INFRA_I2C5>, 574 <&infracfg CLK_INFRA_AP_DMA>, 575 <&infracfg CLK_INFRA_I2C5_ARBITER>; 576 clock-names = "main", "dma", "arb"; 577 clock-div = <1>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 i2c11: i2c@11017000 { 584 compatible = "mediatek,mt8183-i2c"; 585 reg = <0 0x11017000 0 0x1000>, 586 <0 0x11000580 0 0x80>; 587 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 588 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 589 <&infracfg CLK_INFRA_AP_DMA>, 590 <&infracfg CLK_INFRA_I2C5_ARBITER>; 591 clock-names = "main", "dma", "arb"; 592 clock-div = <1>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "disabled"; 596 }; 597 598 spi4: spi@11018000 { 599 compatible = "mediatek,mt8183-spi"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 reg = <0 0x11018000 0 0x1000>; 603 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 604 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 605 <&topckgen CLK_TOP_MUX_SPI>, 606 <&infracfg CLK_INFRA_SPI4>; 607 clock-names = "parent-clk", "sel-clk", "spi-clk"; 608 status = "disabled"; 609 }; 610 611 spi5: spi@11019000 { 612 compatible = "mediatek,mt8183-spi"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 reg = <0 0x11019000 0 0x1000>; 616 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 617 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 618 <&topckgen CLK_TOP_MUX_SPI>, 619 <&infracfg CLK_INFRA_SPI5>; 620 clock-names = "parent-clk", "sel-clk", "spi-clk"; 621 status = "disabled"; 622 }; 623 624 i2c7: i2c@1101a000 { 625 compatible = "mediatek,mt8183-i2c"; 626 reg = <0 0x1101a000 0 0x1000>, 627 <0 0x11000680 0 0x80>; 628 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 629 clocks = <&infracfg CLK_INFRA_I2C7>, 630 <&infracfg CLK_INFRA_AP_DMA>; 631 clock-names = "main", "dma"; 632 clock-div = <1>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 i2c8: i2c@1101b000 { 639 compatible = "mediatek,mt8183-i2c"; 640 reg = <0 0x1101b000 0 0x1000>, 641 <0 0x11000700 0 0x80>; 642 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 643 clocks = <&infracfg CLK_INFRA_I2C8>, 644 <&infracfg CLK_INFRA_AP_DMA>; 645 clock-names = "main", "dma"; 646 clock-div = <1>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 ssusb: usb@11201000 { 653 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 654 reg = <0 0x11201000 0 0x2e00>, 655 <0 0x11203e00 0 0x0100>; 656 reg-names = "mac", "ippc"; 657 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 658 phys = <&u2port0 PHY_TYPE_USB2>, 659 <&u3port0 PHY_TYPE_USB3>; 660 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 661 <&infracfg CLK_INFRA_USB>; 662 clock-names = "sys_ck", "ref_ck"; 663 mediatek,syscon-wakeup = <&pericfg 0x400 0>; 664 #address-cells = <2>; 665 #size-cells = <2>; 666 ranges; 667 status = "disabled"; 668 669 usb_host: xhci@11200000 { 670 compatible = "mediatek,mt8183-xhci", 671 "mediatek,mtk-xhci"; 672 reg = <0 0x11200000 0 0x1000>; 673 reg-names = "mac"; 674 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 675 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 676 <&infracfg CLK_INFRA_USB>; 677 clock-names = "sys_ck", "ref_ck"; 678 status = "disabled"; 679 }; 680 }; 681 682 audiosys: syscon@11220000 { 683 compatible = "mediatek,mt8183-audiosys", "syscon"; 684 reg = <0 0x11220000 0 0x1000>; 685 #clock-cells = <1>; 686 }; 687 688 mmc0: mmc@11230000 { 689 compatible = "mediatek,mt8183-mmc"; 690 reg = <0 0x11230000 0 0x1000>, 691 <0 0x11f50000 0 0x1000>; 692 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 693 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 694 <&infracfg CLK_INFRA_MSDC0>, 695 <&infracfg CLK_INFRA_MSDC0_SCK>; 696 clock-names = "source", "hclk", "source_cg"; 697 status = "disabled"; 698 }; 699 700 mmc1: mmc@11240000 { 701 compatible = "mediatek,mt8183-mmc"; 702 reg = <0 0x11240000 0 0x1000>, 703 <0 0x11e10000 0 0x1000>; 704 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 705 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 706 <&infracfg CLK_INFRA_MSDC1>, 707 <&infracfg CLK_INFRA_MSDC1_SCK>; 708 clock-names = "source", "hclk", "source_cg"; 709 status = "disabled"; 710 }; 711 712 efuse: efuse@11f10000 { 713 compatible = "mediatek,mt8183-efuse", 714 "mediatek,efuse"; 715 reg = <0 0x11f10000 0 0x1000>; 716 }; 717 718 u3phy: usb-phy@11f40000 { 719 compatible = "mediatek,mt8183-tphy", 720 "mediatek,generic-tphy-v2"; 721 #address-cells = <1>; 722 #phy-cells = <1>; 723 #size-cells = <1>; 724 ranges = <0 0 0x11f40000 0x1000>; 725 status = "okay"; 726 727 u2port0: usb-phy@0 { 728 reg = <0x0 0x700>; 729 clocks = <&clk26m>; 730 clock-names = "ref"; 731 #phy-cells = <1>; 732 mediatek,discth = <15>; 733 status = "okay"; 734 }; 735 736 u3port0: usb-phy@0700 { 737 reg = <0x0700 0x900>; 738 clocks = <&clk26m>; 739 clock-names = "ref"; 740 #phy-cells = <1>; 741 status = "okay"; 742 }; 743 }; 744 745 mfgcfg: syscon@13000000 { 746 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 747 reg = <0 0x13000000 0 0x1000>; 748 #clock-cells = <1>; 749 }; 750 751 mmsys: syscon@14000000 { 752 compatible = "mediatek,mt8183-mmsys", "syscon"; 753 reg = <0 0x14000000 0 0x1000>; 754 #clock-cells = <1>; 755 }; 756 757 imgsys: syscon@15020000 { 758 compatible = "mediatek,mt8183-imgsys", "syscon"; 759 reg = <0 0x15020000 0 0x1000>; 760 #clock-cells = <1>; 761 }; 762 763 vdecsys: syscon@16000000 { 764 compatible = "mediatek,mt8183-vdecsys", "syscon"; 765 reg = <0 0x16000000 0 0x1000>; 766 #clock-cells = <1>; 767 }; 768 769 vencsys: syscon@17000000 { 770 compatible = "mediatek,mt8183-vencsys", "syscon"; 771 reg = <0 0x17000000 0 0x1000>; 772 #clock-cells = <1>; 773 }; 774 775 ipu_conn: syscon@19000000 { 776 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 777 reg = <0 0x19000000 0 0x1000>; 778 #clock-cells = <1>; 779 }; 780 781 ipu_adl: syscon@19010000 { 782 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 783 reg = <0 0x19010000 0 0x1000>; 784 #clock-cells = <1>; 785 }; 786 787 ipu_core0: syscon@19180000 { 788 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 789 reg = <0 0x19180000 0 0x1000>; 790 #clock-cells = <1>; 791 }; 792 793 ipu_core1: syscon@19280000 { 794 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 795 reg = <0 0x19280000 0 0x1000>; 796 #clock-cells = <1>; 797 }; 798 799 camsys: syscon@1a000000 { 800 compatible = "mediatek,mt8183-camsys", "syscon"; 801 reg = <0 0x1a000000 0 0x1000>; 802 #clock-cells = <1>; 803 }; 804 }; 805}; 806