1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/gce/mt8183-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8183-larb-port.h>
13#include <dt-bindings/power/mt8183-power.h>
14#include <dt-bindings/reset/mt8183-resets.h>
15#include <dt-bindings/phy/phy.h>
16#include <dt-bindings/thermal/thermal.h>
17#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
18
19/ {
20	compatible = "mediatek,mt8183";
21	interrupt-parent = <&sysirq>;
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	aliases {
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		i2c2 = &i2c2;
29		i2c3 = &i2c3;
30		i2c4 = &i2c4;
31		i2c5 = &i2c5;
32		i2c6 = &i2c6;
33		i2c7 = &i2c7;
34		i2c8 = &i2c8;
35		i2c9 = &i2c9;
36		i2c10 = &i2c10;
37		i2c11 = &i2c11;
38		ovl0 = &ovl0;
39		ovl-2l0 = &ovl_2l0;
40		ovl-2l1 = &ovl_2l1;
41		rdma0 = &rdma0;
42		rdma1 = &rdma1;
43	};
44
45	cluster0_opp: opp-table-cluster0 {
46		compatible = "operating-points-v2";
47		opp-shared;
48		opp0-793000000 {
49			opp-hz = /bits/ 64 <793000000>;
50			opp-microvolt = <650000>;
51			required-opps = <&opp2_00>;
52		};
53		opp0-910000000 {
54			opp-hz = /bits/ 64 <910000000>;
55			opp-microvolt = <687500>;
56			required-opps = <&opp2_01>;
57		};
58		opp0-1014000000 {
59			opp-hz = /bits/ 64 <1014000000>;
60			opp-microvolt = <718750>;
61			required-opps = <&opp2_02>;
62		};
63		opp0-1131000000 {
64			opp-hz = /bits/ 64 <1131000000>;
65			opp-microvolt = <756250>;
66			required-opps = <&opp2_03>;
67		};
68		opp0-1248000000 {
69			opp-hz = /bits/ 64 <1248000000>;
70			opp-microvolt = <800000>;
71			required-opps = <&opp2_04>;
72		};
73		opp0-1326000000 {
74			opp-hz = /bits/ 64 <1326000000>;
75			opp-microvolt = <818750>;
76			required-opps = <&opp2_05>;
77		};
78		opp0-1417000000 {
79			opp-hz = /bits/ 64 <1417000000>;
80			opp-microvolt = <850000>;
81			required-opps = <&opp2_06>;
82		};
83		opp0-1508000000 {
84			opp-hz = /bits/ 64 <1508000000>;
85			opp-microvolt = <868750>;
86			required-opps = <&opp2_07>;
87		};
88		opp0-1586000000 {
89			opp-hz = /bits/ 64 <1586000000>;
90			opp-microvolt = <893750>;
91			required-opps = <&opp2_08>;
92		};
93		opp0-1625000000 {
94			opp-hz = /bits/ 64 <1625000000>;
95			opp-microvolt = <906250>;
96			required-opps = <&opp2_09>;
97		};
98		opp0-1677000000 {
99			opp-hz = /bits/ 64 <1677000000>;
100			opp-microvolt = <931250>;
101			required-opps = <&opp2_10>;
102		};
103		opp0-1716000000 {
104			opp-hz = /bits/ 64 <1716000000>;
105			opp-microvolt = <943750>;
106			required-opps = <&opp2_11>;
107		};
108		opp0-1781000000 {
109			opp-hz = /bits/ 64 <1781000000>;
110			opp-microvolt = <975000>;
111			required-opps = <&opp2_12>;
112		};
113		opp0-1846000000 {
114			opp-hz = /bits/ 64 <1846000000>;
115			opp-microvolt = <1000000>;
116			required-opps = <&opp2_13>;
117		};
118		opp0-1924000000 {
119			opp-hz = /bits/ 64 <1924000000>;
120			opp-microvolt = <1025000>;
121			required-opps = <&opp2_14>;
122		};
123		opp0-1989000000 {
124			opp-hz = /bits/ 64 <1989000000>;
125			opp-microvolt = <1050000>;
126			required-opps = <&opp2_15>;
127		};	};
128
129	cluster1_opp: opp-table-cluster1 {
130		compatible = "operating-points-v2";
131		opp-shared;
132		opp1-793000000 {
133			opp-hz = /bits/ 64 <793000000>;
134			opp-microvolt = <700000>;
135			required-opps = <&opp2_00>;
136		};
137		opp1-910000000 {
138			opp-hz = /bits/ 64 <910000000>;
139			opp-microvolt = <725000>;
140			required-opps = <&opp2_01>;
141		};
142		opp1-1014000000 {
143			opp-hz = /bits/ 64 <1014000000>;
144			opp-microvolt = <750000>;
145			required-opps = <&opp2_02>;
146		};
147		opp1-1131000000 {
148			opp-hz = /bits/ 64 <1131000000>;
149			opp-microvolt = <775000>;
150			required-opps = <&opp2_03>;
151		};
152		opp1-1248000000 {
153			opp-hz = /bits/ 64 <1248000000>;
154			opp-microvolt = <800000>;
155			required-opps = <&opp2_04>;
156		};
157		opp1-1326000000 {
158			opp-hz = /bits/ 64 <1326000000>;
159			opp-microvolt = <825000>;
160			required-opps = <&opp2_05>;
161		};
162		opp1-1417000000 {
163			opp-hz = /bits/ 64 <1417000000>;
164			opp-microvolt = <850000>;
165			required-opps = <&opp2_06>;
166		};
167		opp1-1508000000 {
168			opp-hz = /bits/ 64 <1508000000>;
169			opp-microvolt = <875000>;
170			required-opps = <&opp2_07>;
171		};
172		opp1-1586000000 {
173			opp-hz = /bits/ 64 <1586000000>;
174			opp-microvolt = <900000>;
175			required-opps = <&opp2_08>;
176		};
177		opp1-1625000000 {
178			opp-hz = /bits/ 64 <1625000000>;
179			opp-microvolt = <912500>;
180			required-opps = <&opp2_09>;
181		};
182		opp1-1677000000 {
183			opp-hz = /bits/ 64 <1677000000>;
184			opp-microvolt = <931250>;
185			required-opps = <&opp2_10>;
186		};
187		opp1-1716000000 {
188			opp-hz = /bits/ 64 <1716000000>;
189			opp-microvolt = <950000>;
190			required-opps = <&opp2_11>;
191		};
192		opp1-1781000000 {
193			opp-hz = /bits/ 64 <1781000000>;
194			opp-microvolt = <975000>;
195			required-opps = <&opp2_12>;
196		};
197		opp1-1846000000 {
198			opp-hz = /bits/ 64 <1846000000>;
199			opp-microvolt = <1000000>;
200			required-opps = <&opp2_13>;
201		};
202		opp1-1924000000 {
203			opp-hz = /bits/ 64 <1924000000>;
204			opp-microvolt = <1025000>;
205			required-opps = <&opp2_14>;
206		};
207		opp1-1989000000 {
208			opp-hz = /bits/ 64 <1989000000>;
209			opp-microvolt = <1050000>;
210			required-opps = <&opp2_15>;
211		};
212	};
213
214	cci_opp: opp-table-cci {
215		compatible = "operating-points-v2";
216		opp-shared;
217		opp2_00: opp-273000000 {
218			opp-hz = /bits/ 64 <273000000>;
219			opp-microvolt = <650000>;
220		};
221		opp2_01: opp-338000000 {
222			opp-hz = /bits/ 64 <338000000>;
223			opp-microvolt = <687500>;
224		};
225		opp2_02: opp-403000000 {
226			opp-hz = /bits/ 64 <403000000>;
227			opp-microvolt = <718750>;
228		};
229		opp2_03: opp-463000000 {
230			opp-hz = /bits/ 64 <463000000>;
231			opp-microvolt = <756250>;
232		};
233		opp2_04: opp-546000000 {
234			opp-hz = /bits/ 64 <546000000>;
235			opp-microvolt = <800000>;
236		};
237		opp2_05: opp-624000000 {
238			opp-hz = /bits/ 64 <624000000>;
239			opp-microvolt = <818750>;
240		};
241		opp2_06: opp-689000000 {
242			opp-hz = /bits/ 64 <689000000>;
243			opp-microvolt = <850000>;
244		};
245		opp2_07: opp-767000000 {
246			opp-hz = /bits/ 64 <767000000>;
247			opp-microvolt = <868750>;
248		};
249		opp2_08: opp-845000000 {
250			opp-hz = /bits/ 64 <845000000>;
251			opp-microvolt = <893750>;
252		};
253		opp2_09: opp-871000000 {
254			opp-hz = /bits/ 64 <871000000>;
255			opp-microvolt = <906250>;
256		};
257		opp2_10: opp-923000000 {
258			opp-hz = /bits/ 64 <923000000>;
259			opp-microvolt = <931250>;
260		};
261		opp2_11: opp-962000000 {
262			opp-hz = /bits/ 64 <962000000>;
263			opp-microvolt = <943750>;
264		};
265		opp2_12: opp-1027000000 {
266			opp-hz = /bits/ 64 <1027000000>;
267			opp-microvolt = <975000>;
268		};
269		opp2_13: opp-1092000000 {
270			opp-hz = /bits/ 64 <1092000000>;
271			opp-microvolt = <1000000>;
272		};
273		opp2_14: opp-1144000000 {
274			opp-hz = /bits/ 64 <1144000000>;
275			opp-microvolt = <1025000>;
276		};
277		opp2_15: opp-1196000000 {
278			opp-hz = /bits/ 64 <1196000000>;
279			opp-microvolt = <1050000>;
280		};
281	};
282
283	cci: cci {
284		compatible = "mediatek,mt8183-cci";
285		clocks = <&mcucfg CLK_MCU_BUS_SEL>,
286			 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
287		clock-names = "cci", "intermediate";
288		operating-points-v2 = <&cci_opp>;
289	};
290
291	cpus {
292		#address-cells = <1>;
293		#size-cells = <0>;
294
295		cpu-map {
296			cluster0 {
297				core0 {
298					cpu = <&cpu0>;
299				};
300				core1 {
301					cpu = <&cpu1>;
302				};
303				core2 {
304					cpu = <&cpu2>;
305				};
306				core3 {
307					cpu = <&cpu3>;
308				};
309			};
310
311			cluster1 {
312				core0 {
313					cpu = <&cpu4>;
314				};
315				core1 {
316					cpu = <&cpu5>;
317				};
318				core2 {
319					cpu = <&cpu6>;
320				};
321				core3 {
322					cpu = <&cpu7>;
323				};
324			};
325		};
326
327		cpu0: cpu@0 {
328			device_type = "cpu";
329			compatible = "arm,cortex-a53";
330			reg = <0x000>;
331			enable-method = "psci";
332			capacity-dmips-mhz = <741>;
333			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
334			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
335				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
336			clock-names = "cpu", "intermediate";
337			operating-points-v2 = <&cluster0_opp>;
338			dynamic-power-coefficient = <84>;
339			i-cache-size = <32768>;
340			i-cache-line-size = <64>;
341			i-cache-sets = <256>;
342			d-cache-size = <32768>;
343			d-cache-line-size = <64>;
344			d-cache-sets = <128>;
345			next-level-cache = <&l2_0>;
346			#cooling-cells = <2>;
347			mediatek,cci = <&cci>;
348		};
349
350		cpu1: cpu@1 {
351			device_type = "cpu";
352			compatible = "arm,cortex-a53";
353			reg = <0x001>;
354			enable-method = "psci";
355			capacity-dmips-mhz = <741>;
356			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
357			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
358				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
359			clock-names = "cpu", "intermediate";
360			operating-points-v2 = <&cluster0_opp>;
361			dynamic-power-coefficient = <84>;
362			i-cache-size = <32768>;
363			i-cache-line-size = <64>;
364			i-cache-sets = <256>;
365			d-cache-size = <32768>;
366			d-cache-line-size = <64>;
367			d-cache-sets = <128>;
368			next-level-cache = <&l2_0>;
369			#cooling-cells = <2>;
370			mediatek,cci = <&cci>;
371		};
372
373		cpu2: cpu@2 {
374			device_type = "cpu";
375			compatible = "arm,cortex-a53";
376			reg = <0x002>;
377			enable-method = "psci";
378			capacity-dmips-mhz = <741>;
379			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
380			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
381				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
382			clock-names = "cpu", "intermediate";
383			operating-points-v2 = <&cluster0_opp>;
384			dynamic-power-coefficient = <84>;
385			i-cache-size = <32768>;
386			i-cache-line-size = <64>;
387			i-cache-sets = <256>;
388			d-cache-size = <32768>;
389			d-cache-line-size = <64>;
390			d-cache-sets = <128>;
391			next-level-cache = <&l2_0>;
392			#cooling-cells = <2>;
393			mediatek,cci = <&cci>;
394		};
395
396		cpu3: cpu@3 {
397			device_type = "cpu";
398			compatible = "arm,cortex-a53";
399			reg = <0x003>;
400			enable-method = "psci";
401			capacity-dmips-mhz = <741>;
402			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
403			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
404				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
405			clock-names = "cpu", "intermediate";
406			operating-points-v2 = <&cluster0_opp>;
407			dynamic-power-coefficient = <84>;
408			i-cache-size = <32768>;
409			i-cache-line-size = <64>;
410			i-cache-sets = <256>;
411			d-cache-size = <32768>;
412			d-cache-line-size = <64>;
413			d-cache-sets = <128>;
414			next-level-cache = <&l2_0>;
415			#cooling-cells = <2>;
416			mediatek,cci = <&cci>;
417		};
418
419		cpu4: cpu@100 {
420			device_type = "cpu";
421			compatible = "arm,cortex-a73";
422			reg = <0x100>;
423			enable-method = "psci";
424			capacity-dmips-mhz = <1024>;
425			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
426			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
427				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
428			clock-names = "cpu", "intermediate";
429			operating-points-v2 = <&cluster1_opp>;
430			dynamic-power-coefficient = <211>;
431			i-cache-size = <65536>;
432			i-cache-line-size = <64>;
433			i-cache-sets = <256>;
434			d-cache-size = <65536>;
435			d-cache-line-size = <64>;
436			d-cache-sets = <256>;
437			next-level-cache = <&l2_1>;
438			#cooling-cells = <2>;
439			mediatek,cci = <&cci>;
440		};
441
442		cpu5: cpu@101 {
443			device_type = "cpu";
444			compatible = "arm,cortex-a73";
445			reg = <0x101>;
446			enable-method = "psci";
447			capacity-dmips-mhz = <1024>;
448			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
449			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
450				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
451			clock-names = "cpu", "intermediate";
452			operating-points-v2 = <&cluster1_opp>;
453			dynamic-power-coefficient = <211>;
454			i-cache-size = <65536>;
455			i-cache-line-size = <64>;
456			i-cache-sets = <256>;
457			d-cache-size = <65536>;
458			d-cache-line-size = <64>;
459			d-cache-sets = <256>;
460			next-level-cache = <&l2_1>;
461			#cooling-cells = <2>;
462			mediatek,cci = <&cci>;
463		};
464
465		cpu6: cpu@102 {
466			device_type = "cpu";
467			compatible = "arm,cortex-a73";
468			reg = <0x102>;
469			enable-method = "psci";
470			capacity-dmips-mhz = <1024>;
471			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
472			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
473				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
474			clock-names = "cpu", "intermediate";
475			operating-points-v2 = <&cluster1_opp>;
476			dynamic-power-coefficient = <211>;
477			i-cache-size = <65536>;
478			i-cache-line-size = <64>;
479			i-cache-sets = <256>;
480			d-cache-size = <65536>;
481			d-cache-line-size = <64>;
482			d-cache-sets = <256>;
483			next-level-cache = <&l2_1>;
484			#cooling-cells = <2>;
485			mediatek,cci = <&cci>;
486		};
487
488		cpu7: cpu@103 {
489			device_type = "cpu";
490			compatible = "arm,cortex-a73";
491			reg = <0x103>;
492			enable-method = "psci";
493			capacity-dmips-mhz = <1024>;
494			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
495			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
496				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
497			clock-names = "cpu", "intermediate";
498			operating-points-v2 = <&cluster1_opp>;
499			dynamic-power-coefficient = <211>;
500			i-cache-size = <65536>;
501			i-cache-line-size = <64>;
502			i-cache-sets = <256>;
503			d-cache-size = <65536>;
504			d-cache-line-size = <64>;
505			d-cache-sets = <256>;
506			next-level-cache = <&l2_1>;
507			#cooling-cells = <2>;
508			mediatek,cci = <&cci>;
509		};
510
511		idle-states {
512			entry-method = "psci";
513
514			CPU_SLEEP: cpu-sleep {
515				compatible = "arm,idle-state";
516				local-timer-stop;
517				arm,psci-suspend-param = <0x00010001>;
518				entry-latency-us = <200>;
519				exit-latency-us = <200>;
520				min-residency-us = <800>;
521			};
522
523			CLUSTER_SLEEP0: cluster-sleep-0 {
524				compatible = "arm,idle-state";
525				local-timer-stop;
526				arm,psci-suspend-param = <0x01010001>;
527				entry-latency-us = <250>;
528				exit-latency-us = <400>;
529				min-residency-us = <1000>;
530			};
531			CLUSTER_SLEEP1: cluster-sleep-1 {
532				compatible = "arm,idle-state";
533				local-timer-stop;
534				arm,psci-suspend-param = <0x01010001>;
535				entry-latency-us = <250>;
536				exit-latency-us = <400>;
537				min-residency-us = <1300>;
538			};
539		};
540
541		l2_0: l2-cache0 {
542			compatible = "cache";
543			cache-level = <2>;
544			cache-size = <1048576>;
545			cache-line-size = <64>;
546			cache-sets = <1024>;
547			cache-unified;
548		};
549
550		l2_1: l2-cache1 {
551			compatible = "cache";
552			cache-level = <2>;
553			cache-size = <1048576>;
554			cache-line-size = <64>;
555			cache-sets = <1024>;
556			cache-unified;
557		};
558	};
559
560	gpu_opp_table: opp-table-0 {
561		compatible = "operating-points-v2";
562		opp-shared;
563
564		opp-300000000 {
565			opp-hz = /bits/ 64 <300000000>;
566			opp-microvolt = <625000>, <850000>;
567		};
568
569		opp-320000000 {
570			opp-hz = /bits/ 64 <320000000>;
571			opp-microvolt = <631250>, <850000>;
572		};
573
574		opp-340000000 {
575			opp-hz = /bits/ 64 <340000000>;
576			opp-microvolt = <637500>, <850000>;
577		};
578
579		opp-360000000 {
580			opp-hz = /bits/ 64 <360000000>;
581			opp-microvolt = <643750>, <850000>;
582		};
583
584		opp-380000000 {
585			opp-hz = /bits/ 64 <380000000>;
586			opp-microvolt = <650000>, <850000>;
587		};
588
589		opp-400000000 {
590			opp-hz = /bits/ 64 <400000000>;
591			opp-microvolt = <656250>, <850000>;
592		};
593
594		opp-420000000 {
595			opp-hz = /bits/ 64 <420000000>;
596			opp-microvolt = <662500>, <850000>;
597		};
598
599		opp-460000000 {
600			opp-hz = /bits/ 64 <460000000>;
601			opp-microvolt = <675000>, <850000>;
602		};
603
604		opp-500000000 {
605			opp-hz = /bits/ 64 <500000000>;
606			opp-microvolt = <687500>, <850000>;
607		};
608
609		opp-540000000 {
610			opp-hz = /bits/ 64 <540000000>;
611			opp-microvolt = <700000>, <850000>;
612		};
613
614		opp-580000000 {
615			opp-hz = /bits/ 64 <580000000>;
616			opp-microvolt = <712500>, <850000>;
617		};
618
619		opp-620000000 {
620			opp-hz = /bits/ 64 <620000000>;
621			opp-microvolt = <725000>, <850000>;
622		};
623
624		opp-653000000 {
625			opp-hz = /bits/ 64 <653000000>;
626			opp-microvolt = <743750>, <850000>;
627		};
628
629		opp-698000000 {
630			opp-hz = /bits/ 64 <698000000>;
631			opp-microvolt = <768750>, <868750>;
632		};
633
634		opp-743000000 {
635			opp-hz = /bits/ 64 <743000000>;
636			opp-microvolt = <793750>, <893750>;
637		};
638
639		opp-800000000 {
640			opp-hz = /bits/ 64 <800000000>;
641			opp-microvolt = <825000>, <925000>;
642		};
643	};
644
645	pmu-a53 {
646		compatible = "arm,cortex-a53-pmu";
647		interrupt-parent = <&gic>;
648		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
649	};
650
651	pmu-a73 {
652		compatible = "arm,cortex-a73-pmu";
653		interrupt-parent = <&gic>;
654		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
655	};
656
657	psci {
658		compatible = "arm,psci-1.0";
659		method = "smc";
660	};
661
662	clk13m: fixed-factor-clock-13m {
663		compatible = "fixed-factor-clock";
664		#clock-cells = <0>;
665		clocks = <&clk26m>;
666		clock-div = <2>;
667		clock-mult = <1>;
668		clock-output-names = "clk13m";
669	};
670
671	clk26m: oscillator {
672		compatible = "fixed-clock";
673		#clock-cells = <0>;
674		clock-frequency = <26000000>;
675		clock-output-names = "clk26m";
676	};
677
678	timer {
679		compatible = "arm,armv8-timer";
680		interrupt-parent = <&gic>;
681		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
682			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
683			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
684			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
685	};
686
687	soc {
688		#address-cells = <2>;
689		#size-cells = <2>;
690		compatible = "simple-bus";
691		ranges;
692
693		soc_data: efuse@8000000 {
694			compatible = "mediatek,mt8183-efuse",
695				     "mediatek,efuse";
696			reg = <0 0x08000000 0 0x0010>;
697			#address-cells = <1>;
698			#size-cells = <1>;
699			status = "disabled";
700		};
701
702		gic: interrupt-controller@c000000 {
703			compatible = "arm,gic-v3";
704			#interrupt-cells = <4>;
705			interrupt-parent = <&gic>;
706			interrupt-controller;
707			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
708			      <0 0x0c100000 0 0x200000>, /* GICR */
709			      <0 0x0c400000 0 0x2000>,   /* GICC */
710			      <0 0x0c410000 0 0x1000>,   /* GICH */
711			      <0 0x0c420000 0 0x2000>;   /* GICV */
712
713			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
714			ppi-partitions {
715				ppi_cluster0: interrupt-partition-0 {
716					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
717				};
718				ppi_cluster1: interrupt-partition-1 {
719					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
720				};
721			};
722		};
723
724		mcucfg: syscon@c530000 {
725			compatible = "mediatek,mt8183-mcucfg", "syscon";
726			reg = <0 0x0c530000 0 0x1000>;
727			#clock-cells = <1>;
728		};
729
730		sysirq: interrupt-controller@c530a80 {
731			compatible = "mediatek,mt8183-sysirq",
732				     "mediatek,mt6577-sysirq";
733			interrupt-controller;
734			#interrupt-cells = <3>;
735			interrupt-parent = <&gic>;
736			reg = <0 0x0c530a80 0 0x50>;
737		};
738
739		cpu_debug0: cpu-debug@d410000 {
740			compatible = "arm,coresight-cpu-debug", "arm,primecell";
741			reg = <0x0 0xd410000 0x0 0x1000>;
742			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
743			clock-names = "apb_pclk";
744			cpu = <&cpu0>;
745		};
746
747		cpu_debug1: cpu-debug@d510000 {
748			compatible = "arm,coresight-cpu-debug", "arm,primecell";
749			reg = <0x0 0xd510000 0x0 0x1000>;
750			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
751			clock-names = "apb_pclk";
752			cpu = <&cpu1>;
753		};
754
755		cpu_debug2: cpu-debug@d610000 {
756			compatible = "arm,coresight-cpu-debug", "arm,primecell";
757			reg = <0x0 0xd610000 0x0 0x1000>;
758			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
759			clock-names = "apb_pclk";
760			cpu = <&cpu2>;
761		};
762
763		cpu_debug3: cpu-debug@d710000 {
764			compatible = "arm,coresight-cpu-debug", "arm,primecell";
765			reg = <0x0 0xd710000 0x0 0x1000>;
766			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
767			clock-names = "apb_pclk";
768			cpu = <&cpu3>;
769		};
770
771		cpu_debug4: cpu-debug@d810000 {
772			compatible = "arm,coresight-cpu-debug", "arm,primecell";
773			reg = <0x0 0xd810000 0x0 0x1000>;
774			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
775			clock-names = "apb_pclk";
776			cpu = <&cpu4>;
777		};
778
779		cpu_debug5: cpu-debug@d910000 {
780			compatible = "arm,coresight-cpu-debug", "arm,primecell";
781			reg = <0x0 0xd910000 0x0 0x1000>;
782			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
783			clock-names = "apb_pclk";
784			cpu = <&cpu5>;
785		};
786
787		cpu_debug6: cpu-debug@da10000 {
788			compatible = "arm,coresight-cpu-debug", "arm,primecell";
789			reg = <0x0 0xda10000 0x0 0x1000>;
790			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
791			clock-names = "apb_pclk";
792			cpu = <&cpu6>;
793		};
794
795		cpu_debug7: cpu-debug@db10000 {
796			compatible = "arm,coresight-cpu-debug", "arm,primecell";
797			reg = <0x0 0xdb10000 0x0 0x1000>;
798			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
799			clock-names = "apb_pclk";
800			cpu = <&cpu7>;
801		};
802
803		topckgen: syscon@10000000 {
804			compatible = "mediatek,mt8183-topckgen", "syscon";
805			reg = <0 0x10000000 0 0x1000>;
806			#clock-cells = <1>;
807		};
808
809		infracfg: syscon@10001000 {
810			compatible = "mediatek,mt8183-infracfg", "syscon";
811			reg = <0 0x10001000 0 0x1000>;
812			#clock-cells = <1>;
813			#reset-cells = <1>;
814		};
815
816		pericfg: syscon@10003000 {
817			compatible = "mediatek,mt8183-pericfg", "syscon";
818			reg = <0 0x10003000 0 0x1000>;
819			#clock-cells = <1>;
820		};
821
822		pio: pinctrl@10005000 {
823			compatible = "mediatek,mt8183-pinctrl";
824			reg = <0 0x10005000 0 0x1000>,
825			      <0 0x11f20000 0 0x1000>,
826			      <0 0x11e80000 0 0x1000>,
827			      <0 0x11e70000 0 0x1000>,
828			      <0 0x11e90000 0 0x1000>,
829			      <0 0x11d30000 0 0x1000>,
830			      <0 0x11d20000 0 0x1000>,
831			      <0 0x11c50000 0 0x1000>,
832			      <0 0x11f30000 0 0x1000>,
833			      <0 0x1000b000 0 0x1000>;
834			reg-names = "iocfg0", "iocfg1", "iocfg2",
835				    "iocfg3", "iocfg4", "iocfg5",
836				    "iocfg6", "iocfg7", "iocfg8",
837				    "eint";
838			gpio-controller;
839			#gpio-cells = <2>;
840			gpio-ranges = <&pio 0 0 192>;
841			interrupt-controller;
842			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
843			#interrupt-cells = <2>;
844		};
845
846		scpsys: syscon@10006000 {
847			compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
848			reg = <0 0x10006000 0 0x1000>;
849
850			/* System Power Manager */
851			spm: power-controller {
852				compatible = "mediatek,mt8183-power-controller";
853				#address-cells = <1>;
854				#size-cells = <0>;
855				#power-domain-cells = <1>;
856
857				/* power domain of the SoC */
858				power-domain@MT8183_POWER_DOMAIN_AUDIO {
859					reg = <MT8183_POWER_DOMAIN_AUDIO>;
860					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
861						 <&infracfg CLK_INFRA_AUDIO>,
862						 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
863					clock-names = "audio", "audio1", "audio2";
864					#power-domain-cells = <0>;
865				};
866
867				power-domain@MT8183_POWER_DOMAIN_CONN {
868					reg = <MT8183_POWER_DOMAIN_CONN>;
869					mediatek,infracfg = <&infracfg>;
870					#power-domain-cells = <0>;
871				};
872
873				mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
874					reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
875					clocks = <&topckgen CLK_TOP_MUX_MFG>;
876					clock-names = "mfg";
877					#address-cells = <1>;
878					#size-cells = <0>;
879					#power-domain-cells = <1>;
880
881					mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
882						reg = <MT8183_POWER_DOMAIN_MFG>;
883						#address-cells = <1>;
884						#size-cells = <0>;
885						#power-domain-cells = <1>;
886
887						power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
888							reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
889							#power-domain-cells = <0>;
890						};
891
892						power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
893							reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
894							#power-domain-cells = <0>;
895						};
896
897						power-domain@MT8183_POWER_DOMAIN_MFG_2D {
898							reg = <MT8183_POWER_DOMAIN_MFG_2D>;
899							mediatek,infracfg = <&infracfg>;
900							#power-domain-cells = <0>;
901						};
902					};
903				};
904
905				power-domain@MT8183_POWER_DOMAIN_DISP {
906					reg = <MT8183_POWER_DOMAIN_DISP>;
907					clocks = <&topckgen CLK_TOP_MUX_MM>,
908						 <&mmsys CLK_MM_SMI_COMMON>,
909						 <&mmsys CLK_MM_SMI_LARB0>,
910						 <&mmsys CLK_MM_SMI_LARB1>,
911						 <&mmsys CLK_MM_GALS_COMM0>,
912						 <&mmsys CLK_MM_GALS_COMM1>,
913						 <&mmsys CLK_MM_GALS_CCU2MM>,
914						 <&mmsys CLK_MM_GALS_IPU12MM>,
915						 <&mmsys CLK_MM_GALS_IMG2MM>,
916						 <&mmsys CLK_MM_GALS_CAM2MM>,
917						 <&mmsys CLK_MM_GALS_IPU2MM>;
918					clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
919						      "mm-4", "mm-5", "mm-6", "mm-7",
920						      "mm-8", "mm-9";
921					mediatek,infracfg = <&infracfg>;
922					mediatek,smi = <&smi_common>;
923					#address-cells = <1>;
924					#size-cells = <0>;
925					#power-domain-cells = <1>;
926
927					power-domain@MT8183_POWER_DOMAIN_CAM {
928						reg = <MT8183_POWER_DOMAIN_CAM>;
929						clocks = <&topckgen CLK_TOP_MUX_CAM>,
930							 <&camsys CLK_CAM_LARB6>,
931							 <&camsys CLK_CAM_LARB3>,
932							 <&camsys CLK_CAM_SENINF>,
933							 <&camsys CLK_CAM_CAMSV0>,
934							 <&camsys CLK_CAM_CAMSV1>,
935							 <&camsys CLK_CAM_CAMSV2>,
936							 <&camsys CLK_CAM_CCU>;
937						clock-names = "cam", "cam-0", "cam-1",
938							      "cam-2", "cam-3", "cam-4",
939							      "cam-5", "cam-6";
940						mediatek,infracfg = <&infracfg>;
941						mediatek,smi = <&smi_common>;
942						#power-domain-cells = <0>;
943					};
944
945					power-domain@MT8183_POWER_DOMAIN_ISP {
946						reg = <MT8183_POWER_DOMAIN_ISP>;
947						clocks = <&topckgen CLK_TOP_MUX_IMG>,
948							 <&imgsys CLK_IMG_LARB5>,
949							 <&imgsys CLK_IMG_LARB2>;
950						clock-names = "isp", "isp-0", "isp-1";
951						mediatek,infracfg = <&infracfg>;
952						mediatek,smi = <&smi_common>;
953						#power-domain-cells = <0>;
954					};
955
956					power-domain@MT8183_POWER_DOMAIN_VDEC {
957						reg = <MT8183_POWER_DOMAIN_VDEC>;
958						mediatek,smi = <&smi_common>;
959						#power-domain-cells = <0>;
960					};
961
962					power-domain@MT8183_POWER_DOMAIN_VENC {
963						reg = <MT8183_POWER_DOMAIN_VENC>;
964						mediatek,smi = <&smi_common>;
965						#power-domain-cells = <0>;
966					};
967
968					power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
969						reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
970						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
971							 <&topckgen CLK_TOP_MUX_DSP>,
972							 <&ipu_conn CLK_IPU_CONN_IPU>,
973							 <&ipu_conn CLK_IPU_CONN_AHB>,
974							 <&ipu_conn CLK_IPU_CONN_AXI>,
975							 <&ipu_conn CLK_IPU_CONN_ISP>,
976							 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
977							 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
978						clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
979							      "vpu-2", "vpu-3", "vpu-4", "vpu-5";
980						mediatek,infracfg = <&infracfg>;
981						mediatek,smi = <&smi_common>;
982						#address-cells = <1>;
983						#size-cells = <0>;
984						#power-domain-cells = <1>;
985
986						power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
987							reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
988							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
989							clock-names = "vpu2";
990							mediatek,infracfg = <&infracfg>;
991							#power-domain-cells = <0>;
992						};
993
994						power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
995							reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
996							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
997							clock-names = "vpu3";
998							mediatek,infracfg = <&infracfg>;
999							#power-domain-cells = <0>;
1000						};
1001					};
1002				};
1003			};
1004		};
1005
1006		watchdog: watchdog@10007000 {
1007			compatible = "mediatek,mt8183-wdt";
1008			reg = <0 0x10007000 0 0x100>;
1009			#reset-cells = <1>;
1010		};
1011
1012		apmixedsys: syscon@1000c000 {
1013			compatible = "mediatek,mt8183-apmixedsys", "syscon";
1014			reg = <0 0x1000c000 0 0x1000>;
1015			#clock-cells = <1>;
1016		};
1017
1018		pwrap: pwrap@1000d000 {
1019			compatible = "mediatek,mt8183-pwrap";
1020			reg = <0 0x1000d000 0 0x1000>;
1021			reg-names = "pwrap";
1022			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1023			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
1024				 <&infracfg CLK_INFRA_PMIC_AP>;
1025			clock-names = "spi", "wrap";
1026		};
1027
1028		keyboard: keyboard@10010000 {
1029			compatible = "mediatek,mt6779-keypad";
1030			reg = <0 0x10010000 0 0x1000>;
1031			interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
1032			clocks = <&clk26m>;
1033			clock-names = "kpd";
1034			status = "disabled";
1035		};
1036
1037		scp: scp@10500000 {
1038			compatible = "mediatek,mt8183-scp";
1039			reg = <0 0x10500000 0 0x80000>,
1040			      <0 0x105c0000 0 0x19080>;
1041			reg-names = "sram", "cfg";
1042			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1043			clocks = <&infracfg CLK_INFRA_SCPSYS>;
1044			clock-names = "main";
1045			memory-region = <&scp_mem_reserved>;
1046			status = "disabled";
1047		};
1048
1049		systimer: timer@10017000 {
1050			compatible = "mediatek,mt8183-timer",
1051				     "mediatek,mt6765-timer";
1052			reg = <0 0x10017000 0 0x1000>;
1053			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1054			clocks = <&clk13m>;
1055		};
1056
1057		iommu: iommu@10205000 {
1058			compatible = "mediatek,mt8183-m4u";
1059			reg = <0 0x10205000 0 0x1000>;
1060			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
1061			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
1062					 <&larb4>, <&larb5>, <&larb6>;
1063			#iommu-cells = <1>;
1064		};
1065
1066		gce: mailbox@10238000 {
1067			compatible = "mediatek,mt8183-gce";
1068			reg = <0 0x10238000 0 0x4000>;
1069			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
1070			#mbox-cells = <2>;
1071			clocks = <&infracfg CLK_INFRA_GCE>;
1072			clock-names = "gce";
1073		};
1074
1075		auxadc: auxadc@11001000 {
1076			compatible = "mediatek,mt8183-auxadc",
1077				     "mediatek,mt8173-auxadc";
1078			reg = <0 0x11001000 0 0x1000>;
1079			clocks = <&infracfg CLK_INFRA_AUXADC>;
1080			clock-names = "main";
1081			#io-channel-cells = <1>;
1082			status = "disabled";
1083		};
1084
1085		uart0: serial@11002000 {
1086			compatible = "mediatek,mt8183-uart",
1087				     "mediatek,mt6577-uart";
1088			reg = <0 0x11002000 0 0x1000>;
1089			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
1090			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1091			clock-names = "baud", "bus";
1092			status = "disabled";
1093		};
1094
1095		uart1: serial@11003000 {
1096			compatible = "mediatek,mt8183-uart",
1097				     "mediatek,mt6577-uart";
1098			reg = <0 0x11003000 0 0x1000>;
1099			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
1100			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1101			clock-names = "baud", "bus";
1102			status = "disabled";
1103		};
1104
1105		uart2: serial@11004000 {
1106			compatible = "mediatek,mt8183-uart",
1107				     "mediatek,mt6577-uart";
1108			reg = <0 0x11004000 0 0x1000>;
1109			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
1110			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1111			clock-names = "baud", "bus";
1112			status = "disabled";
1113		};
1114
1115		i2c6: i2c@11005000 {
1116			compatible = "mediatek,mt8183-i2c";
1117			reg = <0 0x11005000 0 0x1000>,
1118			      <0 0x11000600 0 0x80>;
1119			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
1120			clocks = <&infracfg CLK_INFRA_I2C6>,
1121				 <&infracfg CLK_INFRA_AP_DMA>;
1122			clock-names = "main", "dma";
1123			clock-div = <1>;
1124			#address-cells = <1>;
1125			#size-cells = <0>;
1126			status = "disabled";
1127		};
1128
1129		i2c0: i2c@11007000 {
1130			compatible = "mediatek,mt8183-i2c";
1131			reg = <0 0x11007000 0 0x1000>,
1132			      <0 0x11000080 0 0x80>;
1133			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
1134			clocks = <&infracfg CLK_INFRA_I2C0>,
1135				 <&infracfg CLK_INFRA_AP_DMA>;
1136			clock-names = "main", "dma";
1137			clock-div = <1>;
1138			#address-cells = <1>;
1139			#size-cells = <0>;
1140			status = "disabled";
1141		};
1142
1143		i2c4: i2c@11008000 {
1144			compatible = "mediatek,mt8183-i2c";
1145			reg = <0 0x11008000 0 0x1000>,
1146			      <0 0x11000100 0 0x80>;
1147			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
1148			clocks = <&infracfg CLK_INFRA_I2C1>,
1149				 <&infracfg CLK_INFRA_AP_DMA>,
1150				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1151			clock-names = "main", "dma","arb";
1152			clock-div = <1>;
1153			#address-cells = <1>;
1154			#size-cells = <0>;
1155			status = "disabled";
1156		};
1157
1158		i2c2: i2c@11009000 {
1159			compatible = "mediatek,mt8183-i2c";
1160			reg = <0 0x11009000 0 0x1000>,
1161			      <0 0x11000280 0 0x80>;
1162			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
1163			clocks = <&infracfg CLK_INFRA_I2C2>,
1164				 <&infracfg CLK_INFRA_AP_DMA>,
1165				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1166			clock-names = "main", "dma", "arb";
1167			clock-div = <1>;
1168			#address-cells = <1>;
1169			#size-cells = <0>;
1170			status = "disabled";
1171		};
1172
1173		spi0: spi@1100a000 {
1174			compatible = "mediatek,mt8183-spi";
1175			#address-cells = <1>;
1176			#size-cells = <0>;
1177			reg = <0 0x1100a000 0 0x1000>;
1178			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
1179			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1180				 <&topckgen CLK_TOP_MUX_SPI>,
1181				 <&infracfg CLK_INFRA_SPI0>;
1182			clock-names = "parent-clk", "sel-clk", "spi-clk";
1183			status = "disabled";
1184		};
1185
1186		svs: svs@1100b000 {
1187			compatible = "mediatek,mt8183-svs";
1188			reg = <0 0x1100b000 0 0x1000>;
1189			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
1190			clocks = <&infracfg CLK_INFRA_THERM>;
1191			clock-names = "main";
1192			nvmem-cells = <&svs_calibration>,
1193				      <&thermal_calibration>;
1194			nvmem-cell-names = "svs-calibration-data",
1195					   "t-calibration-data";
1196		};
1197
1198		thermal: thermal@1100b000 {
1199			#thermal-sensor-cells = <1>;
1200			compatible = "mediatek,mt8183-thermal";
1201			reg = <0 0x1100b000 0 0x1000>;
1202			clocks = <&infracfg CLK_INFRA_THERM>,
1203				 <&infracfg CLK_INFRA_AUXADC>;
1204			clock-names = "therm", "auxadc";
1205			resets = <&infracfg  MT8183_INFRACFG_AO_THERM_SW_RST>;
1206			interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
1207			mediatek,auxadc = <&auxadc>;
1208			mediatek,apmixedsys = <&apmixedsys>;
1209			nvmem-cells = <&thermal_calibration>;
1210			nvmem-cell-names = "calibration-data";
1211		};
1212
1213		thermal_zones: thermal-zones {
1214			cpu_thermal: cpu-thermal {
1215				polling-delay-passive = <100>;
1216				polling-delay = <500>;
1217				thermal-sensors = <&thermal 0>;
1218				sustainable-power = <5000>;
1219
1220				trips {
1221					threshold: trip-point0 {
1222						temperature = <68000>;
1223						hysteresis = <2000>;
1224						type = "passive";
1225					};
1226
1227					target: trip-point1 {
1228						temperature = <80000>;
1229						hysteresis = <2000>;
1230						type = "passive";
1231					};
1232
1233					cpu_crit: cpu-crit {
1234						temperature = <115000>;
1235						hysteresis = <2000>;
1236						type = "critical";
1237					};
1238				};
1239
1240				cooling-maps {
1241					map0 {
1242						trip = <&target>;
1243						cooling-device = <&cpu0
1244							THERMAL_NO_LIMIT
1245							THERMAL_NO_LIMIT>,
1246								 <&cpu1
1247							THERMAL_NO_LIMIT
1248							THERMAL_NO_LIMIT>,
1249								 <&cpu2
1250							THERMAL_NO_LIMIT
1251							THERMAL_NO_LIMIT>,
1252								 <&cpu3
1253							THERMAL_NO_LIMIT
1254							THERMAL_NO_LIMIT>;
1255						contribution = <3072>;
1256					};
1257					map1 {
1258						trip = <&target>;
1259						cooling-device = <&cpu4
1260							THERMAL_NO_LIMIT
1261							THERMAL_NO_LIMIT>,
1262								 <&cpu5
1263							THERMAL_NO_LIMIT
1264							THERMAL_NO_LIMIT>,
1265								 <&cpu6
1266							THERMAL_NO_LIMIT
1267							THERMAL_NO_LIMIT>,
1268								 <&cpu7
1269							THERMAL_NO_LIMIT
1270							THERMAL_NO_LIMIT>;
1271						contribution = <1024>;
1272					};
1273				};
1274			};
1275
1276			/* The tzts1 ~ tzts6 don't need to polling */
1277			/* The tzts1 ~ tzts6 don't need to thermal throttle */
1278
1279			tzts1: tzts1 {
1280				polling-delay-passive = <0>;
1281				polling-delay = <0>;
1282				thermal-sensors = <&thermal 1>;
1283				sustainable-power = <5000>;
1284				trips {};
1285				cooling-maps {};
1286			};
1287
1288			tzts2: tzts2 {
1289				polling-delay-passive = <0>;
1290				polling-delay = <0>;
1291				thermal-sensors = <&thermal 2>;
1292				sustainable-power = <5000>;
1293				trips {};
1294				cooling-maps {};
1295			};
1296
1297			tzts3: tzts3 {
1298				polling-delay-passive = <0>;
1299				polling-delay = <0>;
1300				thermal-sensors = <&thermal 3>;
1301				sustainable-power = <5000>;
1302				trips {};
1303				cooling-maps {};
1304			};
1305
1306			tzts4: tzts4 {
1307				polling-delay-passive = <0>;
1308				polling-delay = <0>;
1309				thermal-sensors = <&thermal 4>;
1310				sustainable-power = <5000>;
1311				trips {};
1312				cooling-maps {};
1313			};
1314
1315			tzts5: tzts5 {
1316				polling-delay-passive = <0>;
1317				polling-delay = <0>;
1318				thermal-sensors = <&thermal 5>;
1319				sustainable-power = <5000>;
1320				trips {};
1321				cooling-maps {};
1322			};
1323
1324			tztsABB: tztsABB {
1325				polling-delay-passive = <0>;
1326				polling-delay = <0>;
1327				thermal-sensors = <&thermal 6>;
1328				sustainable-power = <5000>;
1329				trips {};
1330				cooling-maps {};
1331			};
1332		};
1333
1334		pwm0: pwm@1100e000 {
1335			compatible = "mediatek,mt8183-disp-pwm";
1336			reg = <0 0x1100e000 0 0x1000>;
1337			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
1338			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1339			#pwm-cells = <2>;
1340			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
1341					<&infracfg CLK_INFRA_DISP_PWM>;
1342			clock-names = "main", "mm";
1343		};
1344
1345		pwm1: pwm@11006000 {
1346			compatible = "mediatek,mt8183-pwm";
1347			reg = <0 0x11006000 0 0x1000>;
1348			#pwm-cells = <2>;
1349			clocks = <&infracfg CLK_INFRA_PWM>,
1350				 <&infracfg CLK_INFRA_PWM_HCLK>,
1351				 <&infracfg CLK_INFRA_PWM1>,
1352				 <&infracfg CLK_INFRA_PWM2>,
1353				 <&infracfg CLK_INFRA_PWM3>,
1354				 <&infracfg CLK_INFRA_PWM4>;
1355			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
1356				      "pwm4";
1357		};
1358
1359		i2c3: i2c@1100f000 {
1360			compatible = "mediatek,mt8183-i2c";
1361			reg = <0 0x1100f000 0 0x1000>,
1362			      <0 0x11000400 0 0x80>;
1363			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
1364			clocks = <&infracfg CLK_INFRA_I2C3>,
1365				 <&infracfg CLK_INFRA_AP_DMA>;
1366			clock-names = "main", "dma";
1367			clock-div = <1>;
1368			#address-cells = <1>;
1369			#size-cells = <0>;
1370			status = "disabled";
1371		};
1372
1373		spi1: spi@11010000 {
1374			compatible = "mediatek,mt8183-spi";
1375			#address-cells = <1>;
1376			#size-cells = <0>;
1377			reg = <0 0x11010000 0 0x1000>;
1378			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
1379			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1380				 <&topckgen CLK_TOP_MUX_SPI>,
1381				 <&infracfg CLK_INFRA_SPI1>;
1382			clock-names = "parent-clk", "sel-clk", "spi-clk";
1383			status = "disabled";
1384		};
1385
1386		i2c1: i2c@11011000 {
1387			compatible = "mediatek,mt8183-i2c";
1388			reg = <0 0x11011000 0 0x1000>,
1389			      <0 0x11000480 0 0x80>;
1390			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
1391			clocks = <&infracfg CLK_INFRA_I2C4>,
1392				 <&infracfg CLK_INFRA_AP_DMA>;
1393			clock-names = "main", "dma";
1394			clock-div = <1>;
1395			#address-cells = <1>;
1396			#size-cells = <0>;
1397			status = "disabled";
1398		};
1399
1400		spi2: spi@11012000 {
1401			compatible = "mediatek,mt8183-spi";
1402			#address-cells = <1>;
1403			#size-cells = <0>;
1404			reg = <0 0x11012000 0 0x1000>;
1405			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
1406			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1407				 <&topckgen CLK_TOP_MUX_SPI>,
1408				 <&infracfg CLK_INFRA_SPI2>;
1409			clock-names = "parent-clk", "sel-clk", "spi-clk";
1410			status = "disabled";
1411		};
1412
1413		spi3: spi@11013000 {
1414			compatible = "mediatek,mt8183-spi";
1415			#address-cells = <1>;
1416			#size-cells = <0>;
1417			reg = <0 0x11013000 0 0x1000>;
1418			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
1419			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1420				 <&topckgen CLK_TOP_MUX_SPI>,
1421				 <&infracfg CLK_INFRA_SPI3>;
1422			clock-names = "parent-clk", "sel-clk", "spi-clk";
1423			status = "disabled";
1424		};
1425
1426		i2c9: i2c@11014000 {
1427			compatible = "mediatek,mt8183-i2c";
1428			reg = <0 0x11014000 0 0x1000>,
1429			      <0 0x11000180 0 0x80>;
1430			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
1431			clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1432				 <&infracfg CLK_INFRA_AP_DMA>,
1433				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1434			clock-names = "main", "dma", "arb";
1435			clock-div = <1>;
1436			#address-cells = <1>;
1437			#size-cells = <0>;
1438			status = "disabled";
1439		};
1440
1441		i2c10: i2c@11015000 {
1442			compatible = "mediatek,mt8183-i2c";
1443			reg = <0 0x11015000 0 0x1000>,
1444			      <0 0x11000300 0 0x80>;
1445			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
1446			clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1447				 <&infracfg CLK_INFRA_AP_DMA>,
1448				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1449			clock-names = "main", "dma", "arb";
1450			clock-div = <1>;
1451			#address-cells = <1>;
1452			#size-cells = <0>;
1453			status = "disabled";
1454		};
1455
1456		i2c5: i2c@11016000 {
1457			compatible = "mediatek,mt8183-i2c";
1458			reg = <0 0x11016000 0 0x1000>,
1459			      <0 0x11000500 0 0x80>;
1460			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
1461			clocks = <&infracfg CLK_INFRA_I2C5>,
1462				 <&infracfg CLK_INFRA_AP_DMA>,
1463				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1464			clock-names = "main", "dma", "arb";
1465			clock-div = <1>;
1466			#address-cells = <1>;
1467			#size-cells = <0>;
1468			status = "disabled";
1469		};
1470
1471		i2c11: i2c@11017000 {
1472			compatible = "mediatek,mt8183-i2c";
1473			reg = <0 0x11017000 0 0x1000>,
1474			      <0 0x11000580 0 0x80>;
1475			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
1476			clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1477				 <&infracfg CLK_INFRA_AP_DMA>,
1478				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1479			clock-names = "main", "dma", "arb";
1480			clock-div = <1>;
1481			#address-cells = <1>;
1482			#size-cells = <0>;
1483			status = "disabled";
1484		};
1485
1486		spi4: spi@11018000 {
1487			compatible = "mediatek,mt8183-spi";
1488			#address-cells = <1>;
1489			#size-cells = <0>;
1490			reg = <0 0x11018000 0 0x1000>;
1491			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
1492			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1493				 <&topckgen CLK_TOP_MUX_SPI>,
1494				 <&infracfg CLK_INFRA_SPI4>;
1495			clock-names = "parent-clk", "sel-clk", "spi-clk";
1496			status = "disabled";
1497		};
1498
1499		spi5: spi@11019000 {
1500			compatible = "mediatek,mt8183-spi";
1501			#address-cells = <1>;
1502			#size-cells = <0>;
1503			reg = <0 0x11019000 0 0x1000>;
1504			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
1505			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1506				 <&topckgen CLK_TOP_MUX_SPI>,
1507				 <&infracfg CLK_INFRA_SPI5>;
1508			clock-names = "parent-clk", "sel-clk", "spi-clk";
1509			status = "disabled";
1510		};
1511
1512		i2c7: i2c@1101a000 {
1513			compatible = "mediatek,mt8183-i2c";
1514			reg = <0 0x1101a000 0 0x1000>,
1515			      <0 0x11000680 0 0x80>;
1516			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
1517			clocks = <&infracfg CLK_INFRA_I2C7>,
1518				 <&infracfg CLK_INFRA_AP_DMA>;
1519			clock-names = "main", "dma";
1520			clock-div = <1>;
1521			#address-cells = <1>;
1522			#size-cells = <0>;
1523			status = "disabled";
1524		};
1525
1526		i2c8: i2c@1101b000 {
1527			compatible = "mediatek,mt8183-i2c";
1528			reg = <0 0x1101b000 0 0x1000>,
1529			      <0 0x11000700 0 0x80>;
1530			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
1531			clocks = <&infracfg CLK_INFRA_I2C8>,
1532				 <&infracfg CLK_INFRA_AP_DMA>;
1533			clock-names = "main", "dma";
1534			clock-div = <1>;
1535			#address-cells = <1>;
1536			#size-cells = <0>;
1537			status = "disabled";
1538		};
1539
1540		ssusb: usb@11201000 {
1541			compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
1542			reg = <0 0x11201000 0 0x2e00>,
1543			      <0 0x11203e00 0 0x0100>;
1544			reg-names = "mac", "ippc";
1545			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
1546			phys = <&u2port0 PHY_TYPE_USB2>,
1547			       <&u3port0 PHY_TYPE_USB3>;
1548			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1549				 <&infracfg CLK_INFRA_USB>;
1550			clock-names = "sys_ck", "ref_ck";
1551			mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1552			#address-cells = <2>;
1553			#size-cells = <2>;
1554			ranges;
1555			status = "disabled";
1556
1557			usb_host: usb@11200000 {
1558				compatible = "mediatek,mt8183-xhci",
1559					     "mediatek,mtk-xhci";
1560				reg = <0 0x11200000 0 0x1000>;
1561				reg-names = "mac";
1562				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
1563				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1564					 <&infracfg CLK_INFRA_USB>;
1565				clock-names = "sys_ck", "ref_ck";
1566				status = "disabled";
1567			};
1568		};
1569
1570		audiosys: audio-controller@11220000 {
1571			compatible = "mediatek,mt8183-audiosys", "syscon";
1572			reg = <0 0x11220000 0 0x1000>;
1573			#clock-cells = <1>;
1574			afe: mt8183-afe-pcm {
1575				compatible = "mediatek,mt8183-audio";
1576				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
1577				resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
1578				reset-names = "audiosys";
1579				power-domains =
1580					<&spm MT8183_POWER_DOMAIN_AUDIO>;
1581				clocks = <&audiosys CLK_AUDIO_AFE>,
1582					 <&audiosys CLK_AUDIO_DAC>,
1583					 <&audiosys CLK_AUDIO_DAC_PREDIS>,
1584					 <&audiosys CLK_AUDIO_ADC>,
1585					 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
1586					 <&audiosys CLK_AUDIO_22M>,
1587					 <&audiosys CLK_AUDIO_24M>,
1588					 <&audiosys CLK_AUDIO_APLL_TUNER>,
1589					 <&audiosys CLK_AUDIO_APLL2_TUNER>,
1590					 <&audiosys CLK_AUDIO_I2S1>,
1591					 <&audiosys CLK_AUDIO_I2S2>,
1592					 <&audiosys CLK_AUDIO_I2S3>,
1593					 <&audiosys CLK_AUDIO_I2S4>,
1594					 <&audiosys CLK_AUDIO_TDM>,
1595					 <&audiosys CLK_AUDIO_TML>,
1596					 <&infracfg CLK_INFRA_AUDIO>,
1597					 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1598					 <&topckgen CLK_TOP_MUX_AUDIO>,
1599					 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1600					 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1601					 <&topckgen CLK_TOP_MUX_AUD_1>,
1602					 <&topckgen CLK_TOP_APLL1_CK>,
1603					 <&topckgen CLK_TOP_MUX_AUD_2>,
1604					 <&topckgen CLK_TOP_APLL2_CK>,
1605					 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1606					 <&topckgen CLK_TOP_APLL1_D8>,
1607					 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1608					 <&topckgen CLK_TOP_APLL2_D8>,
1609					 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1610					 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1611					 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1612					 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1613					 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1614					 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1615					 <&topckgen CLK_TOP_APLL12_DIV0>,
1616					 <&topckgen CLK_TOP_APLL12_DIV1>,
1617					 <&topckgen CLK_TOP_APLL12_DIV2>,
1618					 <&topckgen CLK_TOP_APLL12_DIV3>,
1619					 <&topckgen CLK_TOP_APLL12_DIV4>,
1620					 <&topckgen CLK_TOP_APLL12_DIVB>,
1621					 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1622					 <&clk26m>;
1623				clock-names = "aud_afe_clk",
1624						  "aud_dac_clk",
1625						  "aud_dac_predis_clk",
1626						  "aud_adc_clk",
1627						  "aud_adc_adda6_clk",
1628						  "aud_apll22m_clk",
1629						  "aud_apll24m_clk",
1630						  "aud_apll1_tuner_clk",
1631						  "aud_apll2_tuner_clk",
1632						  "aud_i2s1_bclk_sw",
1633						  "aud_i2s2_bclk_sw",
1634						  "aud_i2s3_bclk_sw",
1635						  "aud_i2s4_bclk_sw",
1636						  "aud_tdm_clk",
1637						  "aud_tml_clk",
1638						  "aud_infra_clk",
1639						  "mtkaif_26m_clk",
1640						  "top_mux_audio",
1641						  "top_mux_aud_intbus",
1642						  "top_syspll_d2_d4",
1643						  "top_mux_aud_1",
1644						  "top_apll1_ck",
1645						  "top_mux_aud_2",
1646						  "top_apll2_ck",
1647						  "top_mux_aud_eng1",
1648						  "top_apll1_d8",
1649						  "top_mux_aud_eng2",
1650						  "top_apll2_d8",
1651						  "top_i2s0_m_sel",
1652						  "top_i2s1_m_sel",
1653						  "top_i2s2_m_sel",
1654						  "top_i2s3_m_sel",
1655						  "top_i2s4_m_sel",
1656						  "top_i2s5_m_sel",
1657						  "top_apll12_div0",
1658						  "top_apll12_div1",
1659						  "top_apll12_div2",
1660						  "top_apll12_div3",
1661						  "top_apll12_div4",
1662						  "top_apll12_divb",
1663						  /*"top_apll12_div5",*/
1664						  "top_clk26m_clk";
1665			};
1666		};
1667
1668		mmc0: mmc@11230000 {
1669			compatible = "mediatek,mt8183-mmc";
1670			reg = <0 0x11230000 0 0x1000>,
1671			      <0 0x11f50000 0 0x1000>;
1672			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
1673			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1674				 <&infracfg CLK_INFRA_MSDC0>,
1675				 <&infracfg CLK_INFRA_MSDC0_SCK>;
1676			clock-names = "source", "hclk", "source_cg";
1677			status = "disabled";
1678		};
1679
1680		mmc1: mmc@11240000 {
1681			compatible = "mediatek,mt8183-mmc";
1682			reg = <0 0x11240000 0 0x1000>,
1683			      <0 0x11e10000 0 0x1000>;
1684			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
1685			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1686				 <&infracfg CLK_INFRA_MSDC1>,
1687				 <&infracfg CLK_INFRA_MSDC1_SCK>;
1688			clock-names = "source", "hclk", "source_cg";
1689			status = "disabled";
1690		};
1691
1692		mipi_tx0: dsi-phy@11e50000 {
1693			compatible = "mediatek,mt8183-mipi-tx";
1694			reg = <0 0x11e50000 0 0x1000>;
1695			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
1696			#clock-cells = <0>;
1697			#phy-cells = <0>;
1698			clock-output-names = "mipi_tx0_pll";
1699			nvmem-cells = <&mipi_tx_calibration>;
1700			nvmem-cell-names = "calibration-data";
1701		};
1702
1703		efuse: efuse@11f10000 {
1704			compatible = "mediatek,mt8183-efuse",
1705				     "mediatek,efuse";
1706			reg = <0 0x11f10000 0 0x1000>;
1707			#address-cells = <1>;
1708			#size-cells = <1>;
1709			thermal_calibration: calib@180 {
1710				reg = <0x180 0xc>;
1711			};
1712
1713			mipi_tx_calibration: calib@190 {
1714				reg = <0x190 0xc>;
1715			};
1716
1717			svs_calibration: calib@580 {
1718				reg = <0x580 0x64>;
1719			};
1720		};
1721
1722		u3phy: t-phy@11f40000 {
1723			compatible = "mediatek,mt8183-tphy",
1724				     "mediatek,generic-tphy-v2";
1725			#address-cells = <1>;
1726			#size-cells = <1>;
1727			ranges = <0 0 0x11f40000 0x1000>;
1728			status = "okay";
1729
1730			u2port0: usb-phy@0 {
1731				reg = <0x0 0x700>;
1732				clocks = <&clk26m>;
1733				clock-names = "ref";
1734				#phy-cells = <1>;
1735				mediatek,discth = <15>;
1736				status = "okay";
1737			};
1738
1739			u3port0: usb-phy@700 {
1740				reg = <0x0700 0x900>;
1741				clocks = <&clk26m>;
1742				clock-names = "ref";
1743				#phy-cells = <1>;
1744				status = "okay";
1745			};
1746		};
1747
1748		mfgcfg: syscon@13000000 {
1749			compatible = "mediatek,mt8183-mfgcfg", "syscon";
1750			reg = <0 0x13000000 0 0x1000>;
1751			#clock-cells = <1>;
1752		};
1753
1754		gpu: gpu@13040000 {
1755			compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
1756			reg = <0 0x13040000 0 0x4000>;
1757			interrupts =
1758				<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
1759				<GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
1760				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
1761			interrupt-names = "job", "mmu", "gpu";
1762
1763			clocks = <&mfgcfg CLK_MFG_BG3D>;
1764
1765			power-domains =
1766				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
1767				<&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
1768				<&spm MT8183_POWER_DOMAIN_MFG_2D>;
1769			power-domain-names = "core0", "core1", "core2";
1770
1771			operating-points-v2 = <&gpu_opp_table>;
1772		};
1773
1774		mmsys: syscon@14000000 {
1775			compatible = "mediatek,mt8183-mmsys", "syscon";
1776			reg = <0 0x14000000 0 0x1000>;
1777			#clock-cells = <1>;
1778			#reset-cells = <1>;
1779			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1780				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1781			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1782		};
1783
1784		mdp3-rdma0@14001000 {
1785			compatible = "mediatek,mt8183-mdp3-rdma";
1786			reg = <0 0x14001000 0 0x1000>;
1787			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1788			mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1789					      <CMDQ_EVENT_MDP_RDMA0_EOF>;
1790			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1791			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1792				 <&mmsys CLK_MM_MDP_RSZ1>;
1793			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1794			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
1795				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
1796		};
1797
1798		mdp3-rsz0@14003000 {
1799			compatible = "mediatek,mt8183-mdp3-rsz";
1800			reg = <0 0x14003000 0 0x1000>;
1801			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1802			mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
1803					      <CMDQ_EVENT_MDP_RSZ0_EOF>;
1804			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1805		};
1806
1807		mdp3-rsz1@14004000 {
1808			compatible = "mediatek,mt8183-mdp3-rsz";
1809			reg = <0 0x14004000 0 0x1000>;
1810			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1811			mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
1812					      <CMDQ_EVENT_MDP_RSZ1_EOF>;
1813			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1814		};
1815
1816		mdp3-wrot0@14005000 {
1817			compatible = "mediatek,mt8183-mdp3-wrot";
1818			reg = <0 0x14005000 0 0x1000>;
1819			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1820			mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
1821					      <CMDQ_EVENT_MDP_WROT0_EOF>;
1822			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1823			clocks = <&mmsys CLK_MM_MDP_WROT0>;
1824			iommus = <&iommu M4U_PORT_MDP_WROT0>;
1825		};
1826
1827		mdp3-wdma@14006000 {
1828			compatible = "mediatek,mt8183-mdp3-wdma";
1829			reg = <0 0x14006000 0 0x1000>;
1830			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1831			mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
1832					      <CMDQ_EVENT_MDP_WDMA0_EOF>;
1833			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1834			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
1835			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
1836		};
1837
1838		ovl0: ovl@14008000 {
1839			compatible = "mediatek,mt8183-disp-ovl";
1840			reg = <0 0x14008000 0 0x1000>;
1841			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
1842			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1843			clocks = <&mmsys CLK_MM_DISP_OVL0>;
1844			iommus = <&iommu M4U_PORT_DISP_OVL0>;
1845			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1846		};
1847
1848		ovl_2l0: ovl@14009000 {
1849			compatible = "mediatek,mt8183-disp-ovl-2l";
1850			reg = <0 0x14009000 0 0x1000>;
1851			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
1852			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1853			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1854			iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
1855			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1856		};
1857
1858		ovl_2l1: ovl@1400a000 {
1859			compatible = "mediatek,mt8183-disp-ovl-2l";
1860			reg = <0 0x1400a000 0 0x1000>;
1861			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
1862			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1863			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1864			iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
1865			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1866		};
1867
1868		rdma0: rdma@1400b000 {
1869			compatible = "mediatek,mt8183-disp-rdma";
1870			reg = <0 0x1400b000 0 0x1000>;
1871			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
1872			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1873			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1874			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1875			mediatek,rdma-fifo-size = <5120>;
1876			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1877		};
1878
1879		rdma1: rdma@1400c000 {
1880			compatible = "mediatek,mt8183-disp-rdma";
1881			reg = <0 0x1400c000 0 0x1000>;
1882			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
1883			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1884			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1885			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1886			mediatek,rdma-fifo-size = <2048>;
1887			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1888		};
1889
1890		color0: color@1400e000 {
1891			compatible = "mediatek,mt8183-disp-color",
1892				     "mediatek,mt8173-disp-color";
1893			reg = <0 0x1400e000 0 0x1000>;
1894			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
1895			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1896			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1897			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1898		};
1899
1900		ccorr0: ccorr@1400f000 {
1901			compatible = "mediatek,mt8183-disp-ccorr";
1902			reg = <0 0x1400f000 0 0x1000>;
1903			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
1904			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1905			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1906			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1907		};
1908
1909		aal0: aal@14010000 {
1910			compatible = "mediatek,mt8183-disp-aal";
1911			reg = <0 0x14010000 0 0x1000>;
1912			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
1913			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1914			clocks = <&mmsys CLK_MM_DISP_AAL0>;
1915			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1916		};
1917
1918		gamma0: gamma@14011000 {
1919			compatible = "mediatek,mt8183-disp-gamma";
1920			reg = <0 0x14011000 0 0x1000>;
1921			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
1922			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1923			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1924			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1925		};
1926
1927		dither0: dither@14012000 {
1928			compatible = "mediatek,mt8183-disp-dither";
1929			reg = <0 0x14012000 0 0x1000>;
1930			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
1931			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1932			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1933			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1934		};
1935
1936		dsi0: dsi@14014000 {
1937			compatible = "mediatek,mt8183-dsi";
1938			reg = <0 0x14014000 0 0x1000>;
1939			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
1940			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1941			clocks = <&mmsys CLK_MM_DSI0_MM>,
1942				 <&mmsys CLK_MM_DSI0_IF>,
1943				 <&mipi_tx0>;
1944			clock-names = "engine", "digital", "hs";
1945			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
1946			phys = <&mipi_tx0>;
1947			phy-names = "dphy";
1948		};
1949
1950		mutex: mutex@14016000 {
1951			compatible = "mediatek,mt8183-disp-mutex";
1952			reg = <0 0x14016000 0 0x1000>;
1953			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
1954			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1955			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1956					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
1957			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1958		};
1959
1960		larb0: larb@14017000 {
1961			compatible = "mediatek,mt8183-smi-larb";
1962			reg = <0 0x14017000 0 0x1000>;
1963			mediatek,smi = <&smi_common>;
1964			clocks = <&mmsys CLK_MM_SMI_LARB0>,
1965				 <&mmsys CLK_MM_SMI_LARB0>;
1966			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1967			clock-names = "apb", "smi";
1968		};
1969
1970		smi_common: smi@14019000 {
1971			compatible = "mediatek,mt8183-smi-common";
1972			reg = <0 0x14019000 0 0x1000>;
1973			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1974				 <&mmsys CLK_MM_SMI_COMMON>,
1975				 <&mmsys CLK_MM_GALS_COMM0>,
1976				 <&mmsys CLK_MM_GALS_COMM1>;
1977			clock-names = "apb", "smi", "gals0", "gals1";
1978			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1979		};
1980
1981		mdp3-ccorr@1401c000 {
1982			compatible = "mediatek,mt8183-mdp3-ccorr";
1983			reg = <0 0x1401c000 0 0x1000>;
1984			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1985			mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
1986					      <CMDQ_EVENT_MDP_CCORR_EOF>;
1987			clocks = <&mmsys CLK_MM_MDP_CCORR>;
1988		};
1989
1990		imgsys: syscon@15020000 {
1991			compatible = "mediatek,mt8183-imgsys", "syscon";
1992			reg = <0 0x15020000 0 0x1000>;
1993			#clock-cells = <1>;
1994		};
1995
1996		larb5: larb@15021000 {
1997			compatible = "mediatek,mt8183-smi-larb";
1998			reg = <0 0x15021000 0 0x1000>;
1999			mediatek,smi = <&smi_common>;
2000			clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
2001				 <&mmsys CLK_MM_GALS_IMG2MM>;
2002			clock-names = "apb", "smi", "gals";
2003			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
2004		};
2005
2006		larb2: larb@1502f000 {
2007			compatible = "mediatek,mt8183-smi-larb";
2008			reg = <0 0x1502f000 0 0x1000>;
2009			mediatek,smi = <&smi_common>;
2010			clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
2011				 <&mmsys CLK_MM_GALS_IPU2MM>;
2012			clock-names = "apb", "smi", "gals";
2013			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
2014		};
2015
2016		vdecsys: syscon@16000000 {
2017			compatible = "mediatek,mt8183-vdecsys", "syscon";
2018			reg = <0 0x16000000 0 0x1000>;
2019			#clock-cells = <1>;
2020		};
2021
2022		larb1: larb@16010000 {
2023			compatible = "mediatek,mt8183-smi-larb";
2024			reg = <0 0x16010000 0 0x1000>;
2025			mediatek,smi = <&smi_common>;
2026			clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
2027			clock-names = "apb", "smi";
2028			power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
2029		};
2030
2031		vencsys: syscon@17000000 {
2032			compatible = "mediatek,mt8183-vencsys", "syscon";
2033			reg = <0 0x17000000 0 0x1000>;
2034			#clock-cells = <1>;
2035		};
2036
2037		larb4: larb@17010000 {
2038			compatible = "mediatek,mt8183-smi-larb";
2039			reg = <0 0x17010000 0 0x1000>;
2040			mediatek,smi = <&smi_common>;
2041			clocks = <&vencsys CLK_VENC_LARB>,
2042				 <&vencsys CLK_VENC_LARB>;
2043			clock-names = "apb", "smi";
2044			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
2045		};
2046
2047		venc_jpg: venc_jpg@17030000 {
2048			compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
2049			reg = <0 0x17030000 0 0x1000>;
2050			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
2051			iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
2052				 <&iommu M4U_PORT_JPGENC_BSDMA>;
2053			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
2054			clocks = <&vencsys CLK_VENC_JPGENC>;
2055			clock-names = "jpgenc";
2056		};
2057
2058		ipu_conn: syscon@19000000 {
2059			compatible = "mediatek,mt8183-ipu_conn", "syscon";
2060			reg = <0 0x19000000 0 0x1000>;
2061			#clock-cells = <1>;
2062		};
2063
2064		ipu_adl: syscon@19010000 {
2065			compatible = "mediatek,mt8183-ipu_adl", "syscon";
2066			reg = <0 0x19010000 0 0x1000>;
2067			#clock-cells = <1>;
2068		};
2069
2070		ipu_core0: syscon@19180000 {
2071			compatible = "mediatek,mt8183-ipu_core0", "syscon";
2072			reg = <0 0x19180000 0 0x1000>;
2073			#clock-cells = <1>;
2074		};
2075
2076		ipu_core1: syscon@19280000 {
2077			compatible = "mediatek,mt8183-ipu_core1", "syscon";
2078			reg = <0 0x19280000 0 0x1000>;
2079			#clock-cells = <1>;
2080		};
2081
2082		camsys: syscon@1a000000 {
2083			compatible = "mediatek,mt8183-camsys", "syscon";
2084			reg = <0 0x1a000000 0 0x1000>;
2085			#clock-cells = <1>;
2086		};
2087
2088		larb6: larb@1a001000 {
2089			compatible = "mediatek,mt8183-smi-larb";
2090			reg = <0 0x1a001000 0 0x1000>;
2091			mediatek,smi = <&smi_common>;
2092			clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
2093				 <&mmsys CLK_MM_GALS_CAM2MM>;
2094			clock-names = "apb", "smi", "gals";
2095			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2096		};
2097
2098		larb3: larb@1a002000 {
2099			compatible = "mediatek,mt8183-smi-larb";
2100			reg = <0 0x1a002000 0 0x1000>;
2101			mediatek,smi = <&smi_common>;
2102			clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
2103				 <&mmsys CLK_MM_GALS_IPU12MM>;
2104			clock-names = "apb", "smi", "gals";
2105			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
2106		};
2107	};
2108};
2109