1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include "mt8183-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt8183"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c7; 29 i2c8 = &i2c8; 30 i2c9 = &i2c9; 31 i2c10 = &i2c10; 32 i2c11 = &i2c11; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 core1 { 45 cpu = <&cpu1>; 46 }; 47 core2 { 48 cpu = <&cpu2>; 49 }; 50 core3 { 51 cpu = <&cpu3>; 52 }; 53 }; 54 55 cluster1 { 56 core0 { 57 cpu = <&cpu4>; 58 }; 59 core1 { 60 cpu = <&cpu5>; 61 }; 62 core2 { 63 cpu = <&cpu6>; 64 }; 65 core3 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x000>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <741>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 78 dynamic-power-coefficient = <84>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x001>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <741>; 88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 89 dynamic-power-coefficient = <84>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x002>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <741>; 99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 100 dynamic-power-coefficient = <84>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu3: cpu@3 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x003>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <741>; 110 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 111 dynamic-power-coefficient = <84>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a73"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <1024>; 121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 122 dynamic-power-coefficient = <211>; 123 #cooling-cells = <2>; 124 }; 125 126 cpu5: cpu@101 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a73"; 129 reg = <0x101>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 133 dynamic-power-coefficient = <211>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu6: cpu@102 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a73"; 140 reg = <0x102>; 141 enable-method = "psci"; 142 capacity-dmips-mhz = <1024>; 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 144 dynamic-power-coefficient = <211>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a73"; 151 reg = <0x103>; 152 enable-method = "psci"; 153 capacity-dmips-mhz = <1024>; 154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 155 dynamic-power-coefficient = <211>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 CPU_SLEEP: cpu-sleep { 163 compatible = "arm,idle-state"; 164 local-timer-stop; 165 arm,psci-suspend-param = <0x00010001>; 166 entry-latency-us = <200>; 167 exit-latency-us = <200>; 168 min-residency-us = <800>; 169 }; 170 171 CLUSTER_SLEEP0: cluster-sleep-0 { 172 compatible = "arm,idle-state"; 173 local-timer-stop; 174 arm,psci-suspend-param = <0x01010001>; 175 entry-latency-us = <250>; 176 exit-latency-us = <400>; 177 min-residency-us = <1000>; 178 }; 179 CLUSTER_SLEEP1: cluster-sleep-1 { 180 compatible = "arm,idle-state"; 181 local-timer-stop; 182 arm,psci-suspend-param = <0x01010001>; 183 entry-latency-us = <250>; 184 exit-latency-us = <400>; 185 min-residency-us = <1300>; 186 }; 187 }; 188 }; 189 190 pmu-a53 { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupt-parent = <&gic>; 193 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 194 }; 195 196 pmu-a73 { 197 compatible = "arm,cortex-a73-pmu"; 198 interrupt-parent = <&gic>; 199 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 200 }; 201 202 psci { 203 compatible = "arm,psci-1.0"; 204 method = "smc"; 205 }; 206 207 clk26m: oscillator { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <26000000>; 211 clock-output-names = "clk26m"; 212 }; 213 214 timer { 215 compatible = "arm,armv8-timer"; 216 interrupt-parent = <&gic>; 217 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 218 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 219 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 220 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 221 }; 222 223 soc { 224 #address-cells = <2>; 225 #size-cells = <2>; 226 compatible = "simple-bus"; 227 ranges; 228 229 soc_data: soc_data@8000000 { 230 compatible = "mediatek,mt8183-efuse", 231 "mediatek,efuse"; 232 reg = <0 0x08000000 0 0x0010>; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 status = "disabled"; 236 }; 237 238 gic: interrupt-controller@c000000 { 239 compatible = "arm,gic-v3"; 240 #interrupt-cells = <4>; 241 interrupt-parent = <&gic>; 242 interrupt-controller; 243 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 244 <0 0x0c100000 0 0x200000>, /* GICR */ 245 <0 0x0c400000 0 0x2000>, /* GICC */ 246 <0 0x0c410000 0 0x1000>, /* GICH */ 247 <0 0x0c420000 0 0x2000>; /* GICV */ 248 249 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 250 ppi-partitions { 251 ppi_cluster0: interrupt-partition-0 { 252 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 253 }; 254 ppi_cluster1: interrupt-partition-1 { 255 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 256 }; 257 }; 258 }; 259 260 mcucfg: syscon@c530000 { 261 compatible = "mediatek,mt8183-mcucfg", "syscon"; 262 reg = <0 0x0c530000 0 0x1000>; 263 #clock-cells = <1>; 264 }; 265 266 sysirq: interrupt-controller@c530a80 { 267 compatible = "mediatek,mt8183-sysirq", 268 "mediatek,mt6577-sysirq"; 269 interrupt-controller; 270 #interrupt-cells = <3>; 271 interrupt-parent = <&gic>; 272 reg = <0 0x0c530a80 0 0x50>; 273 }; 274 275 topckgen: syscon@10000000 { 276 compatible = "mediatek,mt8183-topckgen", "syscon"; 277 reg = <0 0x10000000 0 0x1000>; 278 #clock-cells = <1>; 279 }; 280 281 infracfg: syscon@10001000 { 282 compatible = "mediatek,mt8183-infracfg", "syscon"; 283 reg = <0 0x10001000 0 0x1000>; 284 #clock-cells = <1>; 285 #reset-cells = <1>; 286 }; 287 288 pericfg: syscon@10003000 { 289 compatible = "mediatek,mt8183-pericfg", "syscon"; 290 reg = <0 0x10003000 0 0x1000>; 291 #clock-cells = <1>; 292 }; 293 294 pio: pinctrl@10005000 { 295 compatible = "mediatek,mt8183-pinctrl"; 296 reg = <0 0x10005000 0 0x1000>, 297 <0 0x11f20000 0 0x1000>, 298 <0 0x11e80000 0 0x1000>, 299 <0 0x11e70000 0 0x1000>, 300 <0 0x11e90000 0 0x1000>, 301 <0 0x11d30000 0 0x1000>, 302 <0 0x11d20000 0 0x1000>, 303 <0 0x11c50000 0 0x1000>, 304 <0 0x11f30000 0 0x1000>, 305 <0 0x1000b000 0 0x1000>; 306 reg-names = "iocfg0", "iocfg1", "iocfg2", 307 "iocfg3", "iocfg4", "iocfg5", 308 "iocfg6", "iocfg7", "iocfg8", 309 "eint"; 310 gpio-controller; 311 #gpio-cells = <2>; 312 gpio-ranges = <&pio 0 0 192>; 313 interrupt-controller; 314 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 315 #interrupt-cells = <2>; 316 }; 317 318 watchdog: watchdog@10007000 { 319 compatible = "mediatek,mt8183-wdt", 320 "mediatek,mt6589-wdt"; 321 reg = <0 0x10007000 0 0x100>; 322 #reset-cells = <1>; 323 }; 324 325 apmixedsys: syscon@1000c000 { 326 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 327 reg = <0 0x1000c000 0 0x1000>; 328 #clock-cells = <1>; 329 }; 330 331 pwrap: pwrap@1000d000 { 332 compatible = "mediatek,mt8183-pwrap"; 333 reg = <0 0x1000d000 0 0x1000>; 334 reg-names = "pwrap"; 335 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 337 <&infracfg CLK_INFRA_PMIC_AP>; 338 clock-names = "spi", "wrap"; 339 }; 340 341 systimer: timer@10017000 { 342 compatible = "mediatek,mt8183-timer", 343 "mediatek,mt6765-timer"; 344 reg = <0 0x10017000 0 0x1000>; 345 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&topckgen CLK_TOP_CLK13M>; 347 clock-names = "clk13m"; 348 }; 349 350 gce: mailbox@10238000 { 351 compatible = "mediatek,mt8183-gce"; 352 reg = <0 0x10238000 0 0x4000>; 353 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 354 #mbox-cells = <3>; 355 clocks = <&infracfg CLK_INFRA_GCE>; 356 clock-names = "gce"; 357 }; 358 359 auxadc: auxadc@11001000 { 360 compatible = "mediatek,mt8183-auxadc", 361 "mediatek,mt8173-auxadc"; 362 reg = <0 0x11001000 0 0x1000>; 363 clocks = <&infracfg CLK_INFRA_AUXADC>; 364 clock-names = "main"; 365 #io-channel-cells = <1>; 366 status = "disabled"; 367 }; 368 369 uart0: serial@11002000 { 370 compatible = "mediatek,mt8183-uart", 371 "mediatek,mt6577-uart"; 372 reg = <0 0x11002000 0 0x1000>; 373 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 374 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 375 clock-names = "baud", "bus"; 376 status = "disabled"; 377 }; 378 379 uart1: serial@11003000 { 380 compatible = "mediatek,mt8183-uart", 381 "mediatek,mt6577-uart"; 382 reg = <0 0x11003000 0 0x1000>; 383 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 384 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 385 clock-names = "baud", "bus"; 386 status = "disabled"; 387 }; 388 389 uart2: serial@11004000 { 390 compatible = "mediatek,mt8183-uart", 391 "mediatek,mt6577-uart"; 392 reg = <0 0x11004000 0 0x1000>; 393 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 394 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 395 clock-names = "baud", "bus"; 396 status = "disabled"; 397 }; 398 399 i2c6: i2c@11005000 { 400 compatible = "mediatek,mt8183-i2c"; 401 reg = <0 0x11005000 0 0x1000>, 402 <0 0x11000600 0 0x80>; 403 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 404 clocks = <&infracfg CLK_INFRA_I2C6>, 405 <&infracfg CLK_INFRA_AP_DMA>; 406 clock-names = "main", "dma"; 407 clock-div = <1>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 i2c0: i2c@11007000 { 414 compatible = "mediatek,mt8183-i2c"; 415 reg = <0 0x11007000 0 0x1000>, 416 <0 0x11000080 0 0x80>; 417 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 418 clocks = <&infracfg CLK_INFRA_I2C0>, 419 <&infracfg CLK_INFRA_AP_DMA>; 420 clock-names = "main", "dma"; 421 clock-div = <1>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 427 i2c4: i2c@11008000 { 428 compatible = "mediatek,mt8183-i2c"; 429 reg = <0 0x11008000 0 0x1000>, 430 <0 0x11000100 0 0x80>; 431 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 432 clocks = <&infracfg CLK_INFRA_I2C1>, 433 <&infracfg CLK_INFRA_AP_DMA>, 434 <&infracfg CLK_INFRA_I2C1_ARBITER>; 435 clock-names = "main", "dma","arb"; 436 clock-div = <1>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 }; 441 442 i2c2: i2c@11009000 { 443 compatible = "mediatek,mt8183-i2c"; 444 reg = <0 0x11009000 0 0x1000>, 445 <0 0x11000280 0 0x80>; 446 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 447 clocks = <&infracfg CLK_INFRA_I2C2>, 448 <&infracfg CLK_INFRA_AP_DMA>, 449 <&infracfg CLK_INFRA_I2C2_ARBITER>; 450 clock-names = "main", "dma", "arb"; 451 clock-div = <1>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 status = "disabled"; 455 }; 456 457 spi0: spi@1100a000 { 458 compatible = "mediatek,mt8183-spi"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0 0x1100a000 0 0x1000>; 462 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 463 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 464 <&topckgen CLK_TOP_MUX_SPI>, 465 <&infracfg CLK_INFRA_SPI0>; 466 clock-names = "parent-clk", "sel-clk", "spi-clk"; 467 status = "disabled"; 468 }; 469 470 i2c3: i2c@1100f000 { 471 compatible = "mediatek,mt8183-i2c"; 472 reg = <0 0x1100f000 0 0x1000>, 473 <0 0x11000400 0 0x80>; 474 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 475 clocks = <&infracfg CLK_INFRA_I2C3>, 476 <&infracfg CLK_INFRA_AP_DMA>; 477 clock-names = "main", "dma"; 478 clock-div = <1>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 status = "disabled"; 482 }; 483 484 spi1: spi@11010000 { 485 compatible = "mediatek,mt8183-spi"; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 reg = <0 0x11010000 0 0x1000>; 489 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 490 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 491 <&topckgen CLK_TOP_MUX_SPI>, 492 <&infracfg CLK_INFRA_SPI1>; 493 clock-names = "parent-clk", "sel-clk", "spi-clk"; 494 status = "disabled"; 495 }; 496 497 i2c1: i2c@11011000 { 498 compatible = "mediatek,mt8183-i2c"; 499 reg = <0 0x11011000 0 0x1000>, 500 <0 0x11000480 0 0x80>; 501 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 502 clocks = <&infracfg CLK_INFRA_I2C4>, 503 <&infracfg CLK_INFRA_AP_DMA>; 504 clock-names = "main", "dma"; 505 clock-div = <1>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 spi2: spi@11012000 { 512 compatible = "mediatek,mt8183-spi"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0 0x11012000 0 0x1000>; 516 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 517 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 518 <&topckgen CLK_TOP_MUX_SPI>, 519 <&infracfg CLK_INFRA_SPI2>; 520 clock-names = "parent-clk", "sel-clk", "spi-clk"; 521 status = "disabled"; 522 }; 523 524 spi3: spi@11013000 { 525 compatible = "mediatek,mt8183-spi"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 reg = <0 0x11013000 0 0x1000>; 529 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 531 <&topckgen CLK_TOP_MUX_SPI>, 532 <&infracfg CLK_INFRA_SPI3>; 533 clock-names = "parent-clk", "sel-clk", "spi-clk"; 534 status = "disabled"; 535 }; 536 537 i2c9: i2c@11014000 { 538 compatible = "mediatek,mt8183-i2c"; 539 reg = <0 0x11014000 0 0x1000>, 540 <0 0x11000180 0 0x80>; 541 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 543 <&infracfg CLK_INFRA_AP_DMA>, 544 <&infracfg CLK_INFRA_I2C1_ARBITER>; 545 clock-names = "main", "dma", "arb"; 546 clock-div = <1>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 i2c10: i2c@11015000 { 553 compatible = "mediatek,mt8183-i2c"; 554 reg = <0 0x11015000 0 0x1000>, 555 <0 0x11000300 0 0x80>; 556 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 557 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 558 <&infracfg CLK_INFRA_AP_DMA>, 559 <&infracfg CLK_INFRA_I2C2_ARBITER>; 560 clock-names = "main", "dma", "arb"; 561 clock-div = <1>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 i2c5: i2c@11016000 { 568 compatible = "mediatek,mt8183-i2c"; 569 reg = <0 0x11016000 0 0x1000>, 570 <0 0x11000500 0 0x80>; 571 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 572 clocks = <&infracfg CLK_INFRA_I2C5>, 573 <&infracfg CLK_INFRA_AP_DMA>, 574 <&infracfg CLK_INFRA_I2C5_ARBITER>; 575 clock-names = "main", "dma", "arb"; 576 clock-div = <1>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 status = "disabled"; 580 }; 581 582 i2c11: i2c@11017000 { 583 compatible = "mediatek,mt8183-i2c"; 584 reg = <0 0x11017000 0 0x1000>, 585 <0 0x11000580 0 0x80>; 586 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 587 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 588 <&infracfg CLK_INFRA_AP_DMA>, 589 <&infracfg CLK_INFRA_I2C5_ARBITER>; 590 clock-names = "main", "dma", "arb"; 591 clock-div = <1>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 spi4: spi@11018000 { 598 compatible = "mediatek,mt8183-spi"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 reg = <0 0x11018000 0 0x1000>; 602 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 603 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 604 <&topckgen CLK_TOP_MUX_SPI>, 605 <&infracfg CLK_INFRA_SPI4>; 606 clock-names = "parent-clk", "sel-clk", "spi-clk"; 607 status = "disabled"; 608 }; 609 610 spi5: spi@11019000 { 611 compatible = "mediatek,mt8183-spi"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 reg = <0 0x11019000 0 0x1000>; 615 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 616 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 617 <&topckgen CLK_TOP_MUX_SPI>, 618 <&infracfg CLK_INFRA_SPI5>; 619 clock-names = "parent-clk", "sel-clk", "spi-clk"; 620 status = "disabled"; 621 }; 622 623 i2c7: i2c@1101a000 { 624 compatible = "mediatek,mt8183-i2c"; 625 reg = <0 0x1101a000 0 0x1000>, 626 <0 0x11000680 0 0x80>; 627 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 628 clocks = <&infracfg CLK_INFRA_I2C7>, 629 <&infracfg CLK_INFRA_AP_DMA>; 630 clock-names = "main", "dma"; 631 clock-div = <1>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 637 i2c8: i2c@1101b000 { 638 compatible = "mediatek,mt8183-i2c"; 639 reg = <0 0x1101b000 0 0x1000>, 640 <0 0x11000700 0 0x80>; 641 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 642 clocks = <&infracfg CLK_INFRA_I2C8>, 643 <&infracfg CLK_INFRA_AP_DMA>; 644 clock-names = "main", "dma"; 645 clock-div = <1>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 audiosys: syscon@11220000 { 652 compatible = "mediatek,mt8183-audiosys", "syscon"; 653 reg = <0 0x11220000 0 0x1000>; 654 #clock-cells = <1>; 655 }; 656 657 mmc0: mmc@11230000 { 658 compatible = "mediatek,mt8183-mmc"; 659 reg = <0 0x11230000 0 0x1000>, 660 <0 0x11f50000 0 0x1000>; 661 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 662 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 663 <&infracfg CLK_INFRA_MSDC0>, 664 <&infracfg CLK_INFRA_MSDC0_SCK>; 665 clock-names = "source", "hclk", "source_cg"; 666 status = "disabled"; 667 }; 668 669 mmc1: mmc@11240000 { 670 compatible = "mediatek,mt8183-mmc"; 671 reg = <0 0x11240000 0 0x1000>, 672 <0 0x11e10000 0 0x1000>; 673 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 674 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 675 <&infracfg CLK_INFRA_MSDC1>, 676 <&infracfg CLK_INFRA_MSDC1_SCK>; 677 clock-names = "source", "hclk", "source_cg"; 678 status = "disabled"; 679 }; 680 681 efuse: efuse@11f10000 { 682 compatible = "mediatek,mt8183-efuse", 683 "mediatek,efuse"; 684 reg = <0 0x11f10000 0 0x1000>; 685 }; 686 687 mfgcfg: syscon@13000000 { 688 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 689 reg = <0 0x13000000 0 0x1000>; 690 #clock-cells = <1>; 691 }; 692 693 mmsys: syscon@14000000 { 694 compatible = "mediatek,mt8183-mmsys", "syscon"; 695 reg = <0 0x14000000 0 0x1000>; 696 #clock-cells = <1>; 697 }; 698 699 imgsys: syscon@15020000 { 700 compatible = "mediatek,mt8183-imgsys", "syscon"; 701 reg = <0 0x15020000 0 0x1000>; 702 #clock-cells = <1>; 703 }; 704 705 vdecsys: syscon@16000000 { 706 compatible = "mediatek,mt8183-vdecsys", "syscon"; 707 reg = <0 0x16000000 0 0x1000>; 708 #clock-cells = <1>; 709 }; 710 711 vencsys: syscon@17000000 { 712 compatible = "mediatek,mt8183-vencsys", "syscon"; 713 reg = <0 0x17000000 0 0x1000>; 714 #clock-cells = <1>; 715 }; 716 717 ipu_conn: syscon@19000000 { 718 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 719 reg = <0 0x19000000 0 0x1000>; 720 #clock-cells = <1>; 721 }; 722 723 ipu_adl: syscon@19010000 { 724 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 725 reg = <0 0x19010000 0 0x1000>; 726 #clock-cells = <1>; 727 }; 728 729 ipu_core0: syscon@19180000 { 730 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 731 reg = <0 0x19180000 0 0x1000>; 732 #clock-cells = <1>; 733 }; 734 735 ipu_core1: syscon@19280000 { 736 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 737 reg = <0 0x19280000 0 0x1000>; 738 #clock-cells = <1>; 739 }; 740 741 camsys: syscon@1a000000 { 742 compatible = "mediatek,mt8183-camsys", "syscon"; 743 reg = <0 0x1a000000 0 0x1000>; 744 #clock-cells = <1>; 745 }; 746 }; 747}; 748