1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include <dt-bindings/phy/phy.h> 13#include "mt8183-pinfunc.h" 14 15/ { 16 compatible = "mediatek,mt8183"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 i2c9 = &i2c9; 32 i2c10 = &i2c10; 33 i2c11 = &i2c11; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&cpu0>; 44 }; 45 core1 { 46 cpu = <&cpu1>; 47 }; 48 core2 { 49 cpu = <&cpu2>; 50 }; 51 core3 { 52 cpu = <&cpu3>; 53 }; 54 }; 55 56 cluster1 { 57 core0 { 58 cpu = <&cpu4>; 59 }; 60 core1 { 61 cpu = <&cpu5>; 62 }; 63 core2 { 64 cpu = <&cpu6>; 65 }; 66 core3 { 67 cpu = <&cpu7>; 68 }; 69 }; 70 }; 71 72 cpu0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x000>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <741>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 79 dynamic-power-coefficient = <84>; 80 #cooling-cells = <2>; 81 }; 82 83 cpu1: cpu@1 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x001>; 87 enable-method = "psci"; 88 capacity-dmips-mhz = <741>; 89 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 90 dynamic-power-coefficient = <84>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x002>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <741>; 100 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 101 dynamic-power-coefficient = <84>; 102 #cooling-cells = <2>; 103 }; 104 105 cpu3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x003>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <741>; 111 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 112 dynamic-power-coefficient = <84>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu4: cpu@100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a73"; 119 reg = <0x100>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 123 dynamic-power-coefficient = <211>; 124 #cooling-cells = <2>; 125 }; 126 127 cpu5: cpu@101 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a73"; 130 reg = <0x101>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <1024>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 134 dynamic-power-coefficient = <211>; 135 #cooling-cells = <2>; 136 }; 137 138 cpu6: cpu@102 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a73"; 141 reg = <0x102>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 145 dynamic-power-coefficient = <211>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu7: cpu@103 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a73"; 152 reg = <0x103>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 156 dynamic-power-coefficient = <211>; 157 #cooling-cells = <2>; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 CPU_SLEEP: cpu-sleep { 164 compatible = "arm,idle-state"; 165 local-timer-stop; 166 arm,psci-suspend-param = <0x00010001>; 167 entry-latency-us = <200>; 168 exit-latency-us = <200>; 169 min-residency-us = <800>; 170 }; 171 172 CLUSTER_SLEEP0: cluster-sleep-0 { 173 compatible = "arm,idle-state"; 174 local-timer-stop; 175 arm,psci-suspend-param = <0x01010001>; 176 entry-latency-us = <250>; 177 exit-latency-us = <400>; 178 min-residency-us = <1000>; 179 }; 180 CLUSTER_SLEEP1: cluster-sleep-1 { 181 compatible = "arm,idle-state"; 182 local-timer-stop; 183 arm,psci-suspend-param = <0x01010001>; 184 entry-latency-us = <250>; 185 exit-latency-us = <400>; 186 min-residency-us = <1300>; 187 }; 188 }; 189 }; 190 191 pmu-a53 { 192 compatible = "arm,cortex-a53-pmu"; 193 interrupt-parent = <&gic>; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 195 }; 196 197 pmu-a73 { 198 compatible = "arm,cortex-a73-pmu"; 199 interrupt-parent = <&gic>; 200 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 201 }; 202 203 psci { 204 compatible = "arm,psci-1.0"; 205 method = "smc"; 206 }; 207 208 clk26m: oscillator { 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <26000000>; 212 clock-output-names = "clk26m"; 213 }; 214 215 timer { 216 compatible = "arm,armv8-timer"; 217 interrupt-parent = <&gic>; 218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 222 }; 223 224 soc { 225 #address-cells = <2>; 226 #size-cells = <2>; 227 compatible = "simple-bus"; 228 ranges; 229 230 soc_data: soc_data@8000000 { 231 compatible = "mediatek,mt8183-efuse", 232 "mediatek,efuse"; 233 reg = <0 0x08000000 0 0x0010>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 status = "disabled"; 237 }; 238 239 gic: interrupt-controller@c000000 { 240 compatible = "arm,gic-v3"; 241 #interrupt-cells = <4>; 242 interrupt-parent = <&gic>; 243 interrupt-controller; 244 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 245 <0 0x0c100000 0 0x200000>, /* GICR */ 246 <0 0x0c400000 0 0x2000>, /* GICC */ 247 <0 0x0c410000 0 0x1000>, /* GICH */ 248 <0 0x0c420000 0 0x2000>; /* GICV */ 249 250 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 251 ppi-partitions { 252 ppi_cluster0: interrupt-partition-0 { 253 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 254 }; 255 ppi_cluster1: interrupt-partition-1 { 256 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 257 }; 258 }; 259 }; 260 261 mcucfg: syscon@c530000 { 262 compatible = "mediatek,mt8183-mcucfg", "syscon"; 263 reg = <0 0x0c530000 0 0x1000>; 264 #clock-cells = <1>; 265 }; 266 267 sysirq: interrupt-controller@c530a80 { 268 compatible = "mediatek,mt8183-sysirq", 269 "mediatek,mt6577-sysirq"; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 interrupt-parent = <&gic>; 273 reg = <0 0x0c530a80 0 0x50>; 274 }; 275 276 topckgen: syscon@10000000 { 277 compatible = "mediatek,mt8183-topckgen", "syscon"; 278 reg = <0 0x10000000 0 0x1000>; 279 #clock-cells = <1>; 280 }; 281 282 infracfg: syscon@10001000 { 283 compatible = "mediatek,mt8183-infracfg", "syscon"; 284 reg = <0 0x10001000 0 0x1000>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 }; 288 289 pericfg: syscon@10003000 { 290 compatible = "mediatek,mt8183-pericfg", "syscon"; 291 reg = <0 0x10003000 0 0x1000>; 292 #clock-cells = <1>; 293 }; 294 295 pio: pinctrl@10005000 { 296 compatible = "mediatek,mt8183-pinctrl"; 297 reg = <0 0x10005000 0 0x1000>, 298 <0 0x11f20000 0 0x1000>, 299 <0 0x11e80000 0 0x1000>, 300 <0 0x11e70000 0 0x1000>, 301 <0 0x11e90000 0 0x1000>, 302 <0 0x11d30000 0 0x1000>, 303 <0 0x11d20000 0 0x1000>, 304 <0 0x11c50000 0 0x1000>, 305 <0 0x11f30000 0 0x1000>, 306 <0 0x1000b000 0 0x1000>; 307 reg-names = "iocfg0", "iocfg1", "iocfg2", 308 "iocfg3", "iocfg4", "iocfg5", 309 "iocfg6", "iocfg7", "iocfg8", 310 "eint"; 311 gpio-controller; 312 #gpio-cells = <2>; 313 gpio-ranges = <&pio 0 0 192>; 314 interrupt-controller; 315 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 316 #interrupt-cells = <2>; 317 }; 318 319 watchdog: watchdog@10007000 { 320 compatible = "mediatek,mt8183-wdt", 321 "mediatek,mt6589-wdt"; 322 reg = <0 0x10007000 0 0x100>; 323 #reset-cells = <1>; 324 }; 325 326 apmixedsys: syscon@1000c000 { 327 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 328 reg = <0 0x1000c000 0 0x1000>; 329 #clock-cells = <1>; 330 }; 331 332 pwrap: pwrap@1000d000 { 333 compatible = "mediatek,mt8183-pwrap"; 334 reg = <0 0x1000d000 0 0x1000>; 335 reg-names = "pwrap"; 336 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 338 <&infracfg CLK_INFRA_PMIC_AP>; 339 clock-names = "spi", "wrap"; 340 }; 341 342 scp: scp@10500000 { 343 compatible = "mediatek,mt8183-scp"; 344 reg = <0 0x10500000 0 0x80000>, 345 <0 0x105c0000 0 0x19080>; 346 reg-names = "sram", "cfg"; 347 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&infracfg CLK_INFRA_SCPSYS>; 349 clock-names = "main"; 350 memory-region = <&scp_mem_reserved>; 351 status = "disabled"; 352 }; 353 354 systimer: timer@10017000 { 355 compatible = "mediatek,mt8183-timer", 356 "mediatek,mt6765-timer"; 357 reg = <0 0x10017000 0 0x1000>; 358 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&topckgen CLK_TOP_CLK13M>; 360 clock-names = "clk13m"; 361 }; 362 363 gce: mailbox@10238000 { 364 compatible = "mediatek,mt8183-gce"; 365 reg = <0 0x10238000 0 0x4000>; 366 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 367 #mbox-cells = <3>; 368 clocks = <&infracfg CLK_INFRA_GCE>; 369 clock-names = "gce"; 370 }; 371 372 auxadc: auxadc@11001000 { 373 compatible = "mediatek,mt8183-auxadc", 374 "mediatek,mt8173-auxadc"; 375 reg = <0 0x11001000 0 0x1000>; 376 clocks = <&infracfg CLK_INFRA_AUXADC>; 377 clock-names = "main"; 378 #io-channel-cells = <1>; 379 status = "disabled"; 380 }; 381 382 uart0: serial@11002000 { 383 compatible = "mediatek,mt8183-uart", 384 "mediatek,mt6577-uart"; 385 reg = <0 0x11002000 0 0x1000>; 386 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 387 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 388 clock-names = "baud", "bus"; 389 status = "disabled"; 390 }; 391 392 uart1: serial@11003000 { 393 compatible = "mediatek,mt8183-uart", 394 "mediatek,mt6577-uart"; 395 reg = <0 0x11003000 0 0x1000>; 396 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 397 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 398 clock-names = "baud", "bus"; 399 status = "disabled"; 400 }; 401 402 uart2: serial@11004000 { 403 compatible = "mediatek,mt8183-uart", 404 "mediatek,mt6577-uart"; 405 reg = <0 0x11004000 0 0x1000>; 406 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 407 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 408 clock-names = "baud", "bus"; 409 status = "disabled"; 410 }; 411 412 i2c6: i2c@11005000 { 413 compatible = "mediatek,mt8183-i2c"; 414 reg = <0 0x11005000 0 0x1000>, 415 <0 0x11000600 0 0x80>; 416 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 417 clocks = <&infracfg CLK_INFRA_I2C6>, 418 <&infracfg CLK_INFRA_AP_DMA>; 419 clock-names = "main", "dma"; 420 clock-div = <1>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 status = "disabled"; 424 }; 425 426 i2c0: i2c@11007000 { 427 compatible = "mediatek,mt8183-i2c"; 428 reg = <0 0x11007000 0 0x1000>, 429 <0 0x11000080 0 0x80>; 430 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 431 clocks = <&infracfg CLK_INFRA_I2C0>, 432 <&infracfg CLK_INFRA_AP_DMA>; 433 clock-names = "main", "dma"; 434 clock-div = <1>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 status = "disabled"; 438 }; 439 440 i2c4: i2c@11008000 { 441 compatible = "mediatek,mt8183-i2c"; 442 reg = <0 0x11008000 0 0x1000>, 443 <0 0x11000100 0 0x80>; 444 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 445 clocks = <&infracfg CLK_INFRA_I2C1>, 446 <&infracfg CLK_INFRA_AP_DMA>, 447 <&infracfg CLK_INFRA_I2C1_ARBITER>; 448 clock-names = "main", "dma","arb"; 449 clock-div = <1>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 455 i2c2: i2c@11009000 { 456 compatible = "mediatek,mt8183-i2c"; 457 reg = <0 0x11009000 0 0x1000>, 458 <0 0x11000280 0 0x80>; 459 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 460 clocks = <&infracfg CLK_INFRA_I2C2>, 461 <&infracfg CLK_INFRA_AP_DMA>, 462 <&infracfg CLK_INFRA_I2C2_ARBITER>; 463 clock-names = "main", "dma", "arb"; 464 clock-div = <1>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 spi0: spi@1100a000 { 471 compatible = "mediatek,mt8183-spi"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 reg = <0 0x1100a000 0 0x1000>; 475 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 476 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 477 <&topckgen CLK_TOP_MUX_SPI>, 478 <&infracfg CLK_INFRA_SPI0>; 479 clock-names = "parent-clk", "sel-clk", "spi-clk"; 480 status = "disabled"; 481 }; 482 483 i2c3: i2c@1100f000 { 484 compatible = "mediatek,mt8183-i2c"; 485 reg = <0 0x1100f000 0 0x1000>, 486 <0 0x11000400 0 0x80>; 487 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 488 clocks = <&infracfg CLK_INFRA_I2C3>, 489 <&infracfg CLK_INFRA_AP_DMA>; 490 clock-names = "main", "dma"; 491 clock-div = <1>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 status = "disabled"; 495 }; 496 497 spi1: spi@11010000 { 498 compatible = "mediatek,mt8183-spi"; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <0 0x11010000 0 0x1000>; 502 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 503 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 504 <&topckgen CLK_TOP_MUX_SPI>, 505 <&infracfg CLK_INFRA_SPI1>; 506 clock-names = "parent-clk", "sel-clk", "spi-clk"; 507 status = "disabled"; 508 }; 509 510 i2c1: i2c@11011000 { 511 compatible = "mediatek,mt8183-i2c"; 512 reg = <0 0x11011000 0 0x1000>, 513 <0 0x11000480 0 0x80>; 514 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 515 clocks = <&infracfg CLK_INFRA_I2C4>, 516 <&infracfg CLK_INFRA_AP_DMA>; 517 clock-names = "main", "dma"; 518 clock-div = <1>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 status = "disabled"; 522 }; 523 524 spi2: spi@11012000 { 525 compatible = "mediatek,mt8183-spi"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 reg = <0 0x11012000 0 0x1000>; 529 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 531 <&topckgen CLK_TOP_MUX_SPI>, 532 <&infracfg CLK_INFRA_SPI2>; 533 clock-names = "parent-clk", "sel-clk", "spi-clk"; 534 status = "disabled"; 535 }; 536 537 spi3: spi@11013000 { 538 compatible = "mediatek,mt8183-spi"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0 0x11013000 0 0x1000>; 542 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 543 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 544 <&topckgen CLK_TOP_MUX_SPI>, 545 <&infracfg CLK_INFRA_SPI3>; 546 clock-names = "parent-clk", "sel-clk", "spi-clk"; 547 status = "disabled"; 548 }; 549 550 i2c9: i2c@11014000 { 551 compatible = "mediatek,mt8183-i2c"; 552 reg = <0 0x11014000 0 0x1000>, 553 <0 0x11000180 0 0x80>; 554 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 555 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 556 <&infracfg CLK_INFRA_AP_DMA>, 557 <&infracfg CLK_INFRA_I2C1_ARBITER>; 558 clock-names = "main", "dma", "arb"; 559 clock-div = <1>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 i2c10: i2c@11015000 { 566 compatible = "mediatek,mt8183-i2c"; 567 reg = <0 0x11015000 0 0x1000>, 568 <0 0x11000300 0 0x80>; 569 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 570 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 571 <&infracfg CLK_INFRA_AP_DMA>, 572 <&infracfg CLK_INFRA_I2C2_ARBITER>; 573 clock-names = "main", "dma", "arb"; 574 clock-div = <1>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c5: i2c@11016000 { 581 compatible = "mediatek,mt8183-i2c"; 582 reg = <0 0x11016000 0 0x1000>, 583 <0 0x11000500 0 0x80>; 584 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 585 clocks = <&infracfg CLK_INFRA_I2C5>, 586 <&infracfg CLK_INFRA_AP_DMA>, 587 <&infracfg CLK_INFRA_I2C5_ARBITER>; 588 clock-names = "main", "dma", "arb"; 589 clock-div = <1>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 595 i2c11: i2c@11017000 { 596 compatible = "mediatek,mt8183-i2c"; 597 reg = <0 0x11017000 0 0x1000>, 598 <0 0x11000580 0 0x80>; 599 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 600 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 601 <&infracfg CLK_INFRA_AP_DMA>, 602 <&infracfg CLK_INFRA_I2C5_ARBITER>; 603 clock-names = "main", "dma", "arb"; 604 clock-div = <1>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 spi4: spi@11018000 { 611 compatible = "mediatek,mt8183-spi"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 reg = <0 0x11018000 0 0x1000>; 615 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 616 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 617 <&topckgen CLK_TOP_MUX_SPI>, 618 <&infracfg CLK_INFRA_SPI4>; 619 clock-names = "parent-clk", "sel-clk", "spi-clk"; 620 status = "disabled"; 621 }; 622 623 spi5: spi@11019000 { 624 compatible = "mediatek,mt8183-spi"; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 reg = <0 0x11019000 0 0x1000>; 628 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 629 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 630 <&topckgen CLK_TOP_MUX_SPI>, 631 <&infracfg CLK_INFRA_SPI5>; 632 clock-names = "parent-clk", "sel-clk", "spi-clk"; 633 status = "disabled"; 634 }; 635 636 i2c7: i2c@1101a000 { 637 compatible = "mediatek,mt8183-i2c"; 638 reg = <0 0x1101a000 0 0x1000>, 639 <0 0x11000680 0 0x80>; 640 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 641 clocks = <&infracfg CLK_INFRA_I2C7>, 642 <&infracfg CLK_INFRA_AP_DMA>; 643 clock-names = "main", "dma"; 644 clock-div = <1>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 i2c8: i2c@1101b000 { 651 compatible = "mediatek,mt8183-i2c"; 652 reg = <0 0x1101b000 0 0x1000>, 653 <0 0x11000700 0 0x80>; 654 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 655 clocks = <&infracfg CLK_INFRA_I2C8>, 656 <&infracfg CLK_INFRA_AP_DMA>; 657 clock-names = "main", "dma"; 658 clock-div = <1>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 ssusb: usb@11201000 { 665 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 666 reg = <0 0x11201000 0 0x2e00>, 667 <0 0x11203e00 0 0x0100>; 668 reg-names = "mac", "ippc"; 669 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 670 phys = <&u2port0 PHY_TYPE_USB2>, 671 <&u3port0 PHY_TYPE_USB3>; 672 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 673 <&infracfg CLK_INFRA_USB>; 674 clock-names = "sys_ck", "ref_ck"; 675 mediatek,syscon-wakeup = <&pericfg 0x400 0>; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 ranges; 679 status = "disabled"; 680 681 usb_host: xhci@11200000 { 682 compatible = "mediatek,mt8183-xhci", 683 "mediatek,mtk-xhci"; 684 reg = <0 0x11200000 0 0x1000>; 685 reg-names = "mac"; 686 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 687 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 688 <&infracfg CLK_INFRA_USB>; 689 clock-names = "sys_ck", "ref_ck"; 690 status = "disabled"; 691 }; 692 }; 693 694 audiosys: syscon@11220000 { 695 compatible = "mediatek,mt8183-audiosys", "syscon"; 696 reg = <0 0x11220000 0 0x1000>; 697 #clock-cells = <1>; 698 }; 699 700 mmc0: mmc@11230000 { 701 compatible = "mediatek,mt8183-mmc"; 702 reg = <0 0x11230000 0 0x1000>, 703 <0 0x11f50000 0 0x1000>; 704 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 705 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 706 <&infracfg CLK_INFRA_MSDC0>, 707 <&infracfg CLK_INFRA_MSDC0_SCK>; 708 clock-names = "source", "hclk", "source_cg"; 709 status = "disabled"; 710 }; 711 712 mmc1: mmc@11240000 { 713 compatible = "mediatek,mt8183-mmc"; 714 reg = <0 0x11240000 0 0x1000>, 715 <0 0x11e10000 0 0x1000>; 716 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 717 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 718 <&infracfg CLK_INFRA_MSDC1>, 719 <&infracfg CLK_INFRA_MSDC1_SCK>; 720 clock-names = "source", "hclk", "source_cg"; 721 status = "disabled"; 722 }; 723 724 efuse: efuse@11f10000 { 725 compatible = "mediatek,mt8183-efuse", 726 "mediatek,efuse"; 727 reg = <0 0x11f10000 0 0x1000>; 728 }; 729 730 u3phy: usb-phy@11f40000 { 731 compatible = "mediatek,mt8183-tphy", 732 "mediatek,generic-tphy-v2"; 733 #address-cells = <1>; 734 #phy-cells = <1>; 735 #size-cells = <1>; 736 ranges = <0 0 0x11f40000 0x1000>; 737 status = "okay"; 738 739 u2port0: usb-phy@0 { 740 reg = <0x0 0x700>; 741 clocks = <&clk26m>; 742 clock-names = "ref"; 743 #phy-cells = <1>; 744 mediatek,discth = <15>; 745 status = "okay"; 746 }; 747 748 u3port0: usb-phy@0700 { 749 reg = <0x0700 0x900>; 750 clocks = <&clk26m>; 751 clock-names = "ref"; 752 #phy-cells = <1>; 753 status = "okay"; 754 }; 755 }; 756 757 mfgcfg: syscon@13000000 { 758 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 759 reg = <0 0x13000000 0 0x1000>; 760 #clock-cells = <1>; 761 }; 762 763 mmsys: syscon@14000000 { 764 compatible = "mediatek,mt8183-mmsys", "syscon"; 765 reg = <0 0x14000000 0 0x1000>; 766 #clock-cells = <1>; 767 }; 768 769 imgsys: syscon@15020000 { 770 compatible = "mediatek,mt8183-imgsys", "syscon"; 771 reg = <0 0x15020000 0 0x1000>; 772 #clock-cells = <1>; 773 }; 774 775 vdecsys: syscon@16000000 { 776 compatible = "mediatek,mt8183-vdecsys", "syscon"; 777 reg = <0 0x16000000 0 0x1000>; 778 #clock-cells = <1>; 779 }; 780 781 vencsys: syscon@17000000 { 782 compatible = "mediatek,mt8183-vencsys", "syscon"; 783 reg = <0 0x17000000 0 0x1000>; 784 #clock-cells = <1>; 785 }; 786 787 ipu_conn: syscon@19000000 { 788 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 789 reg = <0 0x19000000 0 0x1000>; 790 #clock-cells = <1>; 791 }; 792 793 ipu_adl: syscon@19010000 { 794 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 795 reg = <0 0x19010000 0 0x1000>; 796 #clock-cells = <1>; 797 }; 798 799 ipu_core0: syscon@19180000 { 800 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 801 reg = <0 0x19180000 0 0x1000>; 802 #clock-cells = <1>; 803 }; 804 805 ipu_core1: syscon@19280000 { 806 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 807 reg = <0 0x19280000 0 0x1000>; 808 #clock-cells = <1>; 809 }; 810 811 camsys: syscon@1a000000 { 812 compatible = "mediatek,mt8183-camsys", "syscon"; 813 reg = <0 0x1a000000 0 0x1000>; 814 #clock-cells = <1>; 815 }; 816 }; 817}; 818