1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <&bl_pp5000>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 gpio = <&pio 178 0>; 53 enable-active-high; 54 }; 55 56 lcd_pp3300: regulator1 { 57 compatible = "regulator-fixed"; 58 regulator-name = "lcd_pp3300"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 bl_pp5000: regulator2 { 66 compatible = "regulator-fixed"; 67 regulator-name = "bl_pp5000"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 mmc1_fixed_power: regulator3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "mmc1_power"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 }; 80 81 mmc1_fixed_io: regulator4 { 82 compatible = "regulator-fixed"; 83 regulator-name = "mmc1_io"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87 88 pp1800_alw: regulator5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp1800_alw"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <1800000>; 95 }; 96 97 pp3300_alw: regulator6 { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_alw"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges; 110 111 scp_mem_reserved: scp_mem_region { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x50000000 0 0x2900000>; 114 no-map; 115 }; 116 }; 117 118 sound: mt8183-sound { 119 mediatek,platform = <&afe>; 120 pinctrl-names = "default", 121 "aud_tdm_out_on", 122 "aud_tdm_out_off"; 123 pinctrl-0 = <&aud_pins_default>; 124 pinctrl-1 = <&aud_pins_tdm_out_on>; 125 pinctrl-2 = <&aud_pins_tdm_out_off>; 126 status = "okay"; 127 }; 128 129 btsco: bt-sco { 130 compatible = "linux,bt-sco"; 131 }; 132 133 wifi_pwrseq: wifi-pwrseq { 134 compatible = "mmc-pwrseq-simple"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&wifi_pins_pwrseq>; 137 138 /* Toggle WIFI_ENABLE to reset the chip. */ 139 reset-gpios = <&pio 119 1>; 140 }; 141 142 wifi_wakeup: wifi-wakeup { 143 compatible = "gpio-keys"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wifi_pins_wakeup>; 146 147 button-wowlan { 148 label = "Wake on WiFi"; 149 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 150 linux,code = <KEY_WAKEUP>; 151 wakeup-source; 152 }; 153 }; 154 155 tboard_thermistor1: thermal-sensor1 { 156 compatible = "generic-adc-thermal"; 157 #thermal-sensor-cells = <0>; 158 io-channels = <&auxadc 0>; 159 io-channel-names = "sensor-channel"; 160 temperature-lookup-table = < (-5000) 1553 161 0 1488 162 5000 1412 163 10000 1326 164 15000 1232 165 20000 1132 166 25000 1029 167 30000 925 168 35000 823 169 40000 726 170 45000 635 171 50000 552 172 55000 478 173 60000 411 174 65000 353 175 70000 303 176 75000 260 177 80000 222 178 85000 190 179 90000 163 180 95000 140 181 100000 121 182 105000 104 183 110000 90 184 115000 78 185 120000 67 186 125000 59>; 187 }; 188 189 tboard_thermistor2: thermal-sensor2 { 190 compatible = "generic-adc-thermal"; 191 #thermal-sensor-cells = <0>; 192 io-channels = <&auxadc 1>; 193 io-channel-names = "sensor-channel"; 194 temperature-lookup-table = < (-5000) 1553 195 0 1488 196 5000 1412 197 10000 1326 198 15000 1232 199 20000 1132 200 25000 1029 201 30000 925 202 35000 823 203 40000 726 204 45000 635 205 50000 552 206 55000 478 207 60000 411 208 65000 353 209 70000 303 210 75000 260 211 80000 222 212 85000 190 213 90000 163 214 95000 140 215 100000 121 216 105000 104 217 110000 90 218 115000 78 219 120000 67 220 125000 59>; 221 }; 222}; 223 224&afe { 225 i2s3-share = "I2S2"; 226 i2s0-share = "I2S5"; 227}; 228 229&auxadc { 230 status = "okay"; 231}; 232 233&cci { 234 proc-supply = <&mt6358_vproc12_reg>; 235}; 236 237&cpu0 { 238 proc-supply = <&mt6358_vproc12_reg>; 239}; 240 241&cpu1 { 242 proc-supply = <&mt6358_vproc12_reg>; 243}; 244 245&cpu2 { 246 proc-supply = <&mt6358_vproc12_reg>; 247}; 248 249&cpu3 { 250 proc-supply = <&mt6358_vproc12_reg>; 251}; 252 253&cpu4 { 254 proc-supply = <&mt6358_vproc11_reg>; 255}; 256 257&cpu5 { 258 proc-supply = <&mt6358_vproc11_reg>; 259}; 260 261&cpu6 { 262 proc-supply = <&mt6358_vproc11_reg>; 263}; 264 265&cpu7 { 266 proc-supply = <&mt6358_vproc11_reg>; 267}; 268 269&dsi0 { 270 status = "okay"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 panel: panel@0 { 274 /* compatible will be set in board dts */ 275 reg = <0>; 276 enable-gpios = <&pio 45 0>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&panel_pins_default>; 279 avdd-supply = <&ppvarn_lcd>; 280 avee-supply = <&ppvarp_lcd>; 281 pp1800-supply = <&pp1800_lcd>; 282 backlight = <&backlight_lcd0>; 283 port { 284 panel_in: endpoint { 285 remote-endpoint = <&dsi_out>; 286 }; 287 }; 288 }; 289 290 ports { 291 port { 292 dsi_out: endpoint { 293 remote-endpoint = <&panel_in>; 294 }; 295 }; 296 }; 297}; 298 299&gpu { 300 mali-supply = <&mt6358_vgpu_reg>; 301 sram-supply = <&mt6358_vsram_gpu_reg>; 302}; 303 304&i2c0 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&i2c0_pins>; 307 status = "okay"; 308 clock-frequency = <400000>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311}; 312 313&i2c1 { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&i2c1_pins>; 316 status = "okay"; 317 clock-frequency = <100000>; 318}; 319 320&i2c3 { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c3_pins>; 323 status = "okay"; 324 clock-frequency = <100000>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327}; 328 329&i2c5 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2c5_pins>; 332 status = "okay"; 333 clock-frequency = <100000>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336}; 337 338&i2c6 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&i2c6_pins>; 341 status = "okay"; 342 clock-frequency = <100000>; 343}; 344 345&mipi_tx0 { 346 status = "okay"; 347}; 348 349&mmc0 { 350 status = "okay"; 351 pinctrl-names = "default", "state_uhs"; 352 pinctrl-0 = <&mmc0_pins_default>; 353 pinctrl-1 = <&mmc0_pins_uhs>; 354 bus-width = <8>; 355 max-frequency = <200000000>; 356 cap-mmc-highspeed; 357 mmc-hs200-1_8v; 358 mmc-hs400-1_8v; 359 cap-mmc-hw-reset; 360 no-sdio; 361 no-sd; 362 hs400-ds-delay = <0x12814>; 363 vmmc-supply = <&mt6358_vemc_reg>; 364 vqmmc-supply = <&mt6358_vio18_reg>; 365 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 366 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 367 non-removable; 368}; 369 370&mmc1 { 371 status = "okay"; 372 pinctrl-names = "default", "state_uhs"; 373 pinctrl-0 = <&mmc1_pins_default>; 374 pinctrl-1 = <&mmc1_pins_uhs>; 375 vmmc-supply = <&mmc1_fixed_power>; 376 vqmmc-supply = <&mmc1_fixed_io>; 377 mmc-pwrseq = <&wifi_pwrseq>; 378 bus-width = <4>; 379 max-frequency = <200000000>; 380 drv-type = <2>; 381 cap-sd-highspeed; 382 sd-uhs-sdr50; 383 sd-uhs-sdr104; 384 keep-power-in-suspend; 385 enable-sdio-wakeup; 386 cap-sdio-irq; 387 non-removable; 388 no-mmc; 389 no-sd; 390 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 391 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 395 qca_wifi: qca-wifi@1 { 396 compatible = "qcom,ath10k"; 397 reg = <1>; 398 }; 399}; 400 401&mt6358_vdram2_reg { 402 regulator-always-on; 403}; 404 405&mt6358codec { 406 Avdd-supply = <&mt6358_vaud28_reg>; 407}; 408 409&mt6358_vsim1_reg { 410 regulator-min-microvolt = <2700000>; 411 regulator-max-microvolt = <2700000>; 412}; 413 414&mt6358_vsim2_reg { 415 regulator-min-microvolt = <2700000>; 416 regulator-max-microvolt = <2700000>; 417}; 418 419&pio { 420 aud_pins_default: audiopins { 421 pins_bus { 422 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 423 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 424 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 425 <PINMUX_GPIO102__FUNC_I2S2_DI>, 426 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 427 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 428 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 429 <PINMUX_GPIO91__FUNC_I2S5_DO>, 430 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 431 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 432 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 433 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 434 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 435 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 436 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 437 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 438 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 439 }; 440 }; 441 442 aud_pins_tdm_out_on: audiotdmouton { 443 pins_bus { 444 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 445 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 446 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 447 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 448 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 449 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 450 drive-strength = <MTK_DRIVE_6mA>; 451 }; 452 }; 453 454 aud_pins_tdm_out_off: audiotdmoutoff { 455 pins_bus { 456 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 457 <PINMUX_GPIO170__FUNC_GPIO170>, 458 <PINMUX_GPIO171__FUNC_GPIO171>, 459 <PINMUX_GPIO172__FUNC_GPIO172>, 460 <PINMUX_GPIO173__FUNC_GPIO173>, 461 <PINMUX_GPIO10__FUNC_GPIO10>; 462 input-enable; 463 bias-pull-down; 464 drive-strength = <MTK_DRIVE_2mA>; 465 }; 466 }; 467 468 bt_pins: bt-pins { 469 pins_bt_en { 470 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 471 output-low; 472 }; 473 }; 474 475 ec_ap_int_odl: ec_ap_int_odl { 476 pins1 { 477 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 478 input-enable; 479 bias-pull-up; 480 }; 481 }; 482 483 h1_int_od_l: h1_int_od_l { 484 pins1 { 485 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 486 input-enable; 487 }; 488 }; 489 490 i2c0_pins: i2c0 { 491 pins_bus { 492 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 493 <PINMUX_GPIO83__FUNC_SCL0>; 494 mediatek,pull-up-adv = <3>; 495 mediatek,drive-strength-adv = <00>; 496 }; 497 }; 498 499 i2c1_pins: i2c1 { 500 pins_bus { 501 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 502 <PINMUX_GPIO84__FUNC_SCL1>; 503 mediatek,pull-up-adv = <3>; 504 mediatek,drive-strength-adv = <00>; 505 }; 506 }; 507 508 i2c2_pins: i2c2 { 509 pins_bus { 510 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 511 <PINMUX_GPIO104__FUNC_SDA2>; 512 bias-disable; 513 mediatek,drive-strength-adv = <00>; 514 }; 515 }; 516 517 i2c3_pins: i2c3 { 518 pins_bus { 519 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 520 <PINMUX_GPIO51__FUNC_SDA3>; 521 mediatek,pull-up-adv = <3>; 522 mediatek,drive-strength-adv = <00>; 523 }; 524 }; 525 526 i2c4_pins: i2c4 { 527 pins_bus { 528 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 529 <PINMUX_GPIO106__FUNC_SDA4>; 530 bias-disable; 531 mediatek,drive-strength-adv = <00>; 532 }; 533 }; 534 535 i2c5_pins: i2c5 { 536 pins_bus { 537 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 538 <PINMUX_GPIO49__FUNC_SDA5>; 539 mediatek,pull-up-adv = <3>; 540 mediatek,drive-strength-adv = <00>; 541 }; 542 }; 543 544 i2c6_pins: i2c6 { 545 pins_bus { 546 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 547 <PINMUX_GPIO12__FUNC_SDA6>; 548 bias-disable; 549 }; 550 }; 551 552 mmc0_pins_default: mmc0-pins-default { 553 pins_cmd_dat { 554 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 555 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 556 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 557 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 558 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 559 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 560 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 561 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 562 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 563 input-enable; 564 drive-strength = <MTK_DRIVE_14mA>; 565 mediatek,pull-up-adv = <01>; 566 }; 567 568 pins_clk { 569 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 570 drive-strength = <MTK_DRIVE_14mA>; 571 mediatek,pull-down-adv = <10>; 572 }; 573 574 pins_rst { 575 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 576 drive-strength = <MTK_DRIVE_14mA>; 577 mediatek,pull-down-adv = <01>; 578 }; 579 }; 580 581 mmc0_pins_uhs: mmc0-pins-uhs { 582 pins_cmd_dat { 583 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 584 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 585 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 586 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 587 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 588 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 589 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 590 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 591 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 592 input-enable; 593 drive-strength = <MTK_DRIVE_14mA>; 594 mediatek,pull-up-adv = <01>; 595 }; 596 597 pins_clk { 598 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 599 drive-strength = <MTK_DRIVE_14mA>; 600 mediatek,pull-down-adv = <10>; 601 }; 602 603 pins_ds { 604 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 605 drive-strength = <MTK_DRIVE_14mA>; 606 mediatek,pull-down-adv = <10>; 607 }; 608 609 pins_rst { 610 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 611 drive-strength = <MTK_DRIVE_14mA>; 612 mediatek,pull-up-adv = <01>; 613 }; 614 }; 615 616 mmc1_pins_default: mmc1-pins-default { 617 pins_cmd_dat { 618 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 619 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 620 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 621 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 622 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 623 input-enable; 624 mediatek,pull-up-adv = <10>; 625 }; 626 627 pins_clk { 628 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 629 input-enable; 630 mediatek,pull-down-adv = <10>; 631 }; 632 }; 633 634 mmc1_pins_uhs: mmc1-pins-uhs { 635 pins_cmd_dat { 636 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 637 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 638 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 639 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 640 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 641 drive-strength = <MTK_DRIVE_6mA>; 642 input-enable; 643 mediatek,pull-up-adv = <10>; 644 }; 645 646 pins_clk { 647 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 648 drive-strength = <MTK_DRIVE_8mA>; 649 mediatek,pull-down-adv = <10>; 650 input-enable; 651 }; 652 }; 653 654 panel_pins_default: panel_pins_default { 655 panel_reset { 656 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 657 output-low; 658 bias-pull-up; 659 }; 660 }; 661 662 pwm0_pin_default: pwm0_pin_default { 663 pins1 { 664 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 665 output-high; 666 bias-pull-up; 667 }; 668 pins2 { 669 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 670 }; 671 }; 672 673 scp_pins: scp { 674 pins_scp_uart { 675 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 676 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 677 }; 678 }; 679 680 spi0_pins: spi0 { 681 pins_spi{ 682 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 683 <PINMUX_GPIO86__FUNC_GPIO86>, 684 <PINMUX_GPIO87__FUNC_SPI0_MO>, 685 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 686 bias-disable; 687 }; 688 }; 689 690 spi1_pins: spi1 { 691 pins_spi{ 692 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 693 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 694 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 695 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 696 bias-disable; 697 }; 698 }; 699 700 spi2_pins: spi2 { 701 pins_spi{ 702 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 703 <PINMUX_GPIO1__FUNC_SPI2_MO>, 704 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 705 bias-disable; 706 }; 707 pins_spi_mi { 708 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 709 mediatek,pull-down-adv = <00>; 710 }; 711 }; 712 713 spi3_pins: spi3 { 714 pins_spi{ 715 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 716 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 717 <PINMUX_GPIO23__FUNC_SPI3_MO>, 718 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 719 bias-disable; 720 }; 721 }; 722 723 spi4_pins: spi4 { 724 pins_spi{ 725 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 726 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 727 <PINMUX_GPIO19__FUNC_SPI4_MO>, 728 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 729 bias-disable; 730 }; 731 }; 732 733 spi5_pins: spi5 { 734 pins_spi{ 735 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 736 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 737 <PINMUX_GPIO15__FUNC_SPI5_MO>, 738 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 739 bias-disable; 740 }; 741 }; 742 743 uart0_pins_default: uart0-pins-default { 744 pins_rx { 745 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 746 input-enable; 747 bias-pull-up; 748 }; 749 pins_tx { 750 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 751 }; 752 }; 753 754 uart1_pins_default: uart1-pins-default { 755 pins_rx { 756 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 757 input-enable; 758 bias-pull-up; 759 }; 760 pins_tx { 761 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 762 }; 763 pins_rts { 764 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 765 output-enable; 766 }; 767 pins_cts { 768 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 769 input-enable; 770 }; 771 }; 772 773 uart1_pins_sleep: uart1-pins-sleep { 774 pins_rx { 775 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 776 input-enable; 777 bias-pull-up; 778 }; 779 pins_tx { 780 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 781 }; 782 pins_rts { 783 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 784 output-enable; 785 }; 786 pins_cts { 787 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 788 input-enable; 789 }; 790 }; 791 792 wifi_pins_pwrseq: wifi-pins-pwrseq { 793 pins_wifi_enable { 794 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 795 output-low; 796 }; 797 }; 798 799 wifi_pins_wakeup: wifi-pins-wakeup { 800 pins_wifi_wakeup { 801 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 802 input-enable; 803 }; 804 }; 805}; 806 807&pwm0 { 808 status = "okay"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&pwm0_pin_default>; 811}; 812 813&scp { 814 status = "okay"; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&scp_pins>; 817 818 cros_ec { 819 compatible = "google,cros-ec-rpmsg"; 820 mediatek,rpmsg-name = "cros-ec-rpmsg"; 821 }; 822}; 823 824&mfg { 825 domain-supply = <&mt6358_vgpu_reg>; 826}; 827 828&soc_data { 829 status = "okay"; 830}; 831 832&spi0 { 833 pinctrl-names = "default"; 834 pinctrl-0 = <&spi0_pins>; 835 mediatek,pad-select = <0>; 836 status = "okay"; 837 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 838 839 cr50@0 { 840 compatible = "google,cr50"; 841 reg = <0>; 842 spi-max-frequency = <1000000>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&h1_int_od_l>; 845 interrupt-parent = <&pio>; 846 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 847 }; 848}; 849 850&spi1 { 851 pinctrl-names = "default"; 852 pinctrl-0 = <&spi1_pins>; 853 mediatek,pad-select = <0>; 854 status = "okay"; 855 856 w25q64dw: flash@0 { 857 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 858 reg = <0>; 859 spi-max-frequency = <25000000>; 860 }; 861}; 862 863&spi2 { 864 pinctrl-names = "default"; 865 pinctrl-0 = <&spi2_pins>; 866 mediatek,pad-select = <0>; 867 status = "okay"; 868 869 cros_ec: cros-ec@0 { 870 compatible = "google,cros-ec-spi"; 871 reg = <0>; 872 spi-max-frequency = <3000000>; 873 interrupt-parent = <&pio>; 874 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&ec_ap_int_odl>; 877 878 i2c_tunnel: i2c-tunnel { 879 compatible = "google,cros-ec-i2c-tunnel"; 880 google,remote-bus = <1>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 }; 884 885 usbc_extcon: extcon0 { 886 compatible = "google,extcon-usbc-cros-ec"; 887 google,usb-port-id = <0>; 888 }; 889 890 cbas { 891 compatible = "google,cros-cbas"; 892 }; 893 894 typec { 895 compatible = "google,cros-ec-typec"; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 usb_c0: connector@0 { 900 compatible = "usb-c-connector"; 901 reg = <0>; 902 power-role = "dual"; 903 data-role = "host"; 904 try-power-role = "sink"; 905 }; 906 }; 907 }; 908}; 909 910&spi3 { 911 pinctrl-names = "default"; 912 pinctrl-0 = <&spi3_pins>; 913 mediatek,pad-select = <0>; 914 status = "disabled"; 915}; 916 917&spi4 { 918 pinctrl-names = "default"; 919 pinctrl-0 = <&spi4_pins>; 920 mediatek,pad-select = <0>; 921 status = "disabled"; 922}; 923 924&spi5 { 925 pinctrl-names = "default"; 926 pinctrl-0 = <&spi5_pins>; 927 mediatek,pad-select = <0>; 928 status = "disabled"; 929}; 930 931&ssusb { 932 dr_mode = "host"; 933 wakeup-source; 934 vusb33-supply = <&mt6358_vusb_reg>; 935 status = "okay"; 936}; 937 938&thermal_zones { 939 tboard1 { 940 polling-delay = <1000>; /* milliseconds */ 941 polling-delay-passive = <0>; /* milliseconds */ 942 thermal-sensors = <&tboard_thermistor1>; 943 }; 944 945 tboard2 { 946 polling-delay = <1000>; /* milliseconds */ 947 polling-delay-passive = <0>; /* milliseconds */ 948 thermal-sensors = <&tboard_thermistor2>; 949 }; 950}; 951 952&u3phy { 953 status = "okay"; 954}; 955 956&uart0 { 957 pinctrl-names = "default"; 958 pinctrl-0 = <&uart0_pins_default>; 959 status = "okay"; 960}; 961 962&uart1 { 963 pinctrl-names = "default", "sleep"; 964 pinctrl-0 = <&uart1_pins_default>; 965 pinctrl-1 = <&uart1_pins_sleep>; 966 status = "okay"; 967 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 968 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 969 970 bluetooth: bluetooth { 971 pinctrl-names = "default"; 972 pinctrl-0 = <&bt_pins>; 973 status = "okay"; 974 compatible = "qcom,qca6174-bt"; 975 enable-gpios = <&pio 120 0>; 976 clocks = <&clk32k>; 977 firmware-name = "nvm_00440302_i2s.bin"; 978 }; 979}; 980 981&usb_host { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 vusb33-supply = <&mt6358_vusb_reg>; 985 status = "okay"; 986 987 hub@1 { 988 compatible = "usb5e3,610"; 989 reg = <1>; 990 }; 991}; 992 993#include <arm/cros-ec-keyboard.dtsi> 994#include <arm/cros-ec-sbs.dtsi> 995