1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <&bl_pp5000>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 gpio = <&pio 178 0>; 53 enable-active-high; 54 }; 55 56 lcd_pp3300: regulator1 { 57 compatible = "regulator-fixed"; 58 regulator-name = "lcd_pp3300"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 bl_pp5000: regulator2 { 66 compatible = "regulator-fixed"; 67 regulator-name = "bl_pp5000"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 mmc1_fixed_power: regulator3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "mmc1_power"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 }; 80 81 mmc1_fixed_io: regulator4 { 82 compatible = "regulator-fixed"; 83 regulator-name = "mmc1_io"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87 88 pp1800_alw: regulator5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp1800_alw"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <1800000>; 95 }; 96 97 pp3300_alw: regulator6 { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_alw"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges; 110 111 scp_mem_reserved: scp_mem_region { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x50000000 0 0x2900000>; 114 no-map; 115 }; 116 }; 117 118 sound: mt8183-sound { 119 mediatek,platform = <&afe>; 120 pinctrl-names = "default", 121 "aud_tdm_out_on", 122 "aud_tdm_out_off"; 123 pinctrl-0 = <&aud_pins_default>; 124 pinctrl-1 = <&aud_pins_tdm_out_on>; 125 pinctrl-2 = <&aud_pins_tdm_out_off>; 126 status = "okay"; 127 }; 128 129 btsco: bt-sco { 130 compatible = "linux,bt-sco"; 131 }; 132 133 wifi_pwrseq: wifi-pwrseq { 134 compatible = "mmc-pwrseq-simple"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&wifi_pins_pwrseq>; 137 138 /* Toggle WIFI_ENABLE to reset the chip. */ 139 reset-gpios = <&pio 119 1>; 140 }; 141 142 wifi_wakeup: wifi-wakeup { 143 compatible = "gpio-keys"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wifi_pins_wakeup>; 146 147 button-wowlan { 148 label = "Wake on WiFi"; 149 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 150 linux,code = <KEY_WAKEUP>; 151 wakeup-source; 152 }; 153 }; 154 155 tboard_thermistor1: thermal-sensor1 { 156 compatible = "generic-adc-thermal"; 157 #thermal-sensor-cells = <0>; 158 io-channels = <&auxadc 0>; 159 io-channel-names = "sensor-channel"; 160 temperature-lookup-table = < (-5000) 1553 161 0 1488 162 5000 1412 163 10000 1326 164 15000 1232 165 20000 1132 166 25000 1029 167 30000 925 168 35000 823 169 40000 726 170 45000 635 171 50000 552 172 55000 478 173 60000 411 174 65000 353 175 70000 303 176 75000 260 177 80000 222 178 85000 190 179 90000 163 180 95000 140 181 100000 121 182 105000 104 183 110000 90 184 115000 78 185 120000 67 186 125000 59>; 187 }; 188 189 tboard_thermistor2: thermal-sensor2 { 190 compatible = "generic-adc-thermal"; 191 #thermal-sensor-cells = <0>; 192 io-channels = <&auxadc 1>; 193 io-channel-names = "sensor-channel"; 194 temperature-lookup-table = < (-5000) 1553 195 0 1488 196 5000 1412 197 10000 1326 198 15000 1232 199 20000 1132 200 25000 1029 201 30000 925 202 35000 823 203 40000 726 204 45000 635 205 50000 552 206 55000 478 207 60000 411 208 65000 353 209 70000 303 210 75000 260 211 80000 222 212 85000 190 213 90000 163 214 95000 140 215 100000 121 216 105000 104 217 110000 90 218 115000 78 219 120000 67 220 125000 59>; 221 }; 222}; 223 224&auxadc { 225 status = "okay"; 226}; 227 228&cci { 229 proc-supply = <&mt6358_vproc12_reg>; 230}; 231 232&cpu0 { 233 proc-supply = <&mt6358_vproc12_reg>; 234}; 235 236&cpu1 { 237 proc-supply = <&mt6358_vproc12_reg>; 238}; 239 240&cpu2 { 241 proc-supply = <&mt6358_vproc12_reg>; 242}; 243 244&cpu3 { 245 proc-supply = <&mt6358_vproc12_reg>; 246}; 247 248&cpu4 { 249 proc-supply = <&mt6358_vproc11_reg>; 250}; 251 252&cpu5 { 253 proc-supply = <&mt6358_vproc11_reg>; 254}; 255 256&cpu6 { 257 proc-supply = <&mt6358_vproc11_reg>; 258}; 259 260&cpu7 { 261 proc-supply = <&mt6358_vproc11_reg>; 262}; 263 264&dsi0 { 265 status = "okay"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 panel: panel@0 { 269 /* compatible will be set in board dts */ 270 reg = <0>; 271 enable-gpios = <&pio 45 0>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&panel_pins_default>; 274 avdd-supply = <&ppvarn_lcd>; 275 avee-supply = <&ppvarp_lcd>; 276 pp1800-supply = <&pp1800_lcd>; 277 backlight = <&backlight_lcd0>; 278 rotation = <270>; 279 port { 280 panel_in: endpoint { 281 remote-endpoint = <&dsi_out>; 282 }; 283 }; 284 }; 285 286 ports { 287 port { 288 dsi_out: endpoint { 289 remote-endpoint = <&panel_in>; 290 }; 291 }; 292 }; 293}; 294 295&gpu { 296 mali-supply = <&mt6358_vgpu_reg>; 297}; 298 299&i2c0 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c0_pins>; 302 status = "okay"; 303 clock-frequency = <400000>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306}; 307 308&i2c1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&i2c1_pins>; 311 status = "okay"; 312 clock-frequency = <100000>; 313}; 314 315&i2c3 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c3_pins>; 318 status = "okay"; 319 clock-frequency = <100000>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322}; 323 324&i2c5 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&i2c5_pins>; 327 status = "okay"; 328 clock-frequency = <100000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331}; 332 333&i2c6 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c6_pins>; 336 status = "okay"; 337 clock-frequency = <100000>; 338}; 339 340&mipi_tx0 { 341 status = "okay"; 342}; 343 344&mmc0 { 345 status = "okay"; 346 pinctrl-names = "default", "state_uhs"; 347 pinctrl-0 = <&mmc0_pins_default>; 348 pinctrl-1 = <&mmc0_pins_uhs>; 349 bus-width = <8>; 350 max-frequency = <200000000>; 351 cap-mmc-highspeed; 352 mmc-hs200-1_8v; 353 mmc-hs400-1_8v; 354 cap-mmc-hw-reset; 355 no-sdio; 356 no-sd; 357 hs400-ds-delay = <0x12814>; 358 vmmc-supply = <&mt6358_vemc_reg>; 359 vqmmc-supply = <&mt6358_vio18_reg>; 360 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 361 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 362 non-removable; 363}; 364 365&mmc1 { 366 status = "okay"; 367 pinctrl-names = "default", "state_uhs"; 368 pinctrl-0 = <&mmc1_pins_default>; 369 pinctrl-1 = <&mmc1_pins_uhs>; 370 vmmc-supply = <&mmc1_fixed_power>; 371 vqmmc-supply = <&mmc1_fixed_io>; 372 mmc-pwrseq = <&wifi_pwrseq>; 373 bus-width = <4>; 374 max-frequency = <200000000>; 375 cap-sd-highspeed; 376 sd-uhs-sdr50; 377 sd-uhs-sdr104; 378 keep-power-in-suspend; 379 wakeup-source; 380 cap-sdio-irq; 381 non-removable; 382 no-mmc; 383 no-sd; 384 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 385 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 qca_wifi: qca-wifi@1 { 390 compatible = "qcom,ath10k"; 391 reg = <1>; 392 }; 393}; 394 395&mt6358_vdram2_reg { 396 regulator-always-on; 397}; 398 399&mt6358codec { 400 Avdd-supply = <&mt6358_vaud28_reg>; 401}; 402 403&mt6358_vgpu_reg { 404 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 405 regulator-coupled-max-spread = <100000>; 406}; 407 408&mt6358_vsim1_reg { 409 regulator-min-microvolt = <2700000>; 410 regulator-max-microvolt = <2700000>; 411}; 412 413&mt6358_vsim2_reg { 414 regulator-min-microvolt = <2700000>; 415 regulator-max-microvolt = <2700000>; 416}; 417 418&mt6358_vsram_gpu_reg { 419 regulator-coupled-with = <&mt6358_vgpu_reg>; 420 regulator-coupled-max-spread = <100000>; 421}; 422 423&pio { 424 aud_pins_default: audiopins { 425 pins_bus { 426 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 427 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 428 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 429 <PINMUX_GPIO102__FUNC_I2S2_DI>, 430 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 431 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 432 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 433 <PINMUX_GPIO91__FUNC_I2S5_DO>, 434 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 435 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 436 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 437 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 438 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 439 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 440 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 441 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 442 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 443 }; 444 }; 445 446 aud_pins_tdm_out_on: audiotdmouton { 447 pins_bus { 448 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 449 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 450 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 451 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 452 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 453 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 454 drive-strength = <MTK_DRIVE_6mA>; 455 }; 456 }; 457 458 aud_pins_tdm_out_off: audiotdmoutoff { 459 pins_bus { 460 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 461 <PINMUX_GPIO170__FUNC_GPIO170>, 462 <PINMUX_GPIO171__FUNC_GPIO171>, 463 <PINMUX_GPIO172__FUNC_GPIO172>, 464 <PINMUX_GPIO173__FUNC_GPIO173>, 465 <PINMUX_GPIO10__FUNC_GPIO10>; 466 input-enable; 467 bias-pull-down; 468 drive-strength = <MTK_DRIVE_2mA>; 469 }; 470 }; 471 472 bt_pins: bt-pins { 473 pins_bt_en { 474 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 475 output-low; 476 }; 477 }; 478 479 ec_ap_int_odl: ec_ap_int_odl { 480 pins1 { 481 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 482 input-enable; 483 bias-pull-up; 484 }; 485 }; 486 487 h1_int_od_l: h1_int_od_l { 488 pins1 { 489 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 490 input-enable; 491 }; 492 }; 493 494 i2c0_pins: i2c0 { 495 pins_bus { 496 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 497 <PINMUX_GPIO83__FUNC_SCL0>; 498 mediatek,pull-up-adv = <3>; 499 mediatek,drive-strength-adv = <00>; 500 }; 501 }; 502 503 i2c1_pins: i2c1 { 504 pins_bus { 505 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 506 <PINMUX_GPIO84__FUNC_SCL1>; 507 mediatek,pull-up-adv = <3>; 508 mediatek,drive-strength-adv = <00>; 509 }; 510 }; 511 512 i2c2_pins: i2c2 { 513 pins_bus { 514 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 515 <PINMUX_GPIO104__FUNC_SDA2>; 516 bias-disable; 517 mediatek,drive-strength-adv = <00>; 518 }; 519 }; 520 521 i2c3_pins: i2c3 { 522 pins_bus { 523 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 524 <PINMUX_GPIO51__FUNC_SDA3>; 525 mediatek,pull-up-adv = <3>; 526 mediatek,drive-strength-adv = <00>; 527 }; 528 }; 529 530 i2c4_pins: i2c4 { 531 pins_bus { 532 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 533 <PINMUX_GPIO106__FUNC_SDA4>; 534 bias-disable; 535 mediatek,drive-strength-adv = <00>; 536 }; 537 }; 538 539 i2c5_pins: i2c5 { 540 pins_bus { 541 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 542 <PINMUX_GPIO49__FUNC_SDA5>; 543 mediatek,pull-up-adv = <3>; 544 mediatek,drive-strength-adv = <00>; 545 }; 546 }; 547 548 i2c6_pins: i2c6 { 549 pins_bus { 550 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 551 <PINMUX_GPIO12__FUNC_SDA6>; 552 bias-disable; 553 }; 554 }; 555 556 mmc0_pins_default: mmc0-pins-default { 557 pins_cmd_dat { 558 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 559 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 560 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 561 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 562 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 563 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 564 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 565 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 566 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 567 input-enable; 568 drive-strength = <MTK_DRIVE_14mA>; 569 mediatek,pull-up-adv = <01>; 570 }; 571 572 pins_clk { 573 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 574 drive-strength = <MTK_DRIVE_14mA>; 575 mediatek,pull-down-adv = <10>; 576 }; 577 578 pins_rst { 579 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 580 drive-strength = <MTK_DRIVE_14mA>; 581 mediatek,pull-down-adv = <01>; 582 }; 583 }; 584 585 mmc0_pins_uhs: mmc0-pins-uhs { 586 pins_cmd_dat { 587 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 588 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 589 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 590 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 591 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 592 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 593 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 594 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 595 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 596 input-enable; 597 drive-strength = <MTK_DRIVE_14mA>; 598 mediatek,pull-up-adv = <01>; 599 }; 600 601 pins_clk { 602 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 603 drive-strength = <MTK_DRIVE_14mA>; 604 mediatek,pull-down-adv = <10>; 605 }; 606 607 pins_ds { 608 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 609 drive-strength = <MTK_DRIVE_14mA>; 610 mediatek,pull-down-adv = <10>; 611 }; 612 613 pins_rst { 614 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 615 drive-strength = <MTK_DRIVE_14mA>; 616 mediatek,pull-up-adv = <01>; 617 }; 618 }; 619 620 mmc1_pins_default: mmc1-pins-default { 621 pins_cmd_dat { 622 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 623 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 624 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 625 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 626 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 627 input-enable; 628 mediatek,pull-up-adv = <10>; 629 }; 630 631 pins_clk { 632 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 633 input-enable; 634 mediatek,pull-down-adv = <10>; 635 }; 636 }; 637 638 mmc1_pins_uhs: mmc1-pins-uhs { 639 pins_cmd_dat { 640 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 641 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 642 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 643 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 644 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 645 drive-strength = <MTK_DRIVE_6mA>; 646 input-enable; 647 mediatek,pull-up-adv = <10>; 648 }; 649 650 pins_clk { 651 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 652 drive-strength = <MTK_DRIVE_8mA>; 653 mediatek,pull-down-adv = <10>; 654 input-enable; 655 }; 656 }; 657 658 panel_pins_default: panel_pins_default { 659 panel_reset { 660 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 661 output-low; 662 bias-pull-up; 663 }; 664 }; 665 666 pwm0_pin_default: pwm0_pin_default { 667 pins1 { 668 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 669 output-high; 670 bias-pull-up; 671 }; 672 pins2 { 673 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 674 }; 675 }; 676 677 scp_pins: scp { 678 pins_scp_uart { 679 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 680 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 681 }; 682 }; 683 684 spi0_pins: spi0 { 685 pins_spi{ 686 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 687 <PINMUX_GPIO86__FUNC_GPIO86>, 688 <PINMUX_GPIO87__FUNC_SPI0_MO>, 689 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 690 bias-disable; 691 }; 692 }; 693 694 spi1_pins: spi1 { 695 pins_spi{ 696 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 697 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 698 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 699 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 700 bias-disable; 701 }; 702 }; 703 704 spi2_pins: spi2 { 705 pins_spi{ 706 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 707 <PINMUX_GPIO1__FUNC_SPI2_MO>, 708 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 709 bias-disable; 710 }; 711 pins_spi_mi { 712 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 713 mediatek,pull-down-adv = <00>; 714 }; 715 }; 716 717 spi3_pins: spi3 { 718 pins_spi{ 719 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 720 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 721 <PINMUX_GPIO23__FUNC_SPI3_MO>, 722 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 723 bias-disable; 724 }; 725 }; 726 727 spi4_pins: spi4 { 728 pins_spi{ 729 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 730 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 731 <PINMUX_GPIO19__FUNC_SPI4_MO>, 732 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 733 bias-disable; 734 }; 735 }; 736 737 spi5_pins: spi5 { 738 pins_spi{ 739 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 740 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 741 <PINMUX_GPIO15__FUNC_SPI5_MO>, 742 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 743 bias-disable; 744 }; 745 }; 746 747 uart0_pins_default: uart0-pins-default { 748 pins_rx { 749 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 750 input-enable; 751 bias-pull-up; 752 }; 753 pins_tx { 754 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 755 }; 756 }; 757 758 uart1_pins_default: uart1-pins-default { 759 pins_rx { 760 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 761 input-enable; 762 bias-pull-up; 763 }; 764 pins_tx { 765 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 766 }; 767 pins_rts { 768 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 769 output-enable; 770 }; 771 pins_cts { 772 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 773 input-enable; 774 }; 775 }; 776 777 uart1_pins_sleep: uart1-pins-sleep { 778 pins_rx { 779 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 780 input-enable; 781 bias-pull-up; 782 }; 783 pins_tx { 784 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 785 }; 786 pins_rts { 787 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 788 output-enable; 789 }; 790 pins_cts { 791 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 792 input-enable; 793 }; 794 }; 795 796 wifi_pins_pwrseq: wifi-pins-pwrseq { 797 pins_wifi_enable { 798 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 799 output-low; 800 }; 801 }; 802 803 wifi_pins_wakeup: wifi-pins-wakeup { 804 pins_wifi_wakeup { 805 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 806 input-enable; 807 }; 808 }; 809}; 810 811&pwm0 { 812 status = "okay"; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pwm0_pin_default>; 815}; 816 817&scp { 818 status = "okay"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&scp_pins>; 821 822 cros_ec { 823 compatible = "google,cros-ec-rpmsg"; 824 mediatek,rpmsg-name = "cros-ec-rpmsg"; 825 }; 826}; 827 828&mfg_async { 829 domain-supply = <&mt6358_vsram_gpu_reg>; 830}; 831 832&mfg { 833 domain-supply = <&mt6358_vgpu_reg>; 834}; 835 836&soc_data { 837 status = "okay"; 838}; 839 840&spi0 { 841 pinctrl-names = "default"; 842 pinctrl-0 = <&spi0_pins>; 843 mediatek,pad-select = <0>; 844 status = "okay"; 845 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 846 847 cr50@0 { 848 compatible = "google,cr50"; 849 reg = <0>; 850 spi-max-frequency = <1000000>; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&h1_int_od_l>; 853 interrupt-parent = <&pio>; 854 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 855 }; 856}; 857 858&spi1 { 859 pinctrl-names = "default"; 860 pinctrl-0 = <&spi1_pins>; 861 mediatek,pad-select = <0>; 862 status = "okay"; 863 864 w25q64dw: flash@0 { 865 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 866 reg = <0>; 867 spi-max-frequency = <25000000>; 868 }; 869}; 870 871&spi2 { 872 pinctrl-names = "default"; 873 pinctrl-0 = <&spi2_pins>; 874 mediatek,pad-select = <0>; 875 status = "okay"; 876 877 cros_ec: cros-ec@0 { 878 compatible = "google,cros-ec-spi"; 879 reg = <0>; 880 spi-max-frequency = <3000000>; 881 interrupt-parent = <&pio>; 882 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&ec_ap_int_odl>; 885 886 i2c_tunnel: i2c-tunnel { 887 compatible = "google,cros-ec-i2c-tunnel"; 888 google,remote-bus = <1>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 }; 892 893 usbc_extcon: extcon0 { 894 compatible = "google,extcon-usbc-cros-ec"; 895 google,usb-port-id = <0>; 896 }; 897 898 cbas { 899 compatible = "google,cros-cbas"; 900 }; 901 902 typec { 903 compatible = "google,cros-ec-typec"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 907 usb_c0: connector@0 { 908 compatible = "usb-c-connector"; 909 reg = <0>; 910 power-role = "dual"; 911 data-role = "host"; 912 try-power-role = "sink"; 913 }; 914 }; 915 }; 916}; 917 918&spi3 { 919 pinctrl-names = "default"; 920 pinctrl-0 = <&spi3_pins>; 921 mediatek,pad-select = <0>; 922 status = "disabled"; 923}; 924 925&spi4 { 926 pinctrl-names = "default"; 927 pinctrl-0 = <&spi4_pins>; 928 mediatek,pad-select = <0>; 929 status = "disabled"; 930}; 931 932&spi5 { 933 pinctrl-names = "default"; 934 pinctrl-0 = <&spi5_pins>; 935 mediatek,pad-select = <0>; 936 status = "disabled"; 937}; 938 939&ssusb { 940 dr_mode = "host"; 941 wakeup-source; 942 vusb33-supply = <&mt6358_vusb_reg>; 943 status = "okay"; 944}; 945 946&thermal_zones { 947 tboard1 { 948 polling-delay = <1000>; /* milliseconds */ 949 polling-delay-passive = <0>; /* milliseconds */ 950 thermal-sensors = <&tboard_thermistor1>; 951 }; 952 953 tboard2 { 954 polling-delay = <1000>; /* milliseconds */ 955 polling-delay-passive = <0>; /* milliseconds */ 956 thermal-sensors = <&tboard_thermistor2>; 957 }; 958}; 959 960&u3phy { 961 status = "okay"; 962}; 963 964&uart0 { 965 pinctrl-names = "default"; 966 pinctrl-0 = <&uart0_pins_default>; 967 status = "okay"; 968}; 969 970&uart1 { 971 pinctrl-names = "default", "sleep"; 972 pinctrl-0 = <&uart1_pins_default>; 973 pinctrl-1 = <&uart1_pins_sleep>; 974 status = "okay"; 975 /delete-property/ interrupts; 976 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 977 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 978 979 bluetooth: bluetooth { 980 pinctrl-names = "default"; 981 pinctrl-0 = <&bt_pins>; 982 status = "okay"; 983 compatible = "qcom,qca6174-bt"; 984 enable-gpios = <&pio 120 0>; 985 clocks = <&clk32k>; 986 firmware-name = "nvm_00440302_i2s.bin"; 987 }; 988}; 989 990&usb_host { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 vusb33-supply = <&mt6358_vusb_reg>; 994 status = "okay"; 995 996 hub@1 { 997 compatible = "usb5e3,610"; 998 reg = <1>; 999 }; 1000}; 1001 1002#include <arm/cros-ec-sbs.dtsi> 1003