1e526c9bcSBen Ho// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2e526c9bcSBen Ho/*
3e526c9bcSBen Ho * Copyright (c) 2018 MediaTek Inc.
4e526c9bcSBen Ho * Author: Ben Ho <ben.ho@mediatek.com>
5e526c9bcSBen Ho *	   Erin Lo <erin.lo@mediatek.com>
6e526c9bcSBen Ho */
7e526c9bcSBen Ho
8e526c9bcSBen Ho/dts-v1/;
9e526c9bcSBen Ho#include "mt8183.dtsi"
109f887222SHsin-Hsiung Wang#include "mt6358.dtsi"
11e526c9bcSBen Ho
12e526c9bcSBen Ho/ {
13e526c9bcSBen Ho	model = "MediaTek MT8183 evaluation board";
14e526c9bcSBen Ho	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
15e526c9bcSBen Ho
16e526c9bcSBen Ho	aliases {
17e526c9bcSBen Ho		serial0 = &uart0;
18e526c9bcSBen Ho	};
19e526c9bcSBen Ho
20e526c9bcSBen Ho	memory@40000000 {
21e526c9bcSBen Ho		device_type = "memory";
22e526c9bcSBen Ho		reg = <0 0x40000000 0 0x80000000>;
23e526c9bcSBen Ho	};
24e526c9bcSBen Ho
25e526c9bcSBen Ho	chosen {
26e526c9bcSBen Ho		stdout-path = "serial0:921600n8";
27e526c9bcSBen Ho	};
281652dbf7SEddie Huang
291652dbf7SEddie Huang	reserved-memory {
301652dbf7SEddie Huang		#address-cells = <2>;
311652dbf7SEddie Huang		#size-cells = <2>;
321652dbf7SEddie Huang		ranges;
331652dbf7SEddie Huang		scp_mem_reserved: scp_mem_region {
341652dbf7SEddie Huang			compatible = "shared-dma-pool";
351652dbf7SEddie Huang			reg = <0 0x50000000 0 0x2900000>;
361652dbf7SEddie Huang			no-map;
371652dbf7SEddie Huang		};
381652dbf7SEddie Huang	};
39e526c9bcSBen Ho};
40e526c9bcSBen Ho
41eb59b353SZhiyong Tao&auxadc {
42eb59b353SZhiyong Tao	status = "okay";
43eb59b353SZhiyong Tao};
44eb59b353SZhiyong Tao
45*a8168cebSNicolas Boichat&gpu {
46*a8168cebSNicolas Boichat	mali-supply = <&mt6358_vgpu_reg>;
47*a8168cebSNicolas Boichat	sram-supply = <&mt6358_vsram_gpu_reg>;
48*a8168cebSNicolas Boichat};
49*a8168cebSNicolas Boichat
50251137b8SQii Wang&i2c0 {
51251137b8SQii Wang	pinctrl-names = "default";
52251137b8SQii Wang	pinctrl-0 = <&i2c_pins_0>;
53251137b8SQii Wang	status = "okay";
54251137b8SQii Wang	clock-frequency = <100000>;
55251137b8SQii Wang};
56251137b8SQii Wang
57251137b8SQii Wang&i2c1 {
58251137b8SQii Wang	pinctrl-names = "default";
59251137b8SQii Wang	pinctrl-0 = <&i2c_pins_1>;
60251137b8SQii Wang	status = "okay";
61251137b8SQii Wang	clock-frequency = <100000>;
62251137b8SQii Wang};
63251137b8SQii Wang
64251137b8SQii Wang&i2c2 {
65251137b8SQii Wang	pinctrl-names = "default";
66251137b8SQii Wang	pinctrl-0 = <&i2c_pins_2>;
67251137b8SQii Wang	status = "okay";
68251137b8SQii Wang	clock-frequency = <100000>;
69251137b8SQii Wang};
70251137b8SQii Wang
71251137b8SQii Wang&i2c3 {
72251137b8SQii Wang	pinctrl-names = "default";
73251137b8SQii Wang	pinctrl-0 = <&i2c_pins_3>;
74251137b8SQii Wang	status = "okay";
75251137b8SQii Wang	clock-frequency = <100000>;
76251137b8SQii Wang};
77251137b8SQii Wang
78251137b8SQii Wang&i2c4 {
79251137b8SQii Wang	pinctrl-names = "default";
80251137b8SQii Wang	pinctrl-0 = <&i2c_pins_4>;
81251137b8SQii Wang	status = "okay";
82251137b8SQii Wang	clock-frequency = <1000000>;
83251137b8SQii Wang};
84251137b8SQii Wang
85251137b8SQii Wang&i2c5 {
86251137b8SQii Wang	pinctrl-names = "default";
87251137b8SQii Wang	pinctrl-0 = <&i2c_pins_5>;
88251137b8SQii Wang	status = "okay";
89251137b8SQii Wang	clock-frequency = <1000000>;
90251137b8SQii Wang};
91251137b8SQii Wang
925e6cdf00Sjjian zhou&mmc0 {
935e6cdf00Sjjian zhou	status = "okay";
945e6cdf00Sjjian zhou	pinctrl-names = "default", "state_uhs";
955e6cdf00Sjjian zhou	pinctrl-0 = <&mmc0_pins_default>;
965e6cdf00Sjjian zhou	pinctrl-1 = <&mmc0_pins_uhs>;
975e6cdf00Sjjian zhou	bus-width = <8>;
985e6cdf00Sjjian zhou	max-frequency = <200000000>;
995e6cdf00Sjjian zhou	cap-mmc-highspeed;
1005e6cdf00Sjjian zhou	mmc-hs200-1_8v;
1015e6cdf00Sjjian zhou	mmc-hs400-1_8v;
1025e6cdf00Sjjian zhou	cap-mmc-hw-reset;
1035e6cdf00Sjjian zhou	no-sdio;
1045e6cdf00Sjjian zhou	no-sd;
1055e6cdf00Sjjian zhou	hs400-ds-delay = <0x12814>;
1065e6cdf00Sjjian zhou	vmmc-supply = <&mt6358_vemc_reg>;
1075e6cdf00Sjjian zhou	vqmmc-supply = <&mt6358_vio18_reg>;
1085e6cdf00Sjjian zhou	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
1095e6cdf00Sjjian zhou	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
1105e6cdf00Sjjian zhou	non-removable;
1115e6cdf00Sjjian zhou};
1125e6cdf00Sjjian zhou
1135e6cdf00Sjjian zhou&mmc1 {
1145e6cdf00Sjjian zhou	status = "okay";
1155e6cdf00Sjjian zhou	pinctrl-names = "default", "state_uhs";
1165e6cdf00Sjjian zhou	pinctrl-0 = <&mmc1_pins_default>;
1175e6cdf00Sjjian zhou	pinctrl-1 = <&mmc1_pins_uhs>;
1185e6cdf00Sjjian zhou	bus-width = <4>;
1195e6cdf00Sjjian zhou	max-frequency = <200000000>;
1205e6cdf00Sjjian zhou	cap-sd-highspeed;
1215e6cdf00Sjjian zhou	sd-uhs-sdr50;
1225e6cdf00Sjjian zhou	sd-uhs-sdr104;
1235e6cdf00Sjjian zhou	cap-sdio-irq;
1245e6cdf00Sjjian zhou	no-mmc;
1255e6cdf00Sjjian zhou	no-sd;
1265e6cdf00Sjjian zhou	vmmc-supply = <&mt6358_vmch_reg>;
1275e6cdf00Sjjian zhou	vqmmc-supply = <&mt6358_vmc_reg>;
1285e6cdf00Sjjian zhou	keep-power-in-suspend;
1295e6cdf00Sjjian zhou	enable-sdio-wakeup;
1305e6cdf00Sjjian zhou	non-removable;
1315e6cdf00Sjjian zhou};
1325e6cdf00Sjjian zhou
1338e2dd0f9SErin Lo&pio {
134251137b8SQii Wang	i2c_pins_0: i2c0{
135251137b8SQii Wang		pins_i2c{
136251137b8SQii Wang			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
137251137b8SQii Wang				 <PINMUX_GPIO83__FUNC_SCL0>;
138251137b8SQii Wang			mediatek,pull-up-adv = <3>;
139251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
140251137b8SQii Wang		};
141251137b8SQii Wang	};
142251137b8SQii Wang
143251137b8SQii Wang	i2c_pins_1: i2c1{
144251137b8SQii Wang		pins_i2c{
145251137b8SQii Wang			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
146251137b8SQii Wang				 <PINMUX_GPIO84__FUNC_SCL1>;
147251137b8SQii Wang			mediatek,pull-up-adv = <3>;
148251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
149251137b8SQii Wang		};
150251137b8SQii Wang	};
151251137b8SQii Wang
152251137b8SQii Wang	i2c_pins_2: i2c2{
153251137b8SQii Wang		pins_i2c{
154251137b8SQii Wang			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
155251137b8SQii Wang				 <PINMUX_GPIO104__FUNC_SDA2>;
156251137b8SQii Wang			mediatek,pull-up-adv = <3>;
157251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
158251137b8SQii Wang		};
159251137b8SQii Wang	};
160251137b8SQii Wang
161251137b8SQii Wang	i2c_pins_3: i2c3{
162251137b8SQii Wang		pins_i2c{
163251137b8SQii Wang			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
164251137b8SQii Wang				 <PINMUX_GPIO51__FUNC_SDA3>;
165251137b8SQii Wang			mediatek,pull-up-adv = <3>;
166251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
167251137b8SQii Wang		};
168251137b8SQii Wang	};
169251137b8SQii Wang
170251137b8SQii Wang	i2c_pins_4: i2c4{
171251137b8SQii Wang		pins_i2c{
172251137b8SQii Wang			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
173251137b8SQii Wang				 <PINMUX_GPIO106__FUNC_SDA4>;
174251137b8SQii Wang			mediatek,pull-up-adv = <3>;
175251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
176251137b8SQii Wang		};
177251137b8SQii Wang	};
178251137b8SQii Wang
179251137b8SQii Wang	i2c_pins_5: i2c5{
180251137b8SQii Wang		pins_i2c{
181251137b8SQii Wang			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
182251137b8SQii Wang				 <PINMUX_GPIO49__FUNC_SDA5>;
183251137b8SQii Wang			mediatek,pull-up-adv = <3>;
184251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
185251137b8SQii Wang		};
186251137b8SQii Wang	};
187251137b8SQii Wang
1888e2dd0f9SErin Lo	spi_pins_0: spi0{
1898e2dd0f9SErin Lo		pins_spi{
1908e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
1918e2dd0f9SErin Lo				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
1928e2dd0f9SErin Lo				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
1938e2dd0f9SErin Lo				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
1948e2dd0f9SErin Lo			bias-disable;
1958e2dd0f9SErin Lo		};
1968e2dd0f9SErin Lo	};
1978e2dd0f9SErin Lo
1985e6cdf00Sjjian zhou	mmc0_pins_default: mmc0default {
1995e6cdf00Sjjian zhou		pins_cmd_dat {
2005e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
2015e6cdf00Sjjian zhou				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
2025e6cdf00Sjjian zhou				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
2035e6cdf00Sjjian zhou				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
2045e6cdf00Sjjian zhou				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
2055e6cdf00Sjjian zhou				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
2065e6cdf00Sjjian zhou				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
2075e6cdf00Sjjian zhou				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
2085e6cdf00Sjjian zhou				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
2095e6cdf00Sjjian zhou			input-enable;
2105e6cdf00Sjjian zhou			bias-pull-up;
2115e6cdf00Sjjian zhou		};
2125e6cdf00Sjjian zhou
2135e6cdf00Sjjian zhou		pins_clk {
2145e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
2155e6cdf00Sjjian zhou			bias-pull-down;
2165e6cdf00Sjjian zhou		};
2175e6cdf00Sjjian zhou
2185e6cdf00Sjjian zhou		pins_rst {
2195e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
2205e6cdf00Sjjian zhou			bias-pull-up;
2215e6cdf00Sjjian zhou		};
2225e6cdf00Sjjian zhou	};
2235e6cdf00Sjjian zhou
2244b1b8fd8SEnric Balletbo i Serra	mmc0_pins_uhs: mmc0 {
2255e6cdf00Sjjian zhou		pins_cmd_dat {
2265e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
2275e6cdf00Sjjian zhou				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
2285e6cdf00Sjjian zhou				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
2295e6cdf00Sjjian zhou				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
2305e6cdf00Sjjian zhou				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
2315e6cdf00Sjjian zhou				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
2325e6cdf00Sjjian zhou				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
2335e6cdf00Sjjian zhou				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
2345e6cdf00Sjjian zhou				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
2355e6cdf00Sjjian zhou			input-enable;
2365e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2375e6cdf00Sjjian zhou			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
2385e6cdf00Sjjian zhou		};
2395e6cdf00Sjjian zhou
2405e6cdf00Sjjian zhou		pins_clk {
2415e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
2425e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2435e6cdf00Sjjian zhou			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
2445e6cdf00Sjjian zhou		};
2455e6cdf00Sjjian zhou
2465e6cdf00Sjjian zhou		pins_ds {
2475e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
2485e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2495e6cdf00Sjjian zhou			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
2505e6cdf00Sjjian zhou		};
2515e6cdf00Sjjian zhou
2525e6cdf00Sjjian zhou		pins_rst {
2535e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
2545e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2555e6cdf00Sjjian zhou			bias-pull-up;
2565e6cdf00Sjjian zhou		};
2575e6cdf00Sjjian zhou	};
2585e6cdf00Sjjian zhou
2595e6cdf00Sjjian zhou	mmc1_pins_default: mmc1default {
2605e6cdf00Sjjian zhou		pins_cmd_dat {
2615e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
2625e6cdf00Sjjian zhou				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
2635e6cdf00Sjjian zhou				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
2645e6cdf00Sjjian zhou				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
2655e6cdf00Sjjian zhou				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
2665e6cdf00Sjjian zhou			input-enable;
2675e6cdf00Sjjian zhou			bias-pull-up;
2685e6cdf00Sjjian zhou		};
2695e6cdf00Sjjian zhou
2705e6cdf00Sjjian zhou		pins_clk {
2715e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
2725e6cdf00Sjjian zhou			input-enable;
2735e6cdf00Sjjian zhou			bias-pull-down;
2745e6cdf00Sjjian zhou		};
2755e6cdf00Sjjian zhou
2765e6cdf00Sjjian zhou		pins_pmu {
2775e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
2785e6cdf00Sjjian zhou				   <PINMUX_GPIO166__FUNC_GPIO166>;
2795e6cdf00Sjjian zhou			output-high;
2805e6cdf00Sjjian zhou		};
2815e6cdf00Sjjian zhou	};
2825e6cdf00Sjjian zhou
2834b1b8fd8SEnric Balletbo i Serra	mmc1_pins_uhs: mmc1 {
2845e6cdf00Sjjian zhou		pins_cmd_dat {
2855e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
2865e6cdf00Sjjian zhou				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
2875e6cdf00Sjjian zhou				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
2885e6cdf00Sjjian zhou				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
2895e6cdf00Sjjian zhou				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
2905e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_6mA>;
2915e6cdf00Sjjian zhou			input-enable;
2925e6cdf00Sjjian zhou			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
2935e6cdf00Sjjian zhou		};
2945e6cdf00Sjjian zhou
2955e6cdf00Sjjian zhou		pins_clk {
2965e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
2975e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_6mA>;
2985e6cdf00Sjjian zhou			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
2995e6cdf00Sjjian zhou			input-enable;
3005e6cdf00Sjjian zhou		};
3015e6cdf00Sjjian zhou	};
3025e6cdf00Sjjian zhou
3038e2dd0f9SErin Lo	spi_pins_1: spi1{
3048e2dd0f9SErin Lo		pins_spi{
3058e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
3068e2dd0f9SErin Lo				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
3078e2dd0f9SErin Lo				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
3088e2dd0f9SErin Lo				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
3098e2dd0f9SErin Lo			bias-disable;
3108e2dd0f9SErin Lo		};
3118e2dd0f9SErin Lo	};
3128e2dd0f9SErin Lo
3138e2dd0f9SErin Lo	spi_pins_2: spi2{
3148e2dd0f9SErin Lo		pins_spi{
3158e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
3168e2dd0f9SErin Lo				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
3178e2dd0f9SErin Lo				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
3188e2dd0f9SErin Lo				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
3198e2dd0f9SErin Lo			bias-disable;
3208e2dd0f9SErin Lo		};
3218e2dd0f9SErin Lo	};
3228e2dd0f9SErin Lo
3238e2dd0f9SErin Lo	spi_pins_3: spi3{
3248e2dd0f9SErin Lo		pins_spi{
3258e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
3268e2dd0f9SErin Lo				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
3278e2dd0f9SErin Lo				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
3288e2dd0f9SErin Lo				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
3298e2dd0f9SErin Lo			bias-disable;
3308e2dd0f9SErin Lo		};
3318e2dd0f9SErin Lo	};
3328e2dd0f9SErin Lo
3338e2dd0f9SErin Lo	spi_pins_4: spi4{
3348e2dd0f9SErin Lo		pins_spi{
3358e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
3368e2dd0f9SErin Lo				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
3378e2dd0f9SErin Lo				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
3388e2dd0f9SErin Lo				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
3398e2dd0f9SErin Lo			bias-disable;
3408e2dd0f9SErin Lo		};
3418e2dd0f9SErin Lo	};
3428e2dd0f9SErin Lo
3438e2dd0f9SErin Lo	spi_pins_5: spi5{
3448e2dd0f9SErin Lo		pins_spi{
3458e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
3468e2dd0f9SErin Lo				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
3478e2dd0f9SErin Lo				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
3488e2dd0f9SErin Lo				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
3498e2dd0f9SErin Lo			bias-disable;
3508e2dd0f9SErin Lo		};
3518e2dd0f9SErin Lo	};
35206ec50ecSFabien Parent
35306ec50ecSFabien Parent	pwm_pins_1: pwm1 {
35406ec50ecSFabien Parent		pins_pwm {
35506ec50ecSFabien Parent			pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
35606ec50ecSFabien Parent		};
35706ec50ecSFabien Parent	};
3588e2dd0f9SErin Lo};
3598e2dd0f9SErin Lo
3602d7ee698SHsin-Yi Wang&mfg {
3612d7ee698SHsin-Yi Wang	domain-supply = <&mt6358_vgpu_reg>;
3622d7ee698SHsin-Yi Wang};
3632d7ee698SHsin-Yi Wang
3648e2dd0f9SErin Lo&spi0 {
3658e2dd0f9SErin Lo	pinctrl-names = "default";
3668e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_0>;
3678e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3688e2dd0f9SErin Lo	status = "okay";
3698e2dd0f9SErin Lo};
3708e2dd0f9SErin Lo
3718e2dd0f9SErin Lo&spi1 {
3728e2dd0f9SErin Lo	pinctrl-names = "default";
3738e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_1>;
3748e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3758e2dd0f9SErin Lo	status = "okay";
3768e2dd0f9SErin Lo};
3778e2dd0f9SErin Lo
3788e2dd0f9SErin Lo&spi2 {
3798e2dd0f9SErin Lo	pinctrl-names = "default";
3808e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_2>;
3818e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3828e2dd0f9SErin Lo	status = "okay";
3838e2dd0f9SErin Lo};
3848e2dd0f9SErin Lo
3858e2dd0f9SErin Lo&spi3 {
3868e2dd0f9SErin Lo	pinctrl-names = "default";
3878e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_3>;
3888e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3898e2dd0f9SErin Lo	status = "okay";
3908e2dd0f9SErin Lo};
3918e2dd0f9SErin Lo
3928e2dd0f9SErin Lo&spi4 {
3938e2dd0f9SErin Lo	pinctrl-names = "default";
3948e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_4>;
3958e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3968e2dd0f9SErin Lo	status = "okay";
3978e2dd0f9SErin Lo};
3988e2dd0f9SErin Lo
3998e2dd0f9SErin Lo&spi5 {
4008e2dd0f9SErin Lo	pinctrl-names = "default";
4018e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_5>;
4028e2dd0f9SErin Lo	mediatek,pad-select = <0>;
4038e2dd0f9SErin Lo	status = "okay";
4048e2dd0f9SErin Lo
4058e2dd0f9SErin Lo};
4068e2dd0f9SErin Lo
407e526c9bcSBen Ho&uart0 {
408e526c9bcSBen Ho	status = "okay";
409e526c9bcSBen Ho};
41006ec50ecSFabien Parent
41106ec50ecSFabien Parent&pwm1 {
41206ec50ecSFabien Parent	status = "okay";
41306ec50ecSFabien Parent	pinctrl-0 = <&pwm_pins_1>;
41406ec50ecSFabien Parent	pinctrl-names = "default";
41506ec50ecSFabien Parent};
416