1e526c9bcSBen Ho// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2e526c9bcSBen Ho/* 3e526c9bcSBen Ho * Copyright (c) 2018 MediaTek Inc. 4e526c9bcSBen Ho * Author: Ben Ho <ben.ho@mediatek.com> 5e526c9bcSBen Ho * Erin Lo <erin.lo@mediatek.com> 6e526c9bcSBen Ho */ 7e526c9bcSBen Ho 8e526c9bcSBen Ho/dts-v1/; 9e526c9bcSBen Ho#include "mt8183.dtsi" 109f887222SHsin-Hsiung Wang#include "mt6358.dtsi" 11e526c9bcSBen Ho 12e526c9bcSBen Ho/ { 13e526c9bcSBen Ho model = "MediaTek MT8183 evaluation board"; 14e526c9bcSBen Ho compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; 15e526c9bcSBen Ho 16e526c9bcSBen Ho aliases { 17e526c9bcSBen Ho serial0 = &uart0; 18e526c9bcSBen Ho }; 19e526c9bcSBen Ho 20e526c9bcSBen Ho memory@40000000 { 21e526c9bcSBen Ho device_type = "memory"; 22e526c9bcSBen Ho reg = <0 0x40000000 0 0x80000000>; 23e526c9bcSBen Ho }; 24e526c9bcSBen Ho 25e526c9bcSBen Ho chosen { 26e526c9bcSBen Ho stdout-path = "serial0:921600n8"; 27e526c9bcSBen Ho }; 281652dbf7SEddie Huang 291652dbf7SEddie Huang reserved-memory { 301652dbf7SEddie Huang #address-cells = <2>; 311652dbf7SEddie Huang #size-cells = <2>; 321652dbf7SEddie Huang ranges; 331652dbf7SEddie Huang scp_mem_reserved: scp_mem_region { 341652dbf7SEddie Huang compatible = "shared-dma-pool"; 351652dbf7SEddie Huang reg = <0 0x50000000 0 0x2900000>; 361652dbf7SEddie Huang no-map; 371652dbf7SEddie Huang }; 381652dbf7SEddie Huang }; 39ff9ea5c6SFabien Parent 40ff9ea5c6SFabien Parent ntc@0 { 41ff9ea5c6SFabien Parent compatible = "murata,ncp03wf104"; 42ff9ea5c6SFabien Parent pullup-uv = <1800000>; 43ff9ea5c6SFabien Parent pullup-ohm = <390000>; 44ff9ea5c6SFabien Parent pulldown-ohm = <0>; 45ff9ea5c6SFabien Parent io-channels = <&auxadc 0>; 46ff9ea5c6SFabien Parent }; 47e526c9bcSBen Ho}; 48e526c9bcSBen Ho 49eb59b353SZhiyong Tao&auxadc { 50eb59b353SZhiyong Tao status = "okay"; 51eb59b353SZhiyong Tao}; 52eb59b353SZhiyong Tao 53a8168cebSNicolas Boichat&gpu { 54a8168cebSNicolas Boichat mali-supply = <&mt6358_vgpu_reg>; 55a8168cebSNicolas Boichat sram-supply = <&mt6358_vsram_gpu_reg>; 56a8168cebSNicolas Boichat}; 57a8168cebSNicolas Boichat 58251137b8SQii Wang&i2c0 { 59251137b8SQii Wang pinctrl-names = "default"; 60251137b8SQii Wang pinctrl-0 = <&i2c_pins_0>; 61251137b8SQii Wang status = "okay"; 62251137b8SQii Wang clock-frequency = <100000>; 63251137b8SQii Wang}; 64251137b8SQii Wang 65251137b8SQii Wang&i2c1 { 66251137b8SQii Wang pinctrl-names = "default"; 67251137b8SQii Wang pinctrl-0 = <&i2c_pins_1>; 68251137b8SQii Wang status = "okay"; 69251137b8SQii Wang clock-frequency = <100000>; 70251137b8SQii Wang}; 71251137b8SQii Wang 72251137b8SQii Wang&i2c2 { 73251137b8SQii Wang pinctrl-names = "default"; 74251137b8SQii Wang pinctrl-0 = <&i2c_pins_2>; 75251137b8SQii Wang status = "okay"; 76251137b8SQii Wang clock-frequency = <100000>; 77251137b8SQii Wang}; 78251137b8SQii Wang 79251137b8SQii Wang&i2c3 { 80251137b8SQii Wang pinctrl-names = "default"; 81251137b8SQii Wang pinctrl-0 = <&i2c_pins_3>; 82251137b8SQii Wang status = "okay"; 83251137b8SQii Wang clock-frequency = <100000>; 84251137b8SQii Wang}; 85251137b8SQii Wang 86251137b8SQii Wang&i2c4 { 87251137b8SQii Wang pinctrl-names = "default"; 88251137b8SQii Wang pinctrl-0 = <&i2c_pins_4>; 89251137b8SQii Wang status = "okay"; 90251137b8SQii Wang clock-frequency = <1000000>; 91251137b8SQii Wang}; 92251137b8SQii Wang 93251137b8SQii Wang&i2c5 { 94251137b8SQii Wang pinctrl-names = "default"; 95251137b8SQii Wang pinctrl-0 = <&i2c_pins_5>; 96251137b8SQii Wang status = "okay"; 97251137b8SQii Wang clock-frequency = <1000000>; 98251137b8SQii Wang}; 99251137b8SQii Wang 1005e6cdf00Sjjian zhou&mmc0 { 1015e6cdf00Sjjian zhou status = "okay"; 1025e6cdf00Sjjian zhou pinctrl-names = "default", "state_uhs"; 1035e6cdf00Sjjian zhou pinctrl-0 = <&mmc0_pins_default>; 1045e6cdf00Sjjian zhou pinctrl-1 = <&mmc0_pins_uhs>; 1055e6cdf00Sjjian zhou bus-width = <8>; 1065e6cdf00Sjjian zhou max-frequency = <200000000>; 1075e6cdf00Sjjian zhou cap-mmc-highspeed; 1085e6cdf00Sjjian zhou mmc-hs200-1_8v; 1095e6cdf00Sjjian zhou mmc-hs400-1_8v; 1105e6cdf00Sjjian zhou cap-mmc-hw-reset; 1115e6cdf00Sjjian zhou no-sdio; 1125e6cdf00Sjjian zhou no-sd; 1135e6cdf00Sjjian zhou hs400-ds-delay = <0x12814>; 1145e6cdf00Sjjian zhou vmmc-supply = <&mt6358_vemc_reg>; 1155e6cdf00Sjjian zhou vqmmc-supply = <&mt6358_vio18_reg>; 1165e6cdf00Sjjian zhou assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 1175e6cdf00Sjjian zhou assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 1185e6cdf00Sjjian zhou non-removable; 1195e6cdf00Sjjian zhou}; 1205e6cdf00Sjjian zhou 1215e6cdf00Sjjian zhou&mmc1 { 1225e6cdf00Sjjian zhou status = "okay"; 1235e6cdf00Sjjian zhou pinctrl-names = "default", "state_uhs"; 1245e6cdf00Sjjian zhou pinctrl-0 = <&mmc1_pins_default>; 1255e6cdf00Sjjian zhou pinctrl-1 = <&mmc1_pins_uhs>; 1265e6cdf00Sjjian zhou bus-width = <4>; 1275e6cdf00Sjjian zhou max-frequency = <200000000>; 1285e6cdf00Sjjian zhou cap-sd-highspeed; 1295e6cdf00Sjjian zhou sd-uhs-sdr50; 1305e6cdf00Sjjian zhou sd-uhs-sdr104; 1315e6cdf00Sjjian zhou cap-sdio-irq; 1325e6cdf00Sjjian zhou no-mmc; 1335e6cdf00Sjjian zhou no-sd; 1345e6cdf00Sjjian zhou vmmc-supply = <&mt6358_vmch_reg>; 1355e6cdf00Sjjian zhou vqmmc-supply = <&mt6358_vmc_reg>; 1365e6cdf00Sjjian zhou keep-power-in-suspend; 1375e6cdf00Sjjian zhou enable-sdio-wakeup; 1385e6cdf00Sjjian zhou non-removable; 1395e6cdf00Sjjian zhou}; 1405e6cdf00Sjjian zhou 1418e2dd0f9SErin Lo&pio { 142251137b8SQii Wang i2c_pins_0: i2c0{ 143251137b8SQii Wang pins_i2c{ 144251137b8SQii Wang pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 145251137b8SQii Wang <PINMUX_GPIO83__FUNC_SCL0>; 146251137b8SQii Wang mediatek,pull-up-adv = <3>; 147251137b8SQii Wang mediatek,drive-strength-adv = <00>; 148251137b8SQii Wang }; 149251137b8SQii Wang }; 150251137b8SQii Wang 151251137b8SQii Wang i2c_pins_1: i2c1{ 152251137b8SQii Wang pins_i2c{ 153251137b8SQii Wang pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 154251137b8SQii Wang <PINMUX_GPIO84__FUNC_SCL1>; 155251137b8SQii Wang mediatek,pull-up-adv = <3>; 156251137b8SQii Wang mediatek,drive-strength-adv = <00>; 157251137b8SQii Wang }; 158251137b8SQii Wang }; 159251137b8SQii Wang 160251137b8SQii Wang i2c_pins_2: i2c2{ 161251137b8SQii Wang pins_i2c{ 162251137b8SQii Wang pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 163251137b8SQii Wang <PINMUX_GPIO104__FUNC_SDA2>; 164251137b8SQii Wang mediatek,pull-up-adv = <3>; 165251137b8SQii Wang mediatek,drive-strength-adv = <00>; 166251137b8SQii Wang }; 167251137b8SQii Wang }; 168251137b8SQii Wang 169251137b8SQii Wang i2c_pins_3: i2c3{ 170251137b8SQii Wang pins_i2c{ 171251137b8SQii Wang pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 172251137b8SQii Wang <PINMUX_GPIO51__FUNC_SDA3>; 173251137b8SQii Wang mediatek,pull-up-adv = <3>; 174251137b8SQii Wang mediatek,drive-strength-adv = <00>; 175251137b8SQii Wang }; 176251137b8SQii Wang }; 177251137b8SQii Wang 178251137b8SQii Wang i2c_pins_4: i2c4{ 179251137b8SQii Wang pins_i2c{ 180251137b8SQii Wang pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 181251137b8SQii Wang <PINMUX_GPIO106__FUNC_SDA4>; 182251137b8SQii Wang mediatek,pull-up-adv = <3>; 183251137b8SQii Wang mediatek,drive-strength-adv = <00>; 184251137b8SQii Wang }; 185251137b8SQii Wang }; 186251137b8SQii Wang 187251137b8SQii Wang i2c_pins_5: i2c5{ 188251137b8SQii Wang pins_i2c{ 189251137b8SQii Wang pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 190251137b8SQii Wang <PINMUX_GPIO49__FUNC_SDA5>; 191251137b8SQii Wang mediatek,pull-up-adv = <3>; 192251137b8SQii Wang mediatek,drive-strength-adv = <00>; 193251137b8SQii Wang }; 194251137b8SQii Wang }; 195251137b8SQii Wang 1968e2dd0f9SErin Lo spi_pins_0: spi0{ 1978e2dd0f9SErin Lo pins_spi{ 1988e2dd0f9SErin Lo pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 1998e2dd0f9SErin Lo <PINMUX_GPIO86__FUNC_SPI0_CSB>, 2008e2dd0f9SErin Lo <PINMUX_GPIO87__FUNC_SPI0_MO>, 2018e2dd0f9SErin Lo <PINMUX_GPIO88__FUNC_SPI0_CLK>; 2028e2dd0f9SErin Lo bias-disable; 2038e2dd0f9SErin Lo }; 2048e2dd0f9SErin Lo }; 2058e2dd0f9SErin Lo 2065e6cdf00Sjjian zhou mmc0_pins_default: mmc0default { 2075e6cdf00Sjjian zhou pins_cmd_dat { 2085e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 2095e6cdf00Sjjian zhou <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 2105e6cdf00Sjjian zhou <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 2115e6cdf00Sjjian zhou <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 2125e6cdf00Sjjian zhou <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 2135e6cdf00Sjjian zhou <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 2145e6cdf00Sjjian zhou <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 2155e6cdf00Sjjian zhou <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 2165e6cdf00Sjjian zhou <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 2175e6cdf00Sjjian zhou input-enable; 2185e6cdf00Sjjian zhou bias-pull-up; 2195e6cdf00Sjjian zhou }; 2205e6cdf00Sjjian zhou 2215e6cdf00Sjjian zhou pins_clk { 2225e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 2235e6cdf00Sjjian zhou bias-pull-down; 2245e6cdf00Sjjian zhou }; 2255e6cdf00Sjjian zhou 2265e6cdf00Sjjian zhou pins_rst { 2275e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 2285e6cdf00Sjjian zhou bias-pull-up; 2295e6cdf00Sjjian zhou }; 2305e6cdf00Sjjian zhou }; 2315e6cdf00Sjjian zhou 2324b1b8fd8SEnric Balletbo i Serra mmc0_pins_uhs: mmc0 { 2335e6cdf00Sjjian zhou pins_cmd_dat { 2345e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 2355e6cdf00Sjjian zhou <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 2365e6cdf00Sjjian zhou <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 2375e6cdf00Sjjian zhou <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 2385e6cdf00Sjjian zhou <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 2395e6cdf00Sjjian zhou <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 2405e6cdf00Sjjian zhou <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 2415e6cdf00Sjjian zhou <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 2425e6cdf00Sjjian zhou <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 2435e6cdf00Sjjian zhou input-enable; 2445e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2455e6cdf00Sjjian zhou bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 2465e6cdf00Sjjian zhou }; 2475e6cdf00Sjjian zhou 2485e6cdf00Sjjian zhou pins_clk { 2495e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 2505e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2515e6cdf00Sjjian zhou bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 2525e6cdf00Sjjian zhou }; 2535e6cdf00Sjjian zhou 2545e6cdf00Sjjian zhou pins_ds { 2555e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 2565e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2575e6cdf00Sjjian zhou bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 2585e6cdf00Sjjian zhou }; 2595e6cdf00Sjjian zhou 2605e6cdf00Sjjian zhou pins_rst { 2615e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 2625e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2635e6cdf00Sjjian zhou bias-pull-up; 2645e6cdf00Sjjian zhou }; 2655e6cdf00Sjjian zhou }; 2665e6cdf00Sjjian zhou 2675e6cdf00Sjjian zhou mmc1_pins_default: mmc1default { 2685e6cdf00Sjjian zhou pins_cmd_dat { 2695e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 2705e6cdf00Sjjian zhou <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 2715e6cdf00Sjjian zhou <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 2725e6cdf00Sjjian zhou <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 2735e6cdf00Sjjian zhou <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 2745e6cdf00Sjjian zhou input-enable; 2755e6cdf00Sjjian zhou bias-pull-up; 2765e6cdf00Sjjian zhou }; 2775e6cdf00Sjjian zhou 2785e6cdf00Sjjian zhou pins_clk { 2795e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 2805e6cdf00Sjjian zhou input-enable; 2815e6cdf00Sjjian zhou bias-pull-down; 2825e6cdf00Sjjian zhou }; 2835e6cdf00Sjjian zhou 2845e6cdf00Sjjian zhou pins_pmu { 2855e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, 2865e6cdf00Sjjian zhou <PINMUX_GPIO166__FUNC_GPIO166>; 2875e6cdf00Sjjian zhou output-high; 2885e6cdf00Sjjian zhou }; 2895e6cdf00Sjjian zhou }; 2905e6cdf00Sjjian zhou 2914b1b8fd8SEnric Balletbo i Serra mmc1_pins_uhs: mmc1 { 2925e6cdf00Sjjian zhou pins_cmd_dat { 2935e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 2945e6cdf00Sjjian zhou <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 2955e6cdf00Sjjian zhou <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 2965e6cdf00Sjjian zhou <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 2975e6cdf00Sjjian zhou <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 2985e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_6mA>; 2995e6cdf00Sjjian zhou input-enable; 3005e6cdf00Sjjian zhou bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 3015e6cdf00Sjjian zhou }; 3025e6cdf00Sjjian zhou 3035e6cdf00Sjjian zhou pins_clk { 3045e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 3055e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_6mA>; 3065e6cdf00Sjjian zhou bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 3075e6cdf00Sjjian zhou input-enable; 3085e6cdf00Sjjian zhou }; 3095e6cdf00Sjjian zhou }; 3105e6cdf00Sjjian zhou 3118e2dd0f9SErin Lo spi_pins_1: spi1{ 3128e2dd0f9SErin Lo pins_spi{ 3138e2dd0f9SErin Lo pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 3148e2dd0f9SErin Lo <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 3158e2dd0f9SErin Lo <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 3168e2dd0f9SErin Lo <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 3178e2dd0f9SErin Lo bias-disable; 3188e2dd0f9SErin Lo }; 3198e2dd0f9SErin Lo }; 3208e2dd0f9SErin Lo 3218e2dd0f9SErin Lo spi_pins_2: spi2{ 3228e2dd0f9SErin Lo pins_spi{ 3238e2dd0f9SErin Lo pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 3248e2dd0f9SErin Lo <PINMUX_GPIO1__FUNC_SPI2_MO>, 3258e2dd0f9SErin Lo <PINMUX_GPIO2__FUNC_SPI2_CLK>, 3268e2dd0f9SErin Lo <PINMUX_GPIO94__FUNC_SPI2_MI>; 3278e2dd0f9SErin Lo bias-disable; 3288e2dd0f9SErin Lo }; 3298e2dd0f9SErin Lo }; 3308e2dd0f9SErin Lo 3318e2dd0f9SErin Lo spi_pins_3: spi3{ 3328e2dd0f9SErin Lo pins_spi{ 3338e2dd0f9SErin Lo pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 3348e2dd0f9SErin Lo <PINMUX_GPIO22__FUNC_SPI3_CSB>, 3358e2dd0f9SErin Lo <PINMUX_GPIO23__FUNC_SPI3_MO>, 3368e2dd0f9SErin Lo <PINMUX_GPIO24__FUNC_SPI3_CLK>; 3378e2dd0f9SErin Lo bias-disable; 3388e2dd0f9SErin Lo }; 3398e2dd0f9SErin Lo }; 3408e2dd0f9SErin Lo 3418e2dd0f9SErin Lo spi_pins_4: spi4{ 3428e2dd0f9SErin Lo pins_spi{ 3438e2dd0f9SErin Lo pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 3448e2dd0f9SErin Lo <PINMUX_GPIO18__FUNC_SPI4_CSB>, 3458e2dd0f9SErin Lo <PINMUX_GPIO19__FUNC_SPI4_MO>, 3468e2dd0f9SErin Lo <PINMUX_GPIO20__FUNC_SPI4_CLK>; 3478e2dd0f9SErin Lo bias-disable; 3488e2dd0f9SErin Lo }; 3498e2dd0f9SErin Lo }; 3508e2dd0f9SErin Lo 3518e2dd0f9SErin Lo spi_pins_5: spi5{ 3528e2dd0f9SErin Lo pins_spi{ 3538e2dd0f9SErin Lo pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 3548e2dd0f9SErin Lo <PINMUX_GPIO14__FUNC_SPI5_CSB>, 3558e2dd0f9SErin Lo <PINMUX_GPIO15__FUNC_SPI5_MO>, 3568e2dd0f9SErin Lo <PINMUX_GPIO16__FUNC_SPI5_CLK>; 3578e2dd0f9SErin Lo bias-disable; 3588e2dd0f9SErin Lo }; 3598e2dd0f9SErin Lo }; 36006ec50ecSFabien Parent 36106ec50ecSFabien Parent pwm_pins_1: pwm1 { 36206ec50ecSFabien Parent pins_pwm { 36306ec50ecSFabien Parent pinmux = <PINMUX_GPIO90__FUNC_PWM_A>; 36406ec50ecSFabien Parent }; 36506ec50ecSFabien Parent }; 3668e2dd0f9SErin Lo}; 3678e2dd0f9SErin Lo 3682d7ee698SHsin-Yi Wang&mfg { 3692d7ee698SHsin-Yi Wang domain-supply = <&mt6358_vgpu_reg>; 3702d7ee698SHsin-Yi Wang}; 3712d7ee698SHsin-Yi Wang 3728e2dd0f9SErin Lo&spi0 { 3738e2dd0f9SErin Lo pinctrl-names = "default"; 3748e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_0>; 3758e2dd0f9SErin Lo mediatek,pad-select = <0>; 3768e2dd0f9SErin Lo status = "okay"; 3778e2dd0f9SErin Lo}; 3788e2dd0f9SErin Lo 3798e2dd0f9SErin Lo&spi1 { 3808e2dd0f9SErin Lo pinctrl-names = "default"; 3818e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_1>; 3828e2dd0f9SErin Lo mediatek,pad-select = <0>; 3838e2dd0f9SErin Lo status = "okay"; 3848e2dd0f9SErin Lo}; 3858e2dd0f9SErin Lo 3868e2dd0f9SErin Lo&spi2 { 3878e2dd0f9SErin Lo pinctrl-names = "default"; 3888e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_2>; 3898e2dd0f9SErin Lo mediatek,pad-select = <0>; 3908e2dd0f9SErin Lo status = "okay"; 3918e2dd0f9SErin Lo}; 3928e2dd0f9SErin Lo 3938e2dd0f9SErin Lo&spi3 { 3948e2dd0f9SErin Lo pinctrl-names = "default"; 3958e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_3>; 3968e2dd0f9SErin Lo mediatek,pad-select = <0>; 3978e2dd0f9SErin Lo status = "okay"; 3988e2dd0f9SErin Lo}; 3998e2dd0f9SErin Lo 4008e2dd0f9SErin Lo&spi4 { 4018e2dd0f9SErin Lo pinctrl-names = "default"; 4028e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_4>; 4038e2dd0f9SErin Lo mediatek,pad-select = <0>; 4048e2dd0f9SErin Lo status = "okay"; 4058e2dd0f9SErin Lo}; 4068e2dd0f9SErin Lo 4078e2dd0f9SErin Lo&spi5 { 4088e2dd0f9SErin Lo pinctrl-names = "default"; 4098e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_5>; 4108e2dd0f9SErin Lo mediatek,pad-select = <0>; 4118e2dd0f9SErin Lo status = "okay"; 4128e2dd0f9SErin Lo 4138e2dd0f9SErin Lo}; 4148e2dd0f9SErin Lo 415*95eacb24SRex-BC Chen&cpu0 { 416*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc12_reg>; 417*95eacb24SRex-BC Chen}; 418*95eacb24SRex-BC Chen 419*95eacb24SRex-BC Chen&cpu1 { 420*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc12_reg>; 421*95eacb24SRex-BC Chen}; 422*95eacb24SRex-BC Chen 423*95eacb24SRex-BC Chen&cpu2 { 424*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc12_reg>; 425*95eacb24SRex-BC Chen}; 426*95eacb24SRex-BC Chen 427*95eacb24SRex-BC Chen&cpu3 { 428*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc12_reg>; 429*95eacb24SRex-BC Chen}; 430*95eacb24SRex-BC Chen 431*95eacb24SRex-BC Chen&cpu4 { 432*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc11_reg>; 433*95eacb24SRex-BC Chen}; 434*95eacb24SRex-BC Chen 435*95eacb24SRex-BC Chen&cpu5 { 436*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc11_reg>; 437*95eacb24SRex-BC Chen}; 438*95eacb24SRex-BC Chen 439*95eacb24SRex-BC Chen&cpu6 { 440*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc11_reg>; 441*95eacb24SRex-BC Chen}; 442*95eacb24SRex-BC Chen 443*95eacb24SRex-BC Chen&cpu7 { 444*95eacb24SRex-BC Chen proc-supply = <&mt6358_vproc11_reg>; 445*95eacb24SRex-BC Chen}; 446*95eacb24SRex-BC Chen 447e526c9bcSBen Ho&uart0 { 448e526c9bcSBen Ho status = "okay"; 449e526c9bcSBen Ho}; 45006ec50ecSFabien Parent 45106ec50ecSFabien Parent&pwm1 { 45206ec50ecSFabien Parent status = "okay"; 45306ec50ecSFabien Parent pinctrl-0 = <&pwm_pins_1>; 45406ec50ecSFabien Parent pinctrl-names = "default"; 45506ec50ecSFabien Parent}; 456