1e526c9bcSBen Ho// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2e526c9bcSBen Ho/* 3e526c9bcSBen Ho * Copyright (c) 2018 MediaTek Inc. 4e526c9bcSBen Ho * Author: Ben Ho <ben.ho@mediatek.com> 5e526c9bcSBen Ho * Erin Lo <erin.lo@mediatek.com> 6e526c9bcSBen Ho */ 7e526c9bcSBen Ho 8e526c9bcSBen Ho/dts-v1/; 9e526c9bcSBen Ho#include "mt8183.dtsi" 109f887222SHsin-Hsiung Wang#include "mt6358.dtsi" 11e526c9bcSBen Ho 12e526c9bcSBen Ho/ { 13e526c9bcSBen Ho model = "MediaTek MT8183 evaluation board"; 14e526c9bcSBen Ho compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; 15e526c9bcSBen Ho 16e526c9bcSBen Ho aliases { 17e526c9bcSBen Ho serial0 = &uart0; 18e526c9bcSBen Ho }; 19e526c9bcSBen Ho 20e526c9bcSBen Ho memory@40000000 { 21e526c9bcSBen Ho device_type = "memory"; 22e526c9bcSBen Ho reg = <0 0x40000000 0 0x80000000>; 23e526c9bcSBen Ho }; 24e526c9bcSBen Ho 25e526c9bcSBen Ho chosen { 26e526c9bcSBen Ho stdout-path = "serial0:921600n8"; 27e526c9bcSBen Ho }; 28e526c9bcSBen Ho}; 29e526c9bcSBen Ho 30eb59b353SZhiyong Tao&auxadc { 31eb59b353SZhiyong Tao status = "okay"; 32eb59b353SZhiyong Tao}; 33eb59b353SZhiyong Tao 34251137b8SQii Wang&i2c0 { 35251137b8SQii Wang pinctrl-names = "default"; 36251137b8SQii Wang pinctrl-0 = <&i2c_pins_0>; 37251137b8SQii Wang status = "okay"; 38251137b8SQii Wang clock-frequency = <100000>; 39251137b8SQii Wang}; 40251137b8SQii Wang 41251137b8SQii Wang&i2c1 { 42251137b8SQii Wang pinctrl-names = "default"; 43251137b8SQii Wang pinctrl-0 = <&i2c_pins_1>; 44251137b8SQii Wang status = "okay"; 45251137b8SQii Wang clock-frequency = <100000>; 46251137b8SQii Wang}; 47251137b8SQii Wang 48251137b8SQii Wang&i2c2 { 49251137b8SQii Wang pinctrl-names = "default"; 50251137b8SQii Wang pinctrl-0 = <&i2c_pins_2>; 51251137b8SQii Wang status = "okay"; 52251137b8SQii Wang clock-frequency = <100000>; 53251137b8SQii Wang}; 54251137b8SQii Wang 55251137b8SQii Wang&i2c3 { 56251137b8SQii Wang pinctrl-names = "default"; 57251137b8SQii Wang pinctrl-0 = <&i2c_pins_3>; 58251137b8SQii Wang status = "okay"; 59251137b8SQii Wang clock-frequency = <100000>; 60251137b8SQii Wang}; 61251137b8SQii Wang 62251137b8SQii Wang&i2c4 { 63251137b8SQii Wang pinctrl-names = "default"; 64251137b8SQii Wang pinctrl-0 = <&i2c_pins_4>; 65251137b8SQii Wang status = "okay"; 66251137b8SQii Wang clock-frequency = <1000000>; 67251137b8SQii Wang}; 68251137b8SQii Wang 69251137b8SQii Wang&i2c5 { 70251137b8SQii Wang pinctrl-names = "default"; 71251137b8SQii Wang pinctrl-0 = <&i2c_pins_5>; 72251137b8SQii Wang status = "okay"; 73251137b8SQii Wang clock-frequency = <1000000>; 74251137b8SQii Wang}; 75251137b8SQii Wang 765e6cdf00Sjjian zhou&mmc0 { 775e6cdf00Sjjian zhou status = "okay"; 785e6cdf00Sjjian zhou pinctrl-names = "default", "state_uhs"; 795e6cdf00Sjjian zhou pinctrl-0 = <&mmc0_pins_default>; 805e6cdf00Sjjian zhou pinctrl-1 = <&mmc0_pins_uhs>; 815e6cdf00Sjjian zhou bus-width = <8>; 825e6cdf00Sjjian zhou max-frequency = <200000000>; 835e6cdf00Sjjian zhou cap-mmc-highspeed; 845e6cdf00Sjjian zhou mmc-hs200-1_8v; 855e6cdf00Sjjian zhou mmc-hs400-1_8v; 865e6cdf00Sjjian zhou cap-mmc-hw-reset; 875e6cdf00Sjjian zhou no-sdio; 885e6cdf00Sjjian zhou no-sd; 895e6cdf00Sjjian zhou hs400-ds-delay = <0x12814>; 905e6cdf00Sjjian zhou vmmc-supply = <&mt6358_vemc_reg>; 915e6cdf00Sjjian zhou vqmmc-supply = <&mt6358_vio18_reg>; 925e6cdf00Sjjian zhou assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 935e6cdf00Sjjian zhou assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 945e6cdf00Sjjian zhou non-removable; 955e6cdf00Sjjian zhou}; 965e6cdf00Sjjian zhou 975e6cdf00Sjjian zhou&mmc1 { 985e6cdf00Sjjian zhou status = "okay"; 995e6cdf00Sjjian zhou pinctrl-names = "default", "state_uhs"; 1005e6cdf00Sjjian zhou pinctrl-0 = <&mmc1_pins_default>; 1015e6cdf00Sjjian zhou pinctrl-1 = <&mmc1_pins_uhs>; 1025e6cdf00Sjjian zhou bus-width = <4>; 1035e6cdf00Sjjian zhou max-frequency = <200000000>; 1045e6cdf00Sjjian zhou cap-sd-highspeed; 1055e6cdf00Sjjian zhou sd-uhs-sdr50; 1065e6cdf00Sjjian zhou sd-uhs-sdr104; 1075e6cdf00Sjjian zhou cap-sdio-irq; 1085e6cdf00Sjjian zhou no-mmc; 1095e6cdf00Sjjian zhou no-sd; 1105e6cdf00Sjjian zhou vmmc-supply = <&mt6358_vmch_reg>; 1115e6cdf00Sjjian zhou vqmmc-supply = <&mt6358_vmc_reg>; 1125e6cdf00Sjjian zhou keep-power-in-suspend; 1135e6cdf00Sjjian zhou enable-sdio-wakeup; 1145e6cdf00Sjjian zhou non-removable; 1155e6cdf00Sjjian zhou}; 1165e6cdf00Sjjian zhou 1178e2dd0f9SErin Lo&pio { 118251137b8SQii Wang i2c_pins_0: i2c0{ 119251137b8SQii Wang pins_i2c{ 120251137b8SQii Wang pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 121251137b8SQii Wang <PINMUX_GPIO83__FUNC_SCL0>; 122251137b8SQii Wang mediatek,pull-up-adv = <3>; 123251137b8SQii Wang mediatek,drive-strength-adv = <00>; 124251137b8SQii Wang }; 125251137b8SQii Wang }; 126251137b8SQii Wang 127251137b8SQii Wang i2c_pins_1: i2c1{ 128251137b8SQii Wang pins_i2c{ 129251137b8SQii Wang pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 130251137b8SQii Wang <PINMUX_GPIO84__FUNC_SCL1>; 131251137b8SQii Wang mediatek,pull-up-adv = <3>; 132251137b8SQii Wang mediatek,drive-strength-adv = <00>; 133251137b8SQii Wang }; 134251137b8SQii Wang }; 135251137b8SQii Wang 136251137b8SQii Wang i2c_pins_2: i2c2{ 137251137b8SQii Wang pins_i2c{ 138251137b8SQii Wang pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 139251137b8SQii Wang <PINMUX_GPIO104__FUNC_SDA2>; 140251137b8SQii Wang mediatek,pull-up-adv = <3>; 141251137b8SQii Wang mediatek,drive-strength-adv = <00>; 142251137b8SQii Wang }; 143251137b8SQii Wang }; 144251137b8SQii Wang 145251137b8SQii Wang i2c_pins_3: i2c3{ 146251137b8SQii Wang pins_i2c{ 147251137b8SQii Wang pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 148251137b8SQii Wang <PINMUX_GPIO51__FUNC_SDA3>; 149251137b8SQii Wang mediatek,pull-up-adv = <3>; 150251137b8SQii Wang mediatek,drive-strength-adv = <00>; 151251137b8SQii Wang }; 152251137b8SQii Wang }; 153251137b8SQii Wang 154251137b8SQii Wang i2c_pins_4: i2c4{ 155251137b8SQii Wang pins_i2c{ 156251137b8SQii Wang pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 157251137b8SQii Wang <PINMUX_GPIO106__FUNC_SDA4>; 158251137b8SQii Wang mediatek,pull-up-adv = <3>; 159251137b8SQii Wang mediatek,drive-strength-adv = <00>; 160251137b8SQii Wang }; 161251137b8SQii Wang }; 162251137b8SQii Wang 163251137b8SQii Wang i2c_pins_5: i2c5{ 164251137b8SQii Wang pins_i2c{ 165251137b8SQii Wang pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 166251137b8SQii Wang <PINMUX_GPIO49__FUNC_SDA5>; 167251137b8SQii Wang mediatek,pull-up-adv = <3>; 168251137b8SQii Wang mediatek,drive-strength-adv = <00>; 169251137b8SQii Wang }; 170251137b8SQii Wang }; 171251137b8SQii Wang 1728e2dd0f9SErin Lo spi_pins_0: spi0{ 1738e2dd0f9SErin Lo pins_spi{ 1748e2dd0f9SErin Lo pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 1758e2dd0f9SErin Lo <PINMUX_GPIO86__FUNC_SPI0_CSB>, 1768e2dd0f9SErin Lo <PINMUX_GPIO87__FUNC_SPI0_MO>, 1778e2dd0f9SErin Lo <PINMUX_GPIO88__FUNC_SPI0_CLK>; 1788e2dd0f9SErin Lo bias-disable; 1798e2dd0f9SErin Lo }; 1808e2dd0f9SErin Lo }; 1818e2dd0f9SErin Lo 1825e6cdf00Sjjian zhou mmc0_pins_default: mmc0default { 1835e6cdf00Sjjian zhou pins_cmd_dat { 1845e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 1855e6cdf00Sjjian zhou <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 1865e6cdf00Sjjian zhou <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 1875e6cdf00Sjjian zhou <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 1885e6cdf00Sjjian zhou <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 1895e6cdf00Sjjian zhou <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 1905e6cdf00Sjjian zhou <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 1915e6cdf00Sjjian zhou <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 1925e6cdf00Sjjian zhou <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 1935e6cdf00Sjjian zhou input-enable; 1945e6cdf00Sjjian zhou bias-pull-up; 1955e6cdf00Sjjian zhou }; 1965e6cdf00Sjjian zhou 1975e6cdf00Sjjian zhou pins_clk { 1985e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 1995e6cdf00Sjjian zhou bias-pull-down; 2005e6cdf00Sjjian zhou }; 2015e6cdf00Sjjian zhou 2025e6cdf00Sjjian zhou pins_rst { 2035e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 2045e6cdf00Sjjian zhou bias-pull-up; 2055e6cdf00Sjjian zhou }; 2065e6cdf00Sjjian zhou }; 2075e6cdf00Sjjian zhou 2084b1b8fd8SEnric Balletbo i Serra mmc0_pins_uhs: mmc0 { 2095e6cdf00Sjjian zhou pins_cmd_dat { 2105e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 2115e6cdf00Sjjian zhou <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 2125e6cdf00Sjjian zhou <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 2135e6cdf00Sjjian zhou <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 2145e6cdf00Sjjian zhou <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 2155e6cdf00Sjjian zhou <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 2165e6cdf00Sjjian zhou <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 2175e6cdf00Sjjian zhou <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 2185e6cdf00Sjjian zhou <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 2195e6cdf00Sjjian zhou input-enable; 2205e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2215e6cdf00Sjjian zhou bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 2225e6cdf00Sjjian zhou }; 2235e6cdf00Sjjian zhou 2245e6cdf00Sjjian zhou pins_clk { 2255e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 2265e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2275e6cdf00Sjjian zhou bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 2285e6cdf00Sjjian zhou }; 2295e6cdf00Sjjian zhou 2305e6cdf00Sjjian zhou pins_ds { 2315e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 2325e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2335e6cdf00Sjjian zhou bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 2345e6cdf00Sjjian zhou }; 2355e6cdf00Sjjian zhou 2365e6cdf00Sjjian zhou pins_rst { 2375e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 2385e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_10mA>; 2395e6cdf00Sjjian zhou bias-pull-up; 2405e6cdf00Sjjian zhou }; 2415e6cdf00Sjjian zhou }; 2425e6cdf00Sjjian zhou 2435e6cdf00Sjjian zhou mmc1_pins_default: mmc1default { 2445e6cdf00Sjjian zhou pins_cmd_dat { 2455e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 2465e6cdf00Sjjian zhou <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 2475e6cdf00Sjjian zhou <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 2485e6cdf00Sjjian zhou <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 2495e6cdf00Sjjian zhou <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 2505e6cdf00Sjjian zhou input-enable; 2515e6cdf00Sjjian zhou bias-pull-up; 2525e6cdf00Sjjian zhou }; 2535e6cdf00Sjjian zhou 2545e6cdf00Sjjian zhou pins_clk { 2555e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 2565e6cdf00Sjjian zhou input-enable; 2575e6cdf00Sjjian zhou bias-pull-down; 2585e6cdf00Sjjian zhou }; 2595e6cdf00Sjjian zhou 2605e6cdf00Sjjian zhou pins_pmu { 2615e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, 2625e6cdf00Sjjian zhou <PINMUX_GPIO166__FUNC_GPIO166>; 2635e6cdf00Sjjian zhou output-high; 2645e6cdf00Sjjian zhou }; 2655e6cdf00Sjjian zhou }; 2665e6cdf00Sjjian zhou 2674b1b8fd8SEnric Balletbo i Serra mmc1_pins_uhs: mmc1 { 2685e6cdf00Sjjian zhou pins_cmd_dat { 2695e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 2705e6cdf00Sjjian zhou <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 2715e6cdf00Sjjian zhou <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 2725e6cdf00Sjjian zhou <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 2735e6cdf00Sjjian zhou <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 2745e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_6mA>; 2755e6cdf00Sjjian zhou input-enable; 2765e6cdf00Sjjian zhou bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 2775e6cdf00Sjjian zhou }; 2785e6cdf00Sjjian zhou 2795e6cdf00Sjjian zhou pins_clk { 2805e6cdf00Sjjian zhou pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 2815e6cdf00Sjjian zhou drive-strength = <MTK_DRIVE_6mA>; 2825e6cdf00Sjjian zhou bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 2835e6cdf00Sjjian zhou input-enable; 2845e6cdf00Sjjian zhou }; 2855e6cdf00Sjjian zhou }; 2865e6cdf00Sjjian zhou 2878e2dd0f9SErin Lo spi_pins_1: spi1{ 2888e2dd0f9SErin Lo pins_spi{ 2898e2dd0f9SErin Lo pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 2908e2dd0f9SErin Lo <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 2918e2dd0f9SErin Lo <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 2928e2dd0f9SErin Lo <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 2938e2dd0f9SErin Lo bias-disable; 2948e2dd0f9SErin Lo }; 2958e2dd0f9SErin Lo }; 2968e2dd0f9SErin Lo 2978e2dd0f9SErin Lo spi_pins_2: spi2{ 2988e2dd0f9SErin Lo pins_spi{ 2998e2dd0f9SErin Lo pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 3008e2dd0f9SErin Lo <PINMUX_GPIO1__FUNC_SPI2_MO>, 3018e2dd0f9SErin Lo <PINMUX_GPIO2__FUNC_SPI2_CLK>, 3028e2dd0f9SErin Lo <PINMUX_GPIO94__FUNC_SPI2_MI>; 3038e2dd0f9SErin Lo bias-disable; 3048e2dd0f9SErin Lo }; 3058e2dd0f9SErin Lo }; 3068e2dd0f9SErin Lo 3078e2dd0f9SErin Lo spi_pins_3: spi3{ 3088e2dd0f9SErin Lo pins_spi{ 3098e2dd0f9SErin Lo pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 3108e2dd0f9SErin Lo <PINMUX_GPIO22__FUNC_SPI3_CSB>, 3118e2dd0f9SErin Lo <PINMUX_GPIO23__FUNC_SPI3_MO>, 3128e2dd0f9SErin Lo <PINMUX_GPIO24__FUNC_SPI3_CLK>; 3138e2dd0f9SErin Lo bias-disable; 3148e2dd0f9SErin Lo }; 3158e2dd0f9SErin Lo }; 3168e2dd0f9SErin Lo 3178e2dd0f9SErin Lo spi_pins_4: spi4{ 3188e2dd0f9SErin Lo pins_spi{ 3198e2dd0f9SErin Lo pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 3208e2dd0f9SErin Lo <PINMUX_GPIO18__FUNC_SPI4_CSB>, 3218e2dd0f9SErin Lo <PINMUX_GPIO19__FUNC_SPI4_MO>, 3228e2dd0f9SErin Lo <PINMUX_GPIO20__FUNC_SPI4_CLK>; 3238e2dd0f9SErin Lo bias-disable; 3248e2dd0f9SErin Lo }; 3258e2dd0f9SErin Lo }; 3268e2dd0f9SErin Lo 3278e2dd0f9SErin Lo spi_pins_5: spi5{ 3288e2dd0f9SErin Lo pins_spi{ 3298e2dd0f9SErin Lo pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 3308e2dd0f9SErin Lo <PINMUX_GPIO14__FUNC_SPI5_CSB>, 3318e2dd0f9SErin Lo <PINMUX_GPIO15__FUNC_SPI5_MO>, 3328e2dd0f9SErin Lo <PINMUX_GPIO16__FUNC_SPI5_CLK>; 3338e2dd0f9SErin Lo bias-disable; 3348e2dd0f9SErin Lo }; 3358e2dd0f9SErin Lo }; 3368e2dd0f9SErin Lo}; 3378e2dd0f9SErin Lo 3388e2dd0f9SErin Lo&spi0 { 3398e2dd0f9SErin Lo pinctrl-names = "default"; 3408e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_0>; 3418e2dd0f9SErin Lo mediatek,pad-select = <0>; 3428e2dd0f9SErin Lo status = "okay"; 3438e2dd0f9SErin Lo}; 3448e2dd0f9SErin Lo 3458e2dd0f9SErin Lo&spi1 { 3468e2dd0f9SErin Lo pinctrl-names = "default"; 3478e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_1>; 3488e2dd0f9SErin Lo mediatek,pad-select = <0>; 3498e2dd0f9SErin Lo status = "okay"; 3508e2dd0f9SErin Lo}; 3518e2dd0f9SErin Lo 3528e2dd0f9SErin Lo&spi2 { 3538e2dd0f9SErin Lo pinctrl-names = "default"; 3548e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_2>; 3558e2dd0f9SErin Lo mediatek,pad-select = <0>; 3568e2dd0f9SErin Lo status = "okay"; 3578e2dd0f9SErin Lo}; 3588e2dd0f9SErin Lo 3598e2dd0f9SErin Lo&spi3 { 3608e2dd0f9SErin Lo pinctrl-names = "default"; 3618e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_3>; 3628e2dd0f9SErin Lo mediatek,pad-select = <0>; 3638e2dd0f9SErin Lo status = "okay"; 3648e2dd0f9SErin Lo}; 3658e2dd0f9SErin Lo 3668e2dd0f9SErin Lo&spi4 { 3678e2dd0f9SErin Lo pinctrl-names = "default"; 3688e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_4>; 3698e2dd0f9SErin Lo mediatek,pad-select = <0>; 3708e2dd0f9SErin Lo status = "okay"; 3718e2dd0f9SErin Lo}; 3728e2dd0f9SErin Lo 3738e2dd0f9SErin Lo&spi5 { 3748e2dd0f9SErin Lo pinctrl-names = "default"; 3758e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_5>; 3768e2dd0f9SErin Lo mediatek,pad-select = <0>; 3778e2dd0f9SErin Lo status = "okay"; 3788e2dd0f9SErin Lo 3798e2dd0f9SErin Lo}; 3808e2dd0f9SErin Lo 381e526c9bcSBen Ho&uart0 { 382e526c9bcSBen Ho status = "okay"; 383e526c9bcSBen Ho}; 384