1e526c9bcSBen Ho// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2e526c9bcSBen Ho/* 3e526c9bcSBen Ho * Copyright (c) 2018 MediaTek Inc. 4e526c9bcSBen Ho * Author: Ben Ho <ben.ho@mediatek.com> 5e526c9bcSBen Ho * Erin Lo <erin.lo@mediatek.com> 6e526c9bcSBen Ho */ 7e526c9bcSBen Ho 8e526c9bcSBen Ho/dts-v1/; 9e526c9bcSBen Ho#include "mt8183.dtsi" 10e526c9bcSBen Ho 11e526c9bcSBen Ho/ { 12e526c9bcSBen Ho model = "MediaTek MT8183 evaluation board"; 13e526c9bcSBen Ho compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; 14e526c9bcSBen Ho 15e526c9bcSBen Ho aliases { 16e526c9bcSBen Ho serial0 = &uart0; 17e526c9bcSBen Ho }; 18e526c9bcSBen Ho 19e526c9bcSBen Ho memory@40000000 { 20e526c9bcSBen Ho device_type = "memory"; 21e526c9bcSBen Ho reg = <0 0x40000000 0 0x80000000>; 22e526c9bcSBen Ho }; 23e526c9bcSBen Ho 24e526c9bcSBen Ho chosen { 25e526c9bcSBen Ho stdout-path = "serial0:921600n8"; 26e526c9bcSBen Ho }; 27e526c9bcSBen Ho}; 28e526c9bcSBen Ho 29eb59b353SZhiyong Tao&auxadc { 30eb59b353SZhiyong Tao status = "okay"; 31eb59b353SZhiyong Tao}; 32eb59b353SZhiyong Tao 33251137b8SQii Wang&i2c0 { 34251137b8SQii Wang pinctrl-names = "default"; 35251137b8SQii Wang pinctrl-0 = <&i2c_pins_0>; 36251137b8SQii Wang status = "okay"; 37251137b8SQii Wang clock-frequency = <100000>; 38251137b8SQii Wang}; 39251137b8SQii Wang 40251137b8SQii Wang&i2c1 { 41251137b8SQii Wang pinctrl-names = "default"; 42251137b8SQii Wang pinctrl-0 = <&i2c_pins_1>; 43251137b8SQii Wang status = "okay"; 44251137b8SQii Wang clock-frequency = <100000>; 45251137b8SQii Wang}; 46251137b8SQii Wang 47251137b8SQii Wang&i2c2 { 48251137b8SQii Wang pinctrl-names = "default"; 49251137b8SQii Wang pinctrl-0 = <&i2c_pins_2>; 50251137b8SQii Wang status = "okay"; 51251137b8SQii Wang clock-frequency = <100000>; 52251137b8SQii Wang}; 53251137b8SQii Wang 54251137b8SQii Wang&i2c3 { 55251137b8SQii Wang pinctrl-names = "default"; 56251137b8SQii Wang pinctrl-0 = <&i2c_pins_3>; 57251137b8SQii Wang status = "okay"; 58251137b8SQii Wang clock-frequency = <100000>; 59251137b8SQii Wang}; 60251137b8SQii Wang 61251137b8SQii Wang&i2c4 { 62251137b8SQii Wang pinctrl-names = "default"; 63251137b8SQii Wang pinctrl-0 = <&i2c_pins_4>; 64251137b8SQii Wang status = "okay"; 65251137b8SQii Wang clock-frequency = <1000000>; 66251137b8SQii Wang}; 67251137b8SQii Wang 68251137b8SQii Wang&i2c5 { 69251137b8SQii Wang pinctrl-names = "default"; 70251137b8SQii Wang pinctrl-0 = <&i2c_pins_5>; 71251137b8SQii Wang status = "okay"; 72251137b8SQii Wang clock-frequency = <1000000>; 73251137b8SQii Wang}; 74251137b8SQii Wang 758e2dd0f9SErin Lo&pio { 76251137b8SQii Wang i2c_pins_0: i2c0{ 77251137b8SQii Wang pins_i2c{ 78251137b8SQii Wang pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 79251137b8SQii Wang <PINMUX_GPIO83__FUNC_SCL0>; 80251137b8SQii Wang mediatek,pull-up-adv = <3>; 81251137b8SQii Wang mediatek,drive-strength-adv = <00>; 82251137b8SQii Wang }; 83251137b8SQii Wang }; 84251137b8SQii Wang 85251137b8SQii Wang i2c_pins_1: i2c1{ 86251137b8SQii Wang pins_i2c{ 87251137b8SQii Wang pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 88251137b8SQii Wang <PINMUX_GPIO84__FUNC_SCL1>; 89251137b8SQii Wang mediatek,pull-up-adv = <3>; 90251137b8SQii Wang mediatek,drive-strength-adv = <00>; 91251137b8SQii Wang }; 92251137b8SQii Wang }; 93251137b8SQii Wang 94251137b8SQii Wang i2c_pins_2: i2c2{ 95251137b8SQii Wang pins_i2c{ 96251137b8SQii Wang pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 97251137b8SQii Wang <PINMUX_GPIO104__FUNC_SDA2>; 98251137b8SQii Wang mediatek,pull-up-adv = <3>; 99251137b8SQii Wang mediatek,drive-strength-adv = <00>; 100251137b8SQii Wang }; 101251137b8SQii Wang }; 102251137b8SQii Wang 103251137b8SQii Wang i2c_pins_3: i2c3{ 104251137b8SQii Wang pins_i2c{ 105251137b8SQii Wang pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 106251137b8SQii Wang <PINMUX_GPIO51__FUNC_SDA3>; 107251137b8SQii Wang mediatek,pull-up-adv = <3>; 108251137b8SQii Wang mediatek,drive-strength-adv = <00>; 109251137b8SQii Wang }; 110251137b8SQii Wang }; 111251137b8SQii Wang 112251137b8SQii Wang i2c_pins_4: i2c4{ 113251137b8SQii Wang pins_i2c{ 114251137b8SQii Wang pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 115251137b8SQii Wang <PINMUX_GPIO106__FUNC_SDA4>; 116251137b8SQii Wang mediatek,pull-up-adv = <3>; 117251137b8SQii Wang mediatek,drive-strength-adv = <00>; 118251137b8SQii Wang }; 119251137b8SQii Wang }; 120251137b8SQii Wang 121251137b8SQii Wang i2c_pins_5: i2c5{ 122251137b8SQii Wang pins_i2c{ 123251137b8SQii Wang pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 124251137b8SQii Wang <PINMUX_GPIO49__FUNC_SDA5>; 125251137b8SQii Wang mediatek,pull-up-adv = <3>; 126251137b8SQii Wang mediatek,drive-strength-adv = <00>; 127251137b8SQii Wang }; 128251137b8SQii Wang }; 129251137b8SQii Wang 1308e2dd0f9SErin Lo spi_pins_0: spi0{ 1318e2dd0f9SErin Lo pins_spi{ 1328e2dd0f9SErin Lo pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 1338e2dd0f9SErin Lo <PINMUX_GPIO86__FUNC_SPI0_CSB>, 1348e2dd0f9SErin Lo <PINMUX_GPIO87__FUNC_SPI0_MO>, 1358e2dd0f9SErin Lo <PINMUX_GPIO88__FUNC_SPI0_CLK>; 1368e2dd0f9SErin Lo bias-disable; 1378e2dd0f9SErin Lo }; 1388e2dd0f9SErin Lo }; 1398e2dd0f9SErin Lo 1408e2dd0f9SErin Lo spi_pins_1: spi1{ 1418e2dd0f9SErin Lo pins_spi{ 1428e2dd0f9SErin Lo pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 1438e2dd0f9SErin Lo <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 1448e2dd0f9SErin Lo <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 1458e2dd0f9SErin Lo <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 1468e2dd0f9SErin Lo bias-disable; 1478e2dd0f9SErin Lo }; 1488e2dd0f9SErin Lo }; 1498e2dd0f9SErin Lo 1508e2dd0f9SErin Lo spi_pins_2: spi2{ 1518e2dd0f9SErin Lo pins_spi{ 1528e2dd0f9SErin Lo pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 1538e2dd0f9SErin Lo <PINMUX_GPIO1__FUNC_SPI2_MO>, 1548e2dd0f9SErin Lo <PINMUX_GPIO2__FUNC_SPI2_CLK>, 1558e2dd0f9SErin Lo <PINMUX_GPIO94__FUNC_SPI2_MI>; 1568e2dd0f9SErin Lo bias-disable; 1578e2dd0f9SErin Lo }; 1588e2dd0f9SErin Lo }; 1598e2dd0f9SErin Lo 1608e2dd0f9SErin Lo spi_pins_3: spi3{ 1618e2dd0f9SErin Lo pins_spi{ 1628e2dd0f9SErin Lo pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 1638e2dd0f9SErin Lo <PINMUX_GPIO22__FUNC_SPI3_CSB>, 1648e2dd0f9SErin Lo <PINMUX_GPIO23__FUNC_SPI3_MO>, 1658e2dd0f9SErin Lo <PINMUX_GPIO24__FUNC_SPI3_CLK>; 1668e2dd0f9SErin Lo bias-disable; 1678e2dd0f9SErin Lo }; 1688e2dd0f9SErin Lo }; 1698e2dd0f9SErin Lo 1708e2dd0f9SErin Lo spi_pins_4: spi4{ 1718e2dd0f9SErin Lo pins_spi{ 1728e2dd0f9SErin Lo pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 1738e2dd0f9SErin Lo <PINMUX_GPIO18__FUNC_SPI4_CSB>, 1748e2dd0f9SErin Lo <PINMUX_GPIO19__FUNC_SPI4_MO>, 1758e2dd0f9SErin Lo <PINMUX_GPIO20__FUNC_SPI4_CLK>; 1768e2dd0f9SErin Lo bias-disable; 1778e2dd0f9SErin Lo }; 1788e2dd0f9SErin Lo }; 1798e2dd0f9SErin Lo 1808e2dd0f9SErin Lo spi_pins_5: spi5{ 1818e2dd0f9SErin Lo pins_spi{ 1828e2dd0f9SErin Lo pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 1838e2dd0f9SErin Lo <PINMUX_GPIO14__FUNC_SPI5_CSB>, 1848e2dd0f9SErin Lo <PINMUX_GPIO15__FUNC_SPI5_MO>, 1858e2dd0f9SErin Lo <PINMUX_GPIO16__FUNC_SPI5_CLK>; 1868e2dd0f9SErin Lo bias-disable; 1878e2dd0f9SErin Lo }; 1888e2dd0f9SErin Lo }; 1898e2dd0f9SErin Lo}; 1908e2dd0f9SErin Lo 1918e2dd0f9SErin Lo&spi0 { 1928e2dd0f9SErin Lo pinctrl-names = "default"; 1938e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_0>; 1948e2dd0f9SErin Lo mediatek,pad-select = <0>; 1958e2dd0f9SErin Lo status = "okay"; 1968e2dd0f9SErin Lo}; 1978e2dd0f9SErin Lo 1988e2dd0f9SErin Lo&spi1 { 1998e2dd0f9SErin Lo pinctrl-names = "default"; 2008e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_1>; 2018e2dd0f9SErin Lo mediatek,pad-select = <0>; 2028e2dd0f9SErin Lo status = "okay"; 2038e2dd0f9SErin Lo}; 2048e2dd0f9SErin Lo 2058e2dd0f9SErin Lo&spi2 { 2068e2dd0f9SErin Lo pinctrl-names = "default"; 2078e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_2>; 2088e2dd0f9SErin Lo mediatek,pad-select = <0>; 2098e2dd0f9SErin Lo status = "okay"; 2108e2dd0f9SErin Lo}; 2118e2dd0f9SErin Lo 2128e2dd0f9SErin Lo&spi3 { 2138e2dd0f9SErin Lo pinctrl-names = "default"; 2148e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_3>; 2158e2dd0f9SErin Lo mediatek,pad-select = <0>; 2168e2dd0f9SErin Lo status = "okay"; 2178e2dd0f9SErin Lo}; 2188e2dd0f9SErin Lo 2198e2dd0f9SErin Lo&spi4 { 2208e2dd0f9SErin Lo pinctrl-names = "default"; 2218e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_4>; 2228e2dd0f9SErin Lo mediatek,pad-select = <0>; 2238e2dd0f9SErin Lo status = "okay"; 2248e2dd0f9SErin Lo}; 2258e2dd0f9SErin Lo 2268e2dd0f9SErin Lo&spi5 { 2278e2dd0f9SErin Lo pinctrl-names = "default"; 2288e2dd0f9SErin Lo pinctrl-0 = <&spi_pins_5>; 2298e2dd0f9SErin Lo mediatek,pad-select = <0>; 2308e2dd0f9SErin Lo status = "okay"; 2318e2dd0f9SErin Lo 2328e2dd0f9SErin Lo}; 2338e2dd0f9SErin Lo 234e526c9bcSBen Ho&uart0 { 235e526c9bcSBen Ho status = "okay"; 236e526c9bcSBen Ho}; 237