1e526c9bcSBen Ho// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2e526c9bcSBen Ho/*
3e526c9bcSBen Ho * Copyright (c) 2018 MediaTek Inc.
4e526c9bcSBen Ho * Author: Ben Ho <ben.ho@mediatek.com>
5e526c9bcSBen Ho *	   Erin Lo <erin.lo@mediatek.com>
6e526c9bcSBen Ho */
7e526c9bcSBen Ho
8e526c9bcSBen Ho/dts-v1/;
9e526c9bcSBen Ho#include "mt8183.dtsi"
109f887222SHsin-Hsiung Wang#include "mt6358.dtsi"
11e526c9bcSBen Ho
12e526c9bcSBen Ho/ {
13e526c9bcSBen Ho	model = "MediaTek MT8183 evaluation board";
14e526c9bcSBen Ho	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
15e526c9bcSBen Ho
16e526c9bcSBen Ho	aliases {
17e526c9bcSBen Ho		serial0 = &uart0;
18e526c9bcSBen Ho	};
19e526c9bcSBen Ho
20e526c9bcSBen Ho	memory@40000000 {
21e526c9bcSBen Ho		device_type = "memory";
22e526c9bcSBen Ho		reg = <0 0x40000000 0 0x80000000>;
23e526c9bcSBen Ho	};
24e526c9bcSBen Ho
25e526c9bcSBen Ho	chosen {
26e526c9bcSBen Ho		stdout-path = "serial0:921600n8";
27e526c9bcSBen Ho	};
281652dbf7SEddie Huang
291652dbf7SEddie Huang	reserved-memory {
301652dbf7SEddie Huang		#address-cells = <2>;
311652dbf7SEddie Huang		#size-cells = <2>;
321652dbf7SEddie Huang		ranges;
331652dbf7SEddie Huang		scp_mem_reserved: scp_mem_region {
341652dbf7SEddie Huang			compatible = "shared-dma-pool";
351652dbf7SEddie Huang			reg = <0 0x50000000 0 0x2900000>;
361652dbf7SEddie Huang			no-map;
371652dbf7SEddie Huang		};
381652dbf7SEddie Huang	};
39e526c9bcSBen Ho};
40e526c9bcSBen Ho
41eb59b353SZhiyong Tao&auxadc {
42eb59b353SZhiyong Tao	status = "okay";
43eb59b353SZhiyong Tao};
44eb59b353SZhiyong Tao
45251137b8SQii Wang&i2c0 {
46251137b8SQii Wang	pinctrl-names = "default";
47251137b8SQii Wang	pinctrl-0 = <&i2c_pins_0>;
48251137b8SQii Wang	status = "okay";
49251137b8SQii Wang	clock-frequency = <100000>;
50251137b8SQii Wang};
51251137b8SQii Wang
52251137b8SQii Wang&i2c1 {
53251137b8SQii Wang	pinctrl-names = "default";
54251137b8SQii Wang	pinctrl-0 = <&i2c_pins_1>;
55251137b8SQii Wang	status = "okay";
56251137b8SQii Wang	clock-frequency = <100000>;
57251137b8SQii Wang};
58251137b8SQii Wang
59251137b8SQii Wang&i2c2 {
60251137b8SQii Wang	pinctrl-names = "default";
61251137b8SQii Wang	pinctrl-0 = <&i2c_pins_2>;
62251137b8SQii Wang	status = "okay";
63251137b8SQii Wang	clock-frequency = <100000>;
64251137b8SQii Wang};
65251137b8SQii Wang
66251137b8SQii Wang&i2c3 {
67251137b8SQii Wang	pinctrl-names = "default";
68251137b8SQii Wang	pinctrl-0 = <&i2c_pins_3>;
69251137b8SQii Wang	status = "okay";
70251137b8SQii Wang	clock-frequency = <100000>;
71251137b8SQii Wang};
72251137b8SQii Wang
73251137b8SQii Wang&i2c4 {
74251137b8SQii Wang	pinctrl-names = "default";
75251137b8SQii Wang	pinctrl-0 = <&i2c_pins_4>;
76251137b8SQii Wang	status = "okay";
77251137b8SQii Wang	clock-frequency = <1000000>;
78251137b8SQii Wang};
79251137b8SQii Wang
80251137b8SQii Wang&i2c5 {
81251137b8SQii Wang	pinctrl-names = "default";
82251137b8SQii Wang	pinctrl-0 = <&i2c_pins_5>;
83251137b8SQii Wang	status = "okay";
84251137b8SQii Wang	clock-frequency = <1000000>;
85251137b8SQii Wang};
86251137b8SQii Wang
875e6cdf00Sjjian zhou&mmc0 {
885e6cdf00Sjjian zhou	status = "okay";
895e6cdf00Sjjian zhou	pinctrl-names = "default", "state_uhs";
905e6cdf00Sjjian zhou	pinctrl-0 = <&mmc0_pins_default>;
915e6cdf00Sjjian zhou	pinctrl-1 = <&mmc0_pins_uhs>;
925e6cdf00Sjjian zhou	bus-width = <8>;
935e6cdf00Sjjian zhou	max-frequency = <200000000>;
945e6cdf00Sjjian zhou	cap-mmc-highspeed;
955e6cdf00Sjjian zhou	mmc-hs200-1_8v;
965e6cdf00Sjjian zhou	mmc-hs400-1_8v;
975e6cdf00Sjjian zhou	cap-mmc-hw-reset;
985e6cdf00Sjjian zhou	no-sdio;
995e6cdf00Sjjian zhou	no-sd;
1005e6cdf00Sjjian zhou	hs400-ds-delay = <0x12814>;
1015e6cdf00Sjjian zhou	vmmc-supply = <&mt6358_vemc_reg>;
1025e6cdf00Sjjian zhou	vqmmc-supply = <&mt6358_vio18_reg>;
1035e6cdf00Sjjian zhou	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
1045e6cdf00Sjjian zhou	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
1055e6cdf00Sjjian zhou	non-removable;
1065e6cdf00Sjjian zhou};
1075e6cdf00Sjjian zhou
1085e6cdf00Sjjian zhou&mmc1 {
1095e6cdf00Sjjian zhou	status = "okay";
1105e6cdf00Sjjian zhou	pinctrl-names = "default", "state_uhs";
1115e6cdf00Sjjian zhou	pinctrl-0 = <&mmc1_pins_default>;
1125e6cdf00Sjjian zhou	pinctrl-1 = <&mmc1_pins_uhs>;
1135e6cdf00Sjjian zhou	bus-width = <4>;
1145e6cdf00Sjjian zhou	max-frequency = <200000000>;
1155e6cdf00Sjjian zhou	cap-sd-highspeed;
1165e6cdf00Sjjian zhou	sd-uhs-sdr50;
1175e6cdf00Sjjian zhou	sd-uhs-sdr104;
1185e6cdf00Sjjian zhou	cap-sdio-irq;
1195e6cdf00Sjjian zhou	no-mmc;
1205e6cdf00Sjjian zhou	no-sd;
1215e6cdf00Sjjian zhou	vmmc-supply = <&mt6358_vmch_reg>;
1225e6cdf00Sjjian zhou	vqmmc-supply = <&mt6358_vmc_reg>;
1235e6cdf00Sjjian zhou	keep-power-in-suspend;
1245e6cdf00Sjjian zhou	enable-sdio-wakeup;
1255e6cdf00Sjjian zhou	non-removable;
1265e6cdf00Sjjian zhou};
1275e6cdf00Sjjian zhou
1288e2dd0f9SErin Lo&pio {
129251137b8SQii Wang	i2c_pins_0: i2c0{
130251137b8SQii Wang		pins_i2c{
131251137b8SQii Wang			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
132251137b8SQii Wang				 <PINMUX_GPIO83__FUNC_SCL0>;
133251137b8SQii Wang			mediatek,pull-up-adv = <3>;
134251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
135251137b8SQii Wang		};
136251137b8SQii Wang	};
137251137b8SQii Wang
138251137b8SQii Wang	i2c_pins_1: i2c1{
139251137b8SQii Wang		pins_i2c{
140251137b8SQii Wang			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
141251137b8SQii Wang				 <PINMUX_GPIO84__FUNC_SCL1>;
142251137b8SQii Wang			mediatek,pull-up-adv = <3>;
143251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
144251137b8SQii Wang		};
145251137b8SQii Wang	};
146251137b8SQii Wang
147251137b8SQii Wang	i2c_pins_2: i2c2{
148251137b8SQii Wang		pins_i2c{
149251137b8SQii Wang			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
150251137b8SQii Wang				 <PINMUX_GPIO104__FUNC_SDA2>;
151251137b8SQii Wang			mediatek,pull-up-adv = <3>;
152251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
153251137b8SQii Wang		};
154251137b8SQii Wang	};
155251137b8SQii Wang
156251137b8SQii Wang	i2c_pins_3: i2c3{
157251137b8SQii Wang		pins_i2c{
158251137b8SQii Wang			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
159251137b8SQii Wang				 <PINMUX_GPIO51__FUNC_SDA3>;
160251137b8SQii Wang			mediatek,pull-up-adv = <3>;
161251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
162251137b8SQii Wang		};
163251137b8SQii Wang	};
164251137b8SQii Wang
165251137b8SQii Wang	i2c_pins_4: i2c4{
166251137b8SQii Wang		pins_i2c{
167251137b8SQii Wang			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
168251137b8SQii Wang				 <PINMUX_GPIO106__FUNC_SDA4>;
169251137b8SQii Wang			mediatek,pull-up-adv = <3>;
170251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
171251137b8SQii Wang		};
172251137b8SQii Wang	};
173251137b8SQii Wang
174251137b8SQii Wang	i2c_pins_5: i2c5{
175251137b8SQii Wang		pins_i2c{
176251137b8SQii Wang			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
177251137b8SQii Wang				 <PINMUX_GPIO49__FUNC_SDA5>;
178251137b8SQii Wang			mediatek,pull-up-adv = <3>;
179251137b8SQii Wang			mediatek,drive-strength-adv = <00>;
180251137b8SQii Wang		};
181251137b8SQii Wang	};
182251137b8SQii Wang
1838e2dd0f9SErin Lo	spi_pins_0: spi0{
1848e2dd0f9SErin Lo		pins_spi{
1858e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
1868e2dd0f9SErin Lo				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
1878e2dd0f9SErin Lo				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
1888e2dd0f9SErin Lo				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
1898e2dd0f9SErin Lo			bias-disable;
1908e2dd0f9SErin Lo		};
1918e2dd0f9SErin Lo	};
1928e2dd0f9SErin Lo
1935e6cdf00Sjjian zhou	mmc0_pins_default: mmc0default {
1945e6cdf00Sjjian zhou		pins_cmd_dat {
1955e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
1965e6cdf00Sjjian zhou				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
1975e6cdf00Sjjian zhou				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
1985e6cdf00Sjjian zhou				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
1995e6cdf00Sjjian zhou				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
2005e6cdf00Sjjian zhou				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
2015e6cdf00Sjjian zhou				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
2025e6cdf00Sjjian zhou				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
2035e6cdf00Sjjian zhou				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
2045e6cdf00Sjjian zhou			input-enable;
2055e6cdf00Sjjian zhou			bias-pull-up;
2065e6cdf00Sjjian zhou		};
2075e6cdf00Sjjian zhou
2085e6cdf00Sjjian zhou		pins_clk {
2095e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
2105e6cdf00Sjjian zhou			bias-pull-down;
2115e6cdf00Sjjian zhou		};
2125e6cdf00Sjjian zhou
2135e6cdf00Sjjian zhou		pins_rst {
2145e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
2155e6cdf00Sjjian zhou			bias-pull-up;
2165e6cdf00Sjjian zhou		};
2175e6cdf00Sjjian zhou	};
2185e6cdf00Sjjian zhou
2194b1b8fd8SEnric Balletbo i Serra	mmc0_pins_uhs: mmc0 {
2205e6cdf00Sjjian zhou		pins_cmd_dat {
2215e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
2225e6cdf00Sjjian zhou				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
2235e6cdf00Sjjian zhou				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
2245e6cdf00Sjjian zhou				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
2255e6cdf00Sjjian zhou				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
2265e6cdf00Sjjian zhou				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
2275e6cdf00Sjjian zhou				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
2285e6cdf00Sjjian zhou				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
2295e6cdf00Sjjian zhou				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
2305e6cdf00Sjjian zhou			input-enable;
2315e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2325e6cdf00Sjjian zhou			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
2335e6cdf00Sjjian zhou		};
2345e6cdf00Sjjian zhou
2355e6cdf00Sjjian zhou		pins_clk {
2365e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
2375e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2385e6cdf00Sjjian zhou			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
2395e6cdf00Sjjian zhou		};
2405e6cdf00Sjjian zhou
2415e6cdf00Sjjian zhou		pins_ds {
2425e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
2435e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2445e6cdf00Sjjian zhou			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
2455e6cdf00Sjjian zhou		};
2465e6cdf00Sjjian zhou
2475e6cdf00Sjjian zhou		pins_rst {
2485e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
2495e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_10mA>;
2505e6cdf00Sjjian zhou			bias-pull-up;
2515e6cdf00Sjjian zhou		};
2525e6cdf00Sjjian zhou	};
2535e6cdf00Sjjian zhou
2545e6cdf00Sjjian zhou	mmc1_pins_default: mmc1default {
2555e6cdf00Sjjian zhou		pins_cmd_dat {
2565e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
2575e6cdf00Sjjian zhou				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
2585e6cdf00Sjjian zhou				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
2595e6cdf00Sjjian zhou				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
2605e6cdf00Sjjian zhou				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
2615e6cdf00Sjjian zhou			input-enable;
2625e6cdf00Sjjian zhou			bias-pull-up;
2635e6cdf00Sjjian zhou		};
2645e6cdf00Sjjian zhou
2655e6cdf00Sjjian zhou		pins_clk {
2665e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
2675e6cdf00Sjjian zhou			input-enable;
2685e6cdf00Sjjian zhou			bias-pull-down;
2695e6cdf00Sjjian zhou		};
2705e6cdf00Sjjian zhou
2715e6cdf00Sjjian zhou		pins_pmu {
2725e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
2735e6cdf00Sjjian zhou				   <PINMUX_GPIO166__FUNC_GPIO166>;
2745e6cdf00Sjjian zhou			output-high;
2755e6cdf00Sjjian zhou		};
2765e6cdf00Sjjian zhou	};
2775e6cdf00Sjjian zhou
2784b1b8fd8SEnric Balletbo i Serra	mmc1_pins_uhs: mmc1 {
2795e6cdf00Sjjian zhou		pins_cmd_dat {
2805e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
2815e6cdf00Sjjian zhou				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
2825e6cdf00Sjjian zhou				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
2835e6cdf00Sjjian zhou				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
2845e6cdf00Sjjian zhou				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
2855e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_6mA>;
2865e6cdf00Sjjian zhou			input-enable;
2875e6cdf00Sjjian zhou			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
2885e6cdf00Sjjian zhou		};
2895e6cdf00Sjjian zhou
2905e6cdf00Sjjian zhou		pins_clk {
2915e6cdf00Sjjian zhou			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
2925e6cdf00Sjjian zhou			drive-strength = <MTK_DRIVE_6mA>;
2935e6cdf00Sjjian zhou			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
2945e6cdf00Sjjian zhou			input-enable;
2955e6cdf00Sjjian zhou		};
2965e6cdf00Sjjian zhou	};
2975e6cdf00Sjjian zhou
2988e2dd0f9SErin Lo	spi_pins_1: spi1{
2998e2dd0f9SErin Lo		pins_spi{
3008e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
3018e2dd0f9SErin Lo				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
3028e2dd0f9SErin Lo				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
3038e2dd0f9SErin Lo				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
3048e2dd0f9SErin Lo			bias-disable;
3058e2dd0f9SErin Lo		};
3068e2dd0f9SErin Lo	};
3078e2dd0f9SErin Lo
3088e2dd0f9SErin Lo	spi_pins_2: spi2{
3098e2dd0f9SErin Lo		pins_spi{
3108e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
3118e2dd0f9SErin Lo				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
3128e2dd0f9SErin Lo				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
3138e2dd0f9SErin Lo				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
3148e2dd0f9SErin Lo			bias-disable;
3158e2dd0f9SErin Lo		};
3168e2dd0f9SErin Lo	};
3178e2dd0f9SErin Lo
3188e2dd0f9SErin Lo	spi_pins_3: spi3{
3198e2dd0f9SErin Lo		pins_spi{
3208e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
3218e2dd0f9SErin Lo				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
3228e2dd0f9SErin Lo				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
3238e2dd0f9SErin Lo				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
3248e2dd0f9SErin Lo			bias-disable;
3258e2dd0f9SErin Lo		};
3268e2dd0f9SErin Lo	};
3278e2dd0f9SErin Lo
3288e2dd0f9SErin Lo	spi_pins_4: spi4{
3298e2dd0f9SErin Lo		pins_spi{
3308e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
3318e2dd0f9SErin Lo				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
3328e2dd0f9SErin Lo				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
3338e2dd0f9SErin Lo				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
3348e2dd0f9SErin Lo			bias-disable;
3358e2dd0f9SErin Lo		};
3368e2dd0f9SErin Lo	};
3378e2dd0f9SErin Lo
3388e2dd0f9SErin Lo	spi_pins_5: spi5{
3398e2dd0f9SErin Lo		pins_spi{
3408e2dd0f9SErin Lo			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
3418e2dd0f9SErin Lo				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
3428e2dd0f9SErin Lo				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
3438e2dd0f9SErin Lo				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
3448e2dd0f9SErin Lo			bias-disable;
3458e2dd0f9SErin Lo		};
3468e2dd0f9SErin Lo	};
3478e2dd0f9SErin Lo};
3488e2dd0f9SErin Lo
3498e2dd0f9SErin Lo&spi0 {
3508e2dd0f9SErin Lo	pinctrl-names = "default";
3518e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_0>;
3528e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3538e2dd0f9SErin Lo	status = "okay";
3548e2dd0f9SErin Lo};
3558e2dd0f9SErin Lo
3568e2dd0f9SErin Lo&spi1 {
3578e2dd0f9SErin Lo	pinctrl-names = "default";
3588e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_1>;
3598e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3608e2dd0f9SErin Lo	status = "okay";
3618e2dd0f9SErin Lo};
3628e2dd0f9SErin Lo
3638e2dd0f9SErin Lo&spi2 {
3648e2dd0f9SErin Lo	pinctrl-names = "default";
3658e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_2>;
3668e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3678e2dd0f9SErin Lo	status = "okay";
3688e2dd0f9SErin Lo};
3698e2dd0f9SErin Lo
3708e2dd0f9SErin Lo&spi3 {
3718e2dd0f9SErin Lo	pinctrl-names = "default";
3728e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_3>;
3738e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3748e2dd0f9SErin Lo	status = "okay";
3758e2dd0f9SErin Lo};
3768e2dd0f9SErin Lo
3778e2dd0f9SErin Lo&spi4 {
3788e2dd0f9SErin Lo	pinctrl-names = "default";
3798e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_4>;
3808e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3818e2dd0f9SErin Lo	status = "okay";
3828e2dd0f9SErin Lo};
3838e2dd0f9SErin Lo
3848e2dd0f9SErin Lo&spi5 {
3858e2dd0f9SErin Lo	pinctrl-names = "default";
3868e2dd0f9SErin Lo	pinctrl-0 = <&spi_pins_5>;
3878e2dd0f9SErin Lo	mediatek,pad-select = <0>;
3888e2dd0f9SErin Lo	status = "okay";
3898e2dd0f9SErin Lo
3908e2dd0f9SErin Lo};
3918e2dd0f9SErin Lo
392e526c9bcSBen Ho&uart0 {
393e526c9bcSBen Ho	status = "okay";
394e526c9bcSBen Ho};
395