1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include <dt-bindings/thermal/thermal.h> 23#include "mt8173-pinfunc.h" 24 25/ { 26 compatible = "mediatek,mt8173"; 27 interrupt-parent = <&sysirq>; 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 aliases { 32 ovl0 = &ovl0; 33 ovl1 = &ovl1; 34 rdma0 = &rdma0; 35 rdma1 = &rdma1; 36 rdma2 = &rdma2; 37 wdma0 = &wdma0; 38 wdma1 = &wdma1; 39 color0 = &color0; 40 color1 = &color1; 41 split0 = &split0; 42 split1 = &split1; 43 dpi0 = &dpi0; 44 dsi0 = &dsi0; 45 dsi1 = &dsi1; 46 mdp-rdma0 = &mdp_rdma0; 47 mdp-rdma1 = &mdp_rdma1; 48 mdp-rsz0 = &mdp_rsz0; 49 mdp-rsz1 = &mdp_rsz1; 50 mdp-rsz2 = &mdp_rsz2; 51 mdp-wdma0 = &mdp_wdma0; 52 mdp-wrot0 = &mdp_wrot0; 53 mdp-wrot1 = &mdp_wrot1; 54 serial0 = &uart0; 55 serial1 = &uart1; 56 serial2 = &uart2; 57 serial3 = &uart3; 58 }; 59 60 cluster0_opp: opp_table0 { 61 compatible = "operating-points-v2"; 62 opp-shared; 63 opp-507000000 { 64 opp-hz = /bits/ 64 <507000000>; 65 opp-microvolt = <859000>; 66 }; 67 opp-702000000 { 68 opp-hz = /bits/ 64 <702000000>; 69 opp-microvolt = <908000>; 70 }; 71 opp-1001000000 { 72 opp-hz = /bits/ 64 <1001000000>; 73 opp-microvolt = <983000>; 74 }; 75 opp-1105000000 { 76 opp-hz = /bits/ 64 <1105000000>; 77 opp-microvolt = <1009000>; 78 }; 79 opp-1209000000 { 80 opp-hz = /bits/ 64 <1209000000>; 81 opp-microvolt = <1034000>; 82 }; 83 opp-1300000000 { 84 opp-hz = /bits/ 64 <1300000000>; 85 opp-microvolt = <1057000>; 86 }; 87 opp-1508000000 { 88 opp-hz = /bits/ 64 <1508000000>; 89 opp-microvolt = <1109000>; 90 }; 91 opp-1703000000 { 92 opp-hz = /bits/ 64 <1703000000>; 93 opp-microvolt = <1125000>; 94 }; 95 }; 96 97 cluster1_opp: opp_table1 { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 opp-507000000 { 101 opp-hz = /bits/ 64 <507000000>; 102 opp-microvolt = <828000>; 103 }; 104 opp-702000000 { 105 opp-hz = /bits/ 64 <702000000>; 106 opp-microvolt = <867000>; 107 }; 108 opp-1001000000 { 109 opp-hz = /bits/ 64 <1001000000>; 110 opp-microvolt = <927000>; 111 }; 112 opp-1209000000 { 113 opp-hz = /bits/ 64 <1209000000>; 114 opp-microvolt = <968000>; 115 }; 116 opp-1404000000 { 117 opp-hz = /bits/ 64 <1404000000>; 118 opp-microvolt = <1007000>; 119 }; 120 opp-1612000000 { 121 opp-hz = /bits/ 64 <1612000000>; 122 opp-microvolt = <1049000>; 123 }; 124 opp-1807000000 { 125 opp-hz = /bits/ 64 <1807000000>; 126 opp-microvolt = <1089000>; 127 }; 128 opp-2106000000 { 129 opp-hz = /bits/ 64 <2106000000>; 130 opp-microvolt = <1125000>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 cpu-map { 139 cluster0 { 140 core0 { 141 cpu = <&cpu0>; 142 }; 143 core1 { 144 cpu = <&cpu1>; 145 }; 146 }; 147 148 cluster1 { 149 core0 { 150 cpu = <&cpu2>; 151 }; 152 core1 { 153 cpu = <&cpu3>; 154 }; 155 }; 156 }; 157 158 cpu0: cpu@0 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a53"; 161 reg = <0x000>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0>; 164 #cooling-cells = <2>; 165 dynamic-power-coefficient = <263>; 166 clocks = <&infracfg CLK_INFRA_CA53SEL>, 167 <&apmixedsys CLK_APMIXED_MAINPLL>; 168 clock-names = "cpu", "intermediate"; 169 operating-points-v2 = <&cluster0_opp>; 170 }; 171 172 cpu1: cpu@1 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a53"; 175 reg = <0x001>; 176 enable-method = "psci"; 177 cpu-idle-states = <&CPU_SLEEP_0>; 178 #cooling-cells = <2>; 179 dynamic-power-coefficient = <263>; 180 clocks = <&infracfg CLK_INFRA_CA53SEL>, 181 <&apmixedsys CLK_APMIXED_MAINPLL>; 182 clock-names = "cpu", "intermediate"; 183 operating-points-v2 = <&cluster0_opp>; 184 }; 185 186 cpu2: cpu@100 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a72"; 189 reg = <0x100>; 190 enable-method = "psci"; 191 cpu-idle-states = <&CPU_SLEEP_0>; 192 #cooling-cells = <2>; 193 dynamic-power-coefficient = <530>; 194 clocks = <&infracfg CLK_INFRA_CA72SEL>, 195 <&apmixedsys CLK_APMIXED_MAINPLL>; 196 clock-names = "cpu", "intermediate"; 197 operating-points-v2 = <&cluster1_opp>; 198 }; 199 200 cpu3: cpu@101 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a72"; 203 reg = <0x101>; 204 enable-method = "psci"; 205 cpu-idle-states = <&CPU_SLEEP_0>; 206 #cooling-cells = <2>; 207 dynamic-power-coefficient = <530>; 208 clocks = <&infracfg CLK_INFRA_CA72SEL>, 209 <&apmixedsys CLK_APMIXED_MAINPLL>; 210 clock-names = "cpu", "intermediate"; 211 operating-points-v2 = <&cluster1_opp>; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 217 CPU_SLEEP_0: cpu-sleep-0 { 218 compatible = "arm,idle-state"; 219 local-timer-stop; 220 entry-latency-us = <639>; 221 exit-latency-us = <680>; 222 min-residency-us = <1088>; 223 arm,psci-suspend-param = <0x0010000>; 224 }; 225 }; 226 }; 227 228 pmu_a53 { 229 compatible = "arm,cortex-a53-pmu"; 230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 231 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 232 interrupt-affinity = <&cpu0>, <&cpu1>; 233 }; 234 235 pmu_a72 { 236 compatible = "arm,cortex-a72-pmu"; 237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 238 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 239 interrupt-affinity = <&cpu2>, <&cpu3>; 240 }; 241 242 psci { 243 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 244 method = "smc"; 245 cpu_suspend = <0x84000001>; 246 cpu_off = <0x84000002>; 247 cpu_on = <0x84000003>; 248 }; 249 250 clk26m: oscillator0 { 251 compatible = "fixed-clock"; 252 #clock-cells = <0>; 253 clock-frequency = <26000000>; 254 clock-output-names = "clk26m"; 255 }; 256 257 clk32k: oscillator1 { 258 compatible = "fixed-clock"; 259 #clock-cells = <0>; 260 clock-frequency = <32000>; 261 clock-output-names = "clk32k"; 262 }; 263 264 cpum_ck: oscillator2 { 265 compatible = "fixed-clock"; 266 #clock-cells = <0>; 267 clock-frequency = <0>; 268 clock-output-names = "cpum_ck"; 269 }; 270 271 thermal-zones { 272 cpu_thermal: cpu_thermal { 273 polling-delay-passive = <1000>; /* milliseconds */ 274 polling-delay = <1000>; /* milliseconds */ 275 276 thermal-sensors = <&thermal>; 277 sustainable-power = <1500>; /* milliwatts */ 278 279 trips { 280 threshold: trip-point0 { 281 temperature = <68000>; 282 hysteresis = <2000>; 283 type = "passive"; 284 }; 285 286 target: trip-point1 { 287 temperature = <85000>; 288 hysteresis = <2000>; 289 type = "passive"; 290 }; 291 292 cpu_crit: cpu_crit0 { 293 temperature = <115000>; 294 hysteresis = <2000>; 295 type = "critical"; 296 }; 297 }; 298 299 cooling-maps { 300 map0 { 301 trip = <&target>; 302 cooling-device = <&cpu0 THERMAL_NO_LIMIT 303 THERMAL_NO_LIMIT>, 304 <&cpu1 THERMAL_NO_LIMIT 305 THERMAL_NO_LIMIT>; 306 contribution = <3072>; 307 }; 308 map1 { 309 trip = <&target>; 310 cooling-device = <&cpu2 THERMAL_NO_LIMIT 311 THERMAL_NO_LIMIT>, 312 <&cpu3 THERMAL_NO_LIMIT 313 THERMAL_NO_LIMIT>; 314 contribution = <1024>; 315 }; 316 }; 317 }; 318 }; 319 320 reserved-memory { 321 #address-cells = <2>; 322 #size-cells = <2>; 323 ranges; 324 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 325 compatible = "shared-dma-pool"; 326 reg = <0 0xb7000000 0 0x500000>; 327 alignment = <0x1000>; 328 no-map; 329 }; 330 }; 331 332 timer { 333 compatible = "arm,armv8-timer"; 334 interrupt-parent = <&gic>; 335 interrupts = <GIC_PPI 13 336 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 337 <GIC_PPI 14 338 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 339 <GIC_PPI 11 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 341 <GIC_PPI 10 342 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 343 arm,no-tick-in-suspend; 344 }; 345 346 soc { 347 #address-cells = <2>; 348 #size-cells = <2>; 349 compatible = "simple-bus"; 350 ranges; 351 352 topckgen: clock-controller@10000000 { 353 compatible = "mediatek,mt8173-topckgen"; 354 reg = <0 0x10000000 0 0x1000>; 355 #clock-cells = <1>; 356 }; 357 358 infracfg: power-controller@10001000 { 359 compatible = "mediatek,mt8173-infracfg", "syscon"; 360 reg = <0 0x10001000 0 0x1000>; 361 #clock-cells = <1>; 362 #reset-cells = <1>; 363 }; 364 365 pericfg: power-controller@10003000 { 366 compatible = "mediatek,mt8173-pericfg", "syscon"; 367 reg = <0 0x10003000 0 0x1000>; 368 #clock-cells = <1>; 369 #reset-cells = <1>; 370 }; 371 372 syscfg_pctl_a: syscfg_pctl_a@10005000 { 373 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 374 reg = <0 0x10005000 0 0x1000>; 375 }; 376 377 pio: pinctrl@1000b000 { 378 compatible = "mediatek,mt8173-pinctrl"; 379 reg = <0 0x1000b000 0 0x1000>; 380 mediatek,pctl-regmap = <&syscfg_pctl_a>; 381 pins-are-numbered; 382 gpio-controller; 383 #gpio-cells = <2>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 389 390 hdmi_pin: xxx { 391 392 /*hdmi htplg pin*/ 393 pins1 { 394 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 395 input-enable; 396 bias-pull-down; 397 }; 398 }; 399 400 i2c0_pins_a: i2c0 { 401 pins1 { 402 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 403 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 404 bias-disable; 405 }; 406 }; 407 408 i2c1_pins_a: i2c1 { 409 pins1 { 410 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 411 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 412 bias-disable; 413 }; 414 }; 415 416 i2c2_pins_a: i2c2 { 417 pins1 { 418 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 419 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 420 bias-disable; 421 }; 422 }; 423 424 i2c3_pins_a: i2c3 { 425 pins1 { 426 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 427 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 428 bias-disable; 429 }; 430 }; 431 432 i2c4_pins_a: i2c4 { 433 pins1 { 434 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 435 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 436 bias-disable; 437 }; 438 }; 439 440 i2c6_pins_a: i2c6 { 441 pins1 { 442 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 443 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 444 bias-disable; 445 }; 446 }; 447 }; 448 449 scpsys: power-controller@10006000 { 450 compatible = "mediatek,mt8173-scpsys"; 451 #power-domain-cells = <1>; 452 reg = <0 0x10006000 0 0x1000>; 453 clocks = <&clk26m>, 454 <&topckgen CLK_TOP_MM_SEL>, 455 <&topckgen CLK_TOP_VENC_SEL>, 456 <&topckgen CLK_TOP_VENC_LT_SEL>; 457 clock-names = "mfg", "mm", "venc", "venc_lt"; 458 infracfg = <&infracfg>; 459 }; 460 461 watchdog: watchdog@10007000 { 462 compatible = "mediatek,mt8173-wdt", 463 "mediatek,mt6589-wdt"; 464 reg = <0 0x10007000 0 0x100>; 465 }; 466 467 timer: timer@10008000 { 468 compatible = "mediatek,mt8173-timer", 469 "mediatek,mt6577-timer"; 470 reg = <0 0x10008000 0 0x1000>; 471 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 472 clocks = <&infracfg CLK_INFRA_CLK_13M>, 473 <&topckgen CLK_TOP_RTC_SEL>; 474 }; 475 476 pwrap: pwrap@1000d000 { 477 compatible = "mediatek,mt8173-pwrap"; 478 reg = <0 0x1000d000 0 0x1000>; 479 reg-names = "pwrap"; 480 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 481 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 482 reset-names = "pwrap"; 483 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 484 clock-names = "spi", "wrap"; 485 }; 486 487 cec: cec@10013000 { 488 compatible = "mediatek,mt8173-cec"; 489 reg = <0 0x10013000 0 0xbc>; 490 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 491 clocks = <&infracfg CLK_INFRA_CEC>; 492 status = "disabled"; 493 }; 494 495 vpu: vpu@10020000 { 496 compatible = "mediatek,mt8173-vpu"; 497 reg = <0 0x10020000 0 0x30000>, 498 <0 0x10050000 0 0x100>; 499 reg-names = "tcm", "cfg_reg"; 500 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&topckgen CLK_TOP_SCP_SEL>; 502 clock-names = "main"; 503 memory-region = <&vpu_dma_reserved>; 504 }; 505 506 sysirq: intpol-controller@10200620 { 507 compatible = "mediatek,mt8173-sysirq", 508 "mediatek,mt6577-sysirq"; 509 interrupt-controller; 510 #interrupt-cells = <3>; 511 interrupt-parent = <&gic>; 512 reg = <0 0x10200620 0 0x20>; 513 }; 514 515 iommu: iommu@10205000 { 516 compatible = "mediatek,mt8173-m4u"; 517 reg = <0 0x10205000 0 0x1000>; 518 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 519 clocks = <&infracfg CLK_INFRA_M4U>; 520 clock-names = "bclk"; 521 mediatek,larbs = <&larb0 &larb1 &larb2 522 &larb3 &larb4 &larb5>; 523 #iommu-cells = <1>; 524 }; 525 526 efuse: efuse@10206000 { 527 compatible = "mediatek,mt8173-efuse"; 528 reg = <0 0x10206000 0 0x1000>; 529 #address-cells = <1>; 530 #size-cells = <1>; 531 thermal_calibration: calib@528 { 532 reg = <0x528 0xc>; 533 }; 534 }; 535 536 apmixedsys: clock-controller@10209000 { 537 compatible = "mediatek,mt8173-apmixedsys"; 538 reg = <0 0x10209000 0 0x1000>; 539 #clock-cells = <1>; 540 }; 541 542 hdmi_phy: hdmi-phy@10209100 { 543 compatible = "mediatek,mt8173-hdmi-phy"; 544 reg = <0 0x10209100 0 0x24>; 545 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 546 clock-names = "pll_ref"; 547 clock-output-names = "hdmitx_dig_cts"; 548 mediatek,ibias = <0xa>; 549 mediatek,ibias_up = <0x1c>; 550 #clock-cells = <0>; 551 #phy-cells = <0>; 552 status = "disabled"; 553 }; 554 555 gce: mailbox@10212000 { 556 compatible = "mediatek,mt8173-gce"; 557 reg = <0 0x10212000 0 0x1000>; 558 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 559 clocks = <&infracfg CLK_INFRA_GCE>; 560 clock-names = "gce"; 561 #mbox-cells = <2>; 562 }; 563 564 mipi_tx0: mipi-dphy@10215000 { 565 compatible = "mediatek,mt8173-mipi-tx"; 566 reg = <0 0x10215000 0 0x1000>; 567 clocks = <&clk26m>; 568 clock-output-names = "mipi_tx0_pll"; 569 #clock-cells = <0>; 570 #phy-cells = <0>; 571 status = "disabled"; 572 }; 573 574 mipi_tx1: mipi-dphy@10216000 { 575 compatible = "mediatek,mt8173-mipi-tx"; 576 reg = <0 0x10216000 0 0x1000>; 577 clocks = <&clk26m>; 578 clock-output-names = "mipi_tx1_pll"; 579 #clock-cells = <0>; 580 #phy-cells = <0>; 581 status = "disabled"; 582 }; 583 584 gic: interrupt-controller@10221000 { 585 compatible = "arm,gic-400"; 586 #interrupt-cells = <3>; 587 interrupt-parent = <&gic>; 588 interrupt-controller; 589 reg = <0 0x10221000 0 0x1000>, 590 <0 0x10222000 0 0x2000>, 591 <0 0x10224000 0 0x2000>, 592 <0 0x10226000 0 0x2000>; 593 interrupts = <GIC_PPI 9 594 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 595 }; 596 597 auxadc: auxadc@11001000 { 598 compatible = "mediatek,mt8173-auxadc"; 599 reg = <0 0x11001000 0 0x1000>; 600 clocks = <&pericfg CLK_PERI_AUXADC>; 601 clock-names = "main"; 602 #io-channel-cells = <1>; 603 }; 604 605 uart0: serial@11002000 { 606 compatible = "mediatek,mt8173-uart", 607 "mediatek,mt6577-uart"; 608 reg = <0 0x11002000 0 0x400>; 609 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 610 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 611 clock-names = "baud", "bus"; 612 status = "disabled"; 613 }; 614 615 uart1: serial@11003000 { 616 compatible = "mediatek,mt8173-uart", 617 "mediatek,mt6577-uart"; 618 reg = <0 0x11003000 0 0x400>; 619 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 620 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 621 clock-names = "baud", "bus"; 622 status = "disabled"; 623 }; 624 625 uart2: serial@11004000 { 626 compatible = "mediatek,mt8173-uart", 627 "mediatek,mt6577-uart"; 628 reg = <0 0x11004000 0 0x400>; 629 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 630 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 631 clock-names = "baud", "bus"; 632 status = "disabled"; 633 }; 634 635 uart3: serial@11005000 { 636 compatible = "mediatek,mt8173-uart", 637 "mediatek,mt6577-uart"; 638 reg = <0 0x11005000 0 0x400>; 639 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 640 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 641 clock-names = "baud", "bus"; 642 status = "disabled"; 643 }; 644 645 i2c0: i2c@11007000 { 646 compatible = "mediatek,mt8173-i2c"; 647 reg = <0 0x11007000 0 0x70>, 648 <0 0x11000100 0 0x80>; 649 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 650 clock-div = <16>; 651 clocks = <&pericfg CLK_PERI_I2C0>, 652 <&pericfg CLK_PERI_AP_DMA>; 653 clock-names = "main", "dma"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&i2c0_pins_a>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 status = "disabled"; 659 }; 660 661 i2c1: i2c@11008000 { 662 compatible = "mediatek,mt8173-i2c"; 663 reg = <0 0x11008000 0 0x70>, 664 <0 0x11000180 0 0x80>; 665 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 666 clock-div = <16>; 667 clocks = <&pericfg CLK_PERI_I2C1>, 668 <&pericfg CLK_PERI_AP_DMA>; 669 clock-names = "main", "dma"; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&i2c1_pins_a>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 i2c2: i2c@11009000 { 678 compatible = "mediatek,mt8173-i2c"; 679 reg = <0 0x11009000 0 0x70>, 680 <0 0x11000200 0 0x80>; 681 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 682 clock-div = <16>; 683 clocks = <&pericfg CLK_PERI_I2C2>, 684 <&pericfg CLK_PERI_AP_DMA>; 685 clock-names = "main", "dma"; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&i2c2_pins_a>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 693 spi: spi@1100a000 { 694 compatible = "mediatek,mt8173-spi"; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 reg = <0 0x1100a000 0 0x1000>; 698 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 699 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 700 <&topckgen CLK_TOP_SPI_SEL>, 701 <&pericfg CLK_PERI_SPI0>; 702 clock-names = "parent-clk", "sel-clk", "spi-clk"; 703 status = "disabled"; 704 }; 705 706 thermal: thermal@1100b000 { 707 #thermal-sensor-cells = <0>; 708 compatible = "mediatek,mt8173-thermal"; 709 reg = <0 0x1100b000 0 0x1000>; 710 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 711 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 712 clock-names = "therm", "auxadc"; 713 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 714 mediatek,auxadc = <&auxadc>; 715 mediatek,apmixedsys = <&apmixedsys>; 716 nvmem-cells = <&thermal_calibration>; 717 nvmem-cell-names = "calibration-data"; 718 }; 719 720 nor_flash: spi@1100d000 { 721 compatible = "mediatek,mt8173-nor"; 722 reg = <0 0x1100d000 0 0xe0>; 723 clocks = <&pericfg CLK_PERI_SPI>, 724 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 725 clock-names = "spi", "sf"; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 status = "disabled"; 729 }; 730 731 i2c3: i2c@11010000 { 732 compatible = "mediatek,mt8173-i2c"; 733 reg = <0 0x11010000 0 0x70>, 734 <0 0x11000280 0 0x80>; 735 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 736 clock-div = <16>; 737 clocks = <&pericfg CLK_PERI_I2C3>, 738 <&pericfg CLK_PERI_AP_DMA>; 739 clock-names = "main", "dma"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&i2c3_pins_a>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 i2c4: i2c@11011000 { 748 compatible = "mediatek,mt8173-i2c"; 749 reg = <0 0x11011000 0 0x70>, 750 <0 0x11000300 0 0x80>; 751 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 752 clock-div = <16>; 753 clocks = <&pericfg CLK_PERI_I2C4>, 754 <&pericfg CLK_PERI_AP_DMA>; 755 clock-names = "main", "dma"; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&i2c4_pins_a>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 hdmiddc0: i2c@11012000 { 764 compatible = "mediatek,mt8173-hdmi-ddc"; 765 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 766 reg = <0 0x11012000 0 0x1C>; 767 clocks = <&pericfg CLK_PERI_I2C5>; 768 clock-names = "ddc-i2c"; 769 }; 770 771 i2c6: i2c@11013000 { 772 compatible = "mediatek,mt8173-i2c"; 773 reg = <0 0x11013000 0 0x70>, 774 <0 0x11000080 0 0x80>; 775 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 776 clock-div = <16>; 777 clocks = <&pericfg CLK_PERI_I2C6>, 778 <&pericfg CLK_PERI_AP_DMA>; 779 clock-names = "main", "dma"; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&i2c6_pins_a>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 status = "disabled"; 785 }; 786 787 afe: audio-controller@11220000 { 788 compatible = "mediatek,mt8173-afe-pcm"; 789 reg = <0 0x11220000 0 0x1000>; 790 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 791 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 792 clocks = <&infracfg CLK_INFRA_AUDIO>, 793 <&topckgen CLK_TOP_AUDIO_SEL>, 794 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 795 <&topckgen CLK_TOP_APLL1_DIV0>, 796 <&topckgen CLK_TOP_APLL2_DIV0>, 797 <&topckgen CLK_TOP_I2S0_M_SEL>, 798 <&topckgen CLK_TOP_I2S1_M_SEL>, 799 <&topckgen CLK_TOP_I2S2_M_SEL>, 800 <&topckgen CLK_TOP_I2S3_M_SEL>, 801 <&topckgen CLK_TOP_I2S3_B_SEL>; 802 clock-names = "infra_sys_audio_clk", 803 "top_pdn_audio", 804 "top_pdn_aud_intbus", 805 "bck0", 806 "bck1", 807 "i2s0_m", 808 "i2s1_m", 809 "i2s2_m", 810 "i2s3_m", 811 "i2s3_b"; 812 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 813 <&topckgen CLK_TOP_AUD_2_SEL>; 814 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 815 <&topckgen CLK_TOP_APLL2>; 816 }; 817 818 mmc0: mmc@11230000 { 819 compatible = "mediatek,mt8173-mmc"; 820 reg = <0 0x11230000 0 0x1000>; 821 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 822 clocks = <&pericfg CLK_PERI_MSDC30_0>, 823 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 824 clock-names = "source", "hclk"; 825 status = "disabled"; 826 }; 827 828 mmc1: mmc@11240000 { 829 compatible = "mediatek,mt8173-mmc"; 830 reg = <0 0x11240000 0 0x1000>; 831 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 832 clocks = <&pericfg CLK_PERI_MSDC30_1>, 833 <&topckgen CLK_TOP_AXI_SEL>; 834 clock-names = "source", "hclk"; 835 status = "disabled"; 836 }; 837 838 mmc2: mmc@11250000 { 839 compatible = "mediatek,mt8173-mmc"; 840 reg = <0 0x11250000 0 0x1000>; 841 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 842 clocks = <&pericfg CLK_PERI_MSDC30_2>, 843 <&topckgen CLK_TOP_AXI_SEL>; 844 clock-names = "source", "hclk"; 845 status = "disabled"; 846 }; 847 848 mmc3: mmc@11260000 { 849 compatible = "mediatek,mt8173-mmc"; 850 reg = <0 0x11260000 0 0x1000>; 851 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 852 clocks = <&pericfg CLK_PERI_MSDC30_3>, 853 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 854 clock-names = "source", "hclk"; 855 status = "disabled"; 856 }; 857 858 ssusb: usb@11271000 { 859 compatible = "mediatek,mt8173-mtu3"; 860 reg = <0 0x11271000 0 0x3000>, 861 <0 0x11280700 0 0x0100>; 862 reg-names = "mac", "ippc"; 863 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 864 phys = <&u2port0 PHY_TYPE_USB2>, 865 <&u3port0 PHY_TYPE_USB3>, 866 <&u2port1 PHY_TYPE_USB2>; 867 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 868 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 869 clock-names = "sys_ck", "ref_ck"; 870 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 871 #address-cells = <2>; 872 #size-cells = <2>; 873 ranges; 874 status = "disabled"; 875 876 usb_host: xhci@11270000 { 877 compatible = "mediatek,mt8173-xhci"; 878 reg = <0 0x11270000 0 0x1000>; 879 reg-names = "mac"; 880 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 881 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 882 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 883 clock-names = "sys_ck", "ref_ck"; 884 status = "disabled"; 885 }; 886 }; 887 888 u3phy: usb-phy@11290000 { 889 compatible = "mediatek,mt8173-u3phy"; 890 reg = <0 0x11290000 0 0x800>; 891 #address-cells = <2>; 892 #size-cells = <2>; 893 ranges; 894 status = "okay"; 895 896 u2port0: usb-phy@11290800 { 897 reg = <0 0x11290800 0 0x100>; 898 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 899 clock-names = "ref"; 900 #phy-cells = <1>; 901 status = "okay"; 902 }; 903 904 u3port0: usb-phy@11290900 { 905 reg = <0 0x11290900 0 0x700>; 906 clocks = <&clk26m>; 907 clock-names = "ref"; 908 #phy-cells = <1>; 909 status = "okay"; 910 }; 911 912 u2port1: usb-phy@11291000 { 913 reg = <0 0x11291000 0 0x100>; 914 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 915 clock-names = "ref"; 916 #phy-cells = <1>; 917 status = "okay"; 918 }; 919 }; 920 921 mmsys: clock-controller@14000000 { 922 compatible = "mediatek,mt8173-mmsys", "syscon"; 923 reg = <0 0x14000000 0 0x1000>; 924 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 925 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 926 assigned-clock-rates = <400000000>; 927 #clock-cells = <1>; 928 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 929 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 930 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 931 }; 932 933 mdp_rdma0: rdma@14001000 { 934 compatible = "mediatek,mt8173-mdp-rdma", 935 "mediatek,mt8173-mdp"; 936 reg = <0 0x14001000 0 0x1000>; 937 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 938 <&mmsys CLK_MM_MUTEX_32K>; 939 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 940 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 941 mediatek,larb = <&larb0>; 942 mediatek,vpu = <&vpu>; 943 }; 944 945 mdp_rdma1: rdma@14002000 { 946 compatible = "mediatek,mt8173-mdp-rdma"; 947 reg = <0 0x14002000 0 0x1000>; 948 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 949 <&mmsys CLK_MM_MUTEX_32K>; 950 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 951 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 952 mediatek,larb = <&larb4>; 953 }; 954 955 mdp_rsz0: rsz@14003000 { 956 compatible = "mediatek,mt8173-mdp-rsz"; 957 reg = <0 0x14003000 0 0x1000>; 958 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 959 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 960 }; 961 962 mdp_rsz1: rsz@14004000 { 963 compatible = "mediatek,mt8173-mdp-rsz"; 964 reg = <0 0x14004000 0 0x1000>; 965 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 966 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 967 }; 968 969 mdp_rsz2: rsz@14005000 { 970 compatible = "mediatek,mt8173-mdp-rsz"; 971 reg = <0 0x14005000 0 0x1000>; 972 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 973 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 974 }; 975 976 mdp_wdma0: wdma@14006000 { 977 compatible = "mediatek,mt8173-mdp-wdma"; 978 reg = <0 0x14006000 0 0x1000>; 979 clocks = <&mmsys CLK_MM_MDP_WDMA>; 980 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 981 iommus = <&iommu M4U_PORT_MDP_WDMA>; 982 mediatek,larb = <&larb0>; 983 }; 984 985 mdp_wrot0: wrot@14007000 { 986 compatible = "mediatek,mt8173-mdp-wrot"; 987 reg = <0 0x14007000 0 0x1000>; 988 clocks = <&mmsys CLK_MM_MDP_WROT0>; 989 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 990 iommus = <&iommu M4U_PORT_MDP_WROT0>; 991 mediatek,larb = <&larb0>; 992 }; 993 994 mdp_wrot1: wrot@14008000 { 995 compatible = "mediatek,mt8173-mdp-wrot"; 996 reg = <0 0x14008000 0 0x1000>; 997 clocks = <&mmsys CLK_MM_MDP_WROT1>; 998 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 999 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1000 mediatek,larb = <&larb4>; 1001 }; 1002 1003 ovl0: ovl@1400c000 { 1004 compatible = "mediatek,mt8173-disp-ovl"; 1005 reg = <0 0x1400c000 0 0x1000>; 1006 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1007 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1008 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1009 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1010 mediatek,larb = <&larb0>; 1011 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1012 }; 1013 1014 ovl1: ovl@1400d000 { 1015 compatible = "mediatek,mt8173-disp-ovl"; 1016 reg = <0 0x1400d000 0 0x1000>; 1017 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1018 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1019 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1020 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1021 mediatek,larb = <&larb4>; 1022 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1023 }; 1024 1025 rdma0: rdma@1400e000 { 1026 compatible = "mediatek,mt8173-disp-rdma"; 1027 reg = <0 0x1400e000 0 0x1000>; 1028 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1029 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1030 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1031 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1032 mediatek,larb = <&larb0>; 1033 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1034 }; 1035 1036 rdma1: rdma@1400f000 { 1037 compatible = "mediatek,mt8173-disp-rdma"; 1038 reg = <0 0x1400f000 0 0x1000>; 1039 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1040 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1041 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1042 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1043 mediatek,larb = <&larb4>; 1044 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1045 }; 1046 1047 rdma2: rdma@14010000 { 1048 compatible = "mediatek,mt8173-disp-rdma"; 1049 reg = <0 0x14010000 0 0x1000>; 1050 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1051 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1052 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1053 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1054 mediatek,larb = <&larb4>; 1055 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1056 }; 1057 1058 wdma0: wdma@14011000 { 1059 compatible = "mediatek,mt8173-disp-wdma"; 1060 reg = <0 0x14011000 0 0x1000>; 1061 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1062 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1063 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1064 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1065 mediatek,larb = <&larb0>; 1066 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1067 }; 1068 1069 wdma1: wdma@14012000 { 1070 compatible = "mediatek,mt8173-disp-wdma"; 1071 reg = <0 0x14012000 0 0x1000>; 1072 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1073 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1074 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1075 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1076 mediatek,larb = <&larb4>; 1077 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1078 }; 1079 1080 color0: color@14013000 { 1081 compatible = "mediatek,mt8173-disp-color"; 1082 reg = <0 0x14013000 0 0x1000>; 1083 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1084 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1085 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1086 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1087 }; 1088 1089 color1: color@14014000 { 1090 compatible = "mediatek,mt8173-disp-color"; 1091 reg = <0 0x14014000 0 0x1000>; 1092 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1093 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1094 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1095 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1096 }; 1097 1098 aal@14015000 { 1099 compatible = "mediatek,mt8173-disp-aal"; 1100 reg = <0 0x14015000 0 0x1000>; 1101 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1102 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1103 clocks = <&mmsys CLK_MM_DISP_AAL>; 1104 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1105 }; 1106 1107 gamma@14016000 { 1108 compatible = "mediatek,mt8173-disp-gamma"; 1109 reg = <0 0x14016000 0 0x1000>; 1110 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1111 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1112 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1113 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1114 }; 1115 1116 merge@14017000 { 1117 compatible = "mediatek,mt8173-disp-merge"; 1118 reg = <0 0x14017000 0 0x1000>; 1119 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1120 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1121 }; 1122 1123 split0: split@14018000 { 1124 compatible = "mediatek,mt8173-disp-split"; 1125 reg = <0 0x14018000 0 0x1000>; 1126 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1127 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1128 }; 1129 1130 split1: split@14019000 { 1131 compatible = "mediatek,mt8173-disp-split"; 1132 reg = <0 0x14019000 0 0x1000>; 1133 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1134 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1135 }; 1136 1137 ufoe@1401a000 { 1138 compatible = "mediatek,mt8173-disp-ufoe"; 1139 reg = <0 0x1401a000 0 0x1000>; 1140 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1141 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1142 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1143 }; 1144 1145 dsi0: dsi@1401b000 { 1146 compatible = "mediatek,mt8173-dsi"; 1147 reg = <0 0x1401b000 0 0x1000>; 1148 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1149 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1150 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1151 <&mmsys CLK_MM_DSI0_DIGITAL>, 1152 <&mipi_tx0>; 1153 clock-names = "engine", "digital", "hs"; 1154 phys = <&mipi_tx0>; 1155 phy-names = "dphy"; 1156 status = "disabled"; 1157 }; 1158 1159 dsi1: dsi@1401c000 { 1160 compatible = "mediatek,mt8173-dsi"; 1161 reg = <0 0x1401c000 0 0x1000>; 1162 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1163 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1164 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1165 <&mmsys CLK_MM_DSI1_DIGITAL>, 1166 <&mipi_tx1>; 1167 clock-names = "engine", "digital", "hs"; 1168 phy = <&mipi_tx1>; 1169 phy-names = "dphy"; 1170 status = "disabled"; 1171 }; 1172 1173 dpi0: dpi@1401d000 { 1174 compatible = "mediatek,mt8173-dpi"; 1175 reg = <0 0x1401d000 0 0x1000>; 1176 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1177 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1178 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1179 <&mmsys CLK_MM_DPI_ENGINE>, 1180 <&apmixedsys CLK_APMIXED_TVDPLL>; 1181 clock-names = "pixel", "engine", "pll"; 1182 status = "disabled"; 1183 1184 port { 1185 dpi0_out: endpoint { 1186 remote-endpoint = <&hdmi0_in>; 1187 }; 1188 }; 1189 }; 1190 1191 pwm0: pwm@1401e000 { 1192 compatible = "mediatek,mt8173-disp-pwm", 1193 "mediatek,mt6595-disp-pwm"; 1194 reg = <0 0x1401e000 0 0x1000>; 1195 #pwm-cells = <2>; 1196 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1197 <&mmsys CLK_MM_DISP_PWM0MM>; 1198 clock-names = "main", "mm"; 1199 status = "disabled"; 1200 }; 1201 1202 pwm1: pwm@1401f000 { 1203 compatible = "mediatek,mt8173-disp-pwm", 1204 "mediatek,mt6595-disp-pwm"; 1205 reg = <0 0x1401f000 0 0x1000>; 1206 #pwm-cells = <2>; 1207 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1208 <&mmsys CLK_MM_DISP_PWM1MM>; 1209 clock-names = "main", "mm"; 1210 status = "disabled"; 1211 }; 1212 1213 mutex: mutex@14020000 { 1214 compatible = "mediatek,mt8173-disp-mutex"; 1215 reg = <0 0x14020000 0 0x1000>; 1216 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1217 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1218 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1219 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1220 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1221 }; 1222 1223 larb0: larb@14021000 { 1224 compatible = "mediatek,mt8173-smi-larb"; 1225 reg = <0 0x14021000 0 0x1000>; 1226 mediatek,smi = <&smi_common>; 1227 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1228 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1229 <&mmsys CLK_MM_SMI_LARB0>; 1230 clock-names = "apb", "smi"; 1231 }; 1232 1233 smi_common: smi@14022000 { 1234 compatible = "mediatek,mt8173-smi-common"; 1235 reg = <0 0x14022000 0 0x1000>; 1236 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1237 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1238 <&mmsys CLK_MM_SMI_COMMON>; 1239 clock-names = "apb", "smi"; 1240 }; 1241 1242 od@14023000 { 1243 compatible = "mediatek,mt8173-disp-od"; 1244 reg = <0 0x14023000 0 0x1000>; 1245 clocks = <&mmsys CLK_MM_DISP_OD>; 1246 }; 1247 1248 hdmi0: hdmi@14025000 { 1249 compatible = "mediatek,mt8173-hdmi"; 1250 reg = <0 0x14025000 0 0x400>; 1251 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1252 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1253 <&mmsys CLK_MM_HDMI_PLLCK>, 1254 <&mmsys CLK_MM_HDMI_AUDIO>, 1255 <&mmsys CLK_MM_HDMI_SPDIF>; 1256 clock-names = "pixel", "pll", "bclk", "spdif"; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&hdmi_pin>; 1259 phys = <&hdmi_phy>; 1260 phy-names = "hdmi"; 1261 mediatek,syscon-hdmi = <&mmsys 0x900>; 1262 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1263 assigned-clock-parents = <&hdmi_phy>; 1264 status = "disabled"; 1265 1266 ports { 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 1270 port@0 { 1271 reg = <0>; 1272 1273 hdmi0_in: endpoint { 1274 remote-endpoint = <&dpi0_out>; 1275 }; 1276 }; 1277 }; 1278 }; 1279 1280 larb4: larb@14027000 { 1281 compatible = "mediatek,mt8173-smi-larb"; 1282 reg = <0 0x14027000 0 0x1000>; 1283 mediatek,smi = <&smi_common>; 1284 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1285 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1286 <&mmsys CLK_MM_SMI_LARB4>; 1287 clock-names = "apb", "smi"; 1288 }; 1289 1290 imgsys: clock-controller@15000000 { 1291 compatible = "mediatek,mt8173-imgsys", "syscon"; 1292 reg = <0 0x15000000 0 0x1000>; 1293 #clock-cells = <1>; 1294 }; 1295 1296 larb2: larb@15001000 { 1297 compatible = "mediatek,mt8173-smi-larb"; 1298 reg = <0 0x15001000 0 0x1000>; 1299 mediatek,smi = <&smi_common>; 1300 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1301 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1302 <&imgsys CLK_IMG_LARB2_SMI>; 1303 clock-names = "apb", "smi"; 1304 }; 1305 1306 vdecsys: clock-controller@16000000 { 1307 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1308 reg = <0 0x16000000 0 0x1000>; 1309 #clock-cells = <1>; 1310 }; 1311 1312 vcodec_dec: vcodec@16000000 { 1313 compatible = "mediatek,mt8173-vcodec-dec"; 1314 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1315 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1316 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1317 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1318 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1319 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1320 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1321 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1322 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1323 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1324 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1325 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1326 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1327 mediatek,larb = <&larb1>; 1328 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1329 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1330 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1331 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1332 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1333 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1334 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1335 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1336 mediatek,vpu = <&vpu>; 1337 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1338 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1339 <&topckgen CLK_TOP_UNIVPLL_D2>, 1340 <&topckgen CLK_TOP_CCI400_SEL>, 1341 <&topckgen CLK_TOP_VDEC_SEL>, 1342 <&topckgen CLK_TOP_VCODECPLL>, 1343 <&apmixedsys CLK_APMIXED_VENCPLL>, 1344 <&topckgen CLK_TOP_VENC_LT_SEL>, 1345 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1346 clock-names = "vcodecpll", 1347 "univpll_d2", 1348 "clk_cci400_sel", 1349 "vdec_sel", 1350 "vdecpll", 1351 "vencpll", 1352 "venc_lt_sel", 1353 "vdec_bus_clk_src"; 1354 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1355 <&topckgen CLK_TOP_CCI400_SEL>, 1356 <&topckgen CLK_TOP_VDEC_SEL>, 1357 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1358 <&apmixedsys CLK_APMIXED_VENCPLL>; 1359 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1360 <&topckgen CLK_TOP_UNIVPLL_D2>, 1361 <&topckgen CLK_TOP_VCODECPLL>; 1362 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1363 }; 1364 1365 larb1: larb@16010000 { 1366 compatible = "mediatek,mt8173-smi-larb"; 1367 reg = <0 0x16010000 0 0x1000>; 1368 mediatek,smi = <&smi_common>; 1369 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1370 clocks = <&vdecsys CLK_VDEC_CKEN>, 1371 <&vdecsys CLK_VDEC_LARB_CKEN>; 1372 clock-names = "apb", "smi"; 1373 }; 1374 1375 vencsys: clock-controller@18000000 { 1376 compatible = "mediatek,mt8173-vencsys", "syscon"; 1377 reg = <0 0x18000000 0 0x1000>; 1378 #clock-cells = <1>; 1379 }; 1380 1381 larb3: larb@18001000 { 1382 compatible = "mediatek,mt8173-smi-larb"; 1383 reg = <0 0x18001000 0 0x1000>; 1384 mediatek,smi = <&smi_common>; 1385 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1386 clocks = <&vencsys CLK_VENC_CKE1>, 1387 <&vencsys CLK_VENC_CKE0>; 1388 clock-names = "apb", "smi"; 1389 }; 1390 1391 vcodec_enc: vcodec@18002000 { 1392 compatible = "mediatek,mt8173-vcodec-enc"; 1393 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1394 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1395 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1396 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1397 mediatek,larb = <&larb3>, 1398 <&larb5>; 1399 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1400 <&iommu M4U_PORT_VENC_REC>, 1401 <&iommu M4U_PORT_VENC_BSDMA>, 1402 <&iommu M4U_PORT_VENC_SV_COMV>, 1403 <&iommu M4U_PORT_VENC_RD_COMV>, 1404 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1405 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1406 <&iommu M4U_PORT_VENC_REF_LUMA>, 1407 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1408 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1409 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1410 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1411 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1412 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1413 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1414 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1415 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1416 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1417 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1418 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1419 mediatek,vpu = <&vpu>; 1420 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1421 <&topckgen CLK_TOP_VENC_SEL>, 1422 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1423 <&topckgen CLK_TOP_VENC_LT_SEL>; 1424 clock-names = "venc_sel_src", 1425 "venc_sel", 1426 "venc_lt_sel_src", 1427 "venc_lt_sel"; 1428 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1429 <&topckgen CLK_TOP_VENC_LT_SEL>; 1430 assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1431 <&topckgen CLK_TOP_UNIVPLL1_D2>; 1432 }; 1433 1434 jpegdec: jpegdec@18004000 { 1435 compatible = "mediatek,mt8173-jpgdec"; 1436 reg = <0 0x18004000 0 0x1000>; 1437 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1438 clocks = <&vencsys CLK_VENC_CKE0>, 1439 <&vencsys CLK_VENC_CKE3>; 1440 clock-names = "jpgdec-smi", 1441 "jpgdec"; 1442 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1443 mediatek,larb = <&larb3>; 1444 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1445 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1446 }; 1447 1448 vencltsys: clock-controller@19000000 { 1449 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1450 reg = <0 0x19000000 0 0x1000>; 1451 #clock-cells = <1>; 1452 }; 1453 1454 larb5: larb@19001000 { 1455 compatible = "mediatek,mt8173-smi-larb"; 1456 reg = <0 0x19001000 0 0x1000>; 1457 mediatek,smi = <&smi_common>; 1458 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1459 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1460 <&vencltsys CLK_VENCLT_CKE0>; 1461 clock-names = "apb", "smi"; 1462 }; 1463 }; 1464}; 1465