1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 mdp_rdma0 = &mdp_rdma0; 45 mdp_rdma1 = &mdp_rdma1; 46 mdp_rsz0 = &mdp_rsz0; 47 mdp_rsz1 = &mdp_rsz1; 48 mdp_rsz2 = &mdp_rsz2; 49 mdp_wdma0 = &mdp_wdma0; 50 mdp_wrot0 = &mdp_wrot0; 51 mdp_wrot1 = &mdp_wrot1; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x000>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x001>; 90 enable-method = "psci"; 91 cpu-idle-states = <&CPU_SLEEP_0>; 92 }; 93 94 cpu2: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 }; 101 102 cpu3: cpu@101 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a57"; 105 reg = <0x101>; 106 enable-method = "psci"; 107 cpu-idle-states = <&CPU_SLEEP_0>; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 113 CPU_SLEEP_0: cpu-sleep-0 { 114 compatible = "arm,idle-state"; 115 local-timer-stop; 116 entry-latency-us = <639>; 117 exit-latency-us = <680>; 118 min-residency-us = <1088>; 119 arm,psci-suspend-param = <0x0010000>; 120 }; 121 }; 122 }; 123 124 psci { 125 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 126 method = "smc"; 127 cpu_suspend = <0x84000001>; 128 cpu_off = <0x84000002>; 129 cpu_on = <0x84000003>; 130 }; 131 132 clk26m: oscillator@0 { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <26000000>; 136 clock-output-names = "clk26m"; 137 }; 138 139 clk32k: oscillator@1 { 140 compatible = "fixed-clock"; 141 #clock-cells = <0>; 142 clock-frequency = <32000>; 143 clock-output-names = "clk32k"; 144 }; 145 146 cpum_ck: oscillator@2 { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <0>; 150 clock-output-names = "cpum_ck"; 151 }; 152 153 thermal-zones { 154 cpu_thermal: cpu_thermal { 155 polling-delay-passive = <1000>; /* milliseconds */ 156 polling-delay = <1000>; /* milliseconds */ 157 158 thermal-sensors = <&thermal>; 159 sustainable-power = <1500>; /* milliwatts */ 160 161 trips { 162 threshold: trip-point@0 { 163 temperature = <68000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 target: trip-point@1 { 169 temperature = <85000>; 170 hysteresis = <2000>; 171 type = "passive"; 172 }; 173 174 cpu_crit: cpu_crit@0 { 175 temperature = <115000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 181 cooling-maps { 182 map@0 { 183 trip = <&target>; 184 cooling-device = <&cpu0 0 0>; 185 contribution = <1024>; 186 }; 187 map@1 { 188 trip = <&target>; 189 cooling-device = <&cpu2 0 0>; 190 contribution = <2048>; 191 }; 192 }; 193 }; 194 }; 195 196 reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 vpu_dma_reserved: vpu_dma_mem_region { 201 compatible = "shared-dma-pool"; 202 reg = <0 0xb7000000 0 0x500000>; 203 alignment = <0x1000>; 204 no-map; 205 }; 206 }; 207 208 timer { 209 compatible = "arm,armv8-timer"; 210 interrupt-parent = <&gic>; 211 interrupts = <GIC_PPI 13 212 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 213 <GIC_PPI 14 214 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 215 <GIC_PPI 11 216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217 <GIC_PPI 10 218 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219 }; 220 221 soc { 222 #address-cells = <2>; 223 #size-cells = <2>; 224 compatible = "simple-bus"; 225 ranges; 226 227 topckgen: clock-controller@10000000 { 228 compatible = "mediatek,mt8173-topckgen"; 229 reg = <0 0x10000000 0 0x1000>; 230 #clock-cells = <1>; 231 }; 232 233 infracfg: power-controller@10001000 { 234 compatible = "mediatek,mt8173-infracfg", "syscon"; 235 reg = <0 0x10001000 0 0x1000>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 pericfg: power-controller@10003000 { 241 compatible = "mediatek,mt8173-pericfg", "syscon"; 242 reg = <0 0x10003000 0 0x1000>; 243 #clock-cells = <1>; 244 #reset-cells = <1>; 245 }; 246 247 syscfg_pctl_a: syscfg_pctl_a@10005000 { 248 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 249 reg = <0 0x10005000 0 0x1000>; 250 }; 251 252 pio: pinctrl@0x10005000 { 253 compatible = "mediatek,mt8173-pinctrl"; 254 reg = <0 0x1000b000 0 0x1000>; 255 mediatek,pctl-regmap = <&syscfg_pctl_a>; 256 pins-are-numbered; 257 gpio-controller; 258 #gpio-cells = <2>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 264 265 hdmi_pin: xxx { 266 267 /*hdmi htplg pin*/ 268 pins1 { 269 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 270 input-enable; 271 bias-pull-down; 272 }; 273 }; 274 275 i2c0_pins_a: i2c0 { 276 pins1 { 277 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 278 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 279 bias-disable; 280 }; 281 }; 282 283 i2c1_pins_a: i2c1 { 284 pins1 { 285 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 286 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 287 bias-disable; 288 }; 289 }; 290 291 i2c2_pins_a: i2c2 { 292 pins1 { 293 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 294 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 295 bias-disable; 296 }; 297 }; 298 299 i2c3_pins_a: i2c3 { 300 pins1 { 301 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 302 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 303 bias-disable; 304 }; 305 }; 306 307 i2c4_pins_a: i2c4 { 308 pins1 { 309 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 310 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 311 bias-disable; 312 }; 313 }; 314 315 i2c6_pins_a: i2c6 { 316 pins1 { 317 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 318 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 319 bias-disable; 320 }; 321 }; 322 }; 323 324 scpsys: scpsys@10006000 { 325 compatible = "mediatek,mt8173-scpsys"; 326 #power-domain-cells = <1>; 327 reg = <0 0x10006000 0 0x1000>; 328 clocks = <&clk26m>, 329 <&topckgen CLK_TOP_MM_SEL>, 330 <&topckgen CLK_TOP_VENC_SEL>, 331 <&topckgen CLK_TOP_VENC_LT_SEL>; 332 clock-names = "mfg", "mm", "venc", "venc_lt"; 333 infracfg = <&infracfg>; 334 }; 335 336 watchdog: watchdog@10007000 { 337 compatible = "mediatek,mt8173-wdt", 338 "mediatek,mt6589-wdt"; 339 reg = <0 0x10007000 0 0x100>; 340 }; 341 342 timer: timer@10008000 { 343 compatible = "mediatek,mt8173-timer", 344 "mediatek,mt6577-timer"; 345 reg = <0 0x10008000 0 0x1000>; 346 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 347 clocks = <&infracfg CLK_INFRA_CLK_13M>, 348 <&topckgen CLK_TOP_RTC_SEL>; 349 }; 350 351 pwrap: pwrap@1000d000 { 352 compatible = "mediatek,mt8173-pwrap"; 353 reg = <0 0x1000d000 0 0x1000>; 354 reg-names = "pwrap"; 355 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 356 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 357 reset-names = "pwrap"; 358 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 359 clock-names = "spi", "wrap"; 360 }; 361 362 cec: cec@10013000 { 363 compatible = "mediatek,mt8173-cec"; 364 reg = <0 0x10013000 0 0xbc>; 365 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 366 clocks = <&infracfg CLK_INFRA_CEC>; 367 status = "disabled"; 368 }; 369 370 vpu: vpu@10020000 { 371 compatible = "mediatek,mt8173-vpu"; 372 reg = <0 0x10020000 0 0x30000>, 373 <0 0x10050000 0 0x100>; 374 reg-names = "tcm", "cfg_reg"; 375 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&topckgen CLK_TOP_SCP_SEL>; 377 clock-names = "main"; 378 memory-region = <&vpu_dma_reserved>; 379 }; 380 381 sysirq: intpol-controller@10200620 { 382 compatible = "mediatek,mt8173-sysirq", 383 "mediatek,mt6577-sysirq"; 384 interrupt-controller; 385 #interrupt-cells = <3>; 386 interrupt-parent = <&gic>; 387 reg = <0 0x10200620 0 0x20>; 388 }; 389 390 iommu: iommu@10205000 { 391 compatible = "mediatek,mt8173-m4u"; 392 reg = <0 0x10205000 0 0x1000>; 393 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 394 clocks = <&infracfg CLK_INFRA_M4U>; 395 clock-names = "bclk"; 396 mediatek,larbs = <&larb0 &larb1 &larb2 397 &larb3 &larb4 &larb5>; 398 #iommu-cells = <1>; 399 }; 400 401 efuse: efuse@10206000 { 402 compatible = "mediatek,mt8173-efuse"; 403 reg = <0 0x10206000 0 0x1000>; 404 }; 405 406 apmixedsys: clock-controller@10209000 { 407 compatible = "mediatek,mt8173-apmixedsys"; 408 reg = <0 0x10209000 0 0x1000>; 409 #clock-cells = <1>; 410 }; 411 412 hdmi_phy: hdmi-phy@10209100 { 413 compatible = "mediatek,mt8173-hdmi-phy"; 414 reg = <0 0x10209100 0 0x24>; 415 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 416 clock-names = "pll_ref"; 417 clock-output-names = "hdmitx_dig_cts"; 418 mediatek,ibias = <0xa>; 419 mediatek,ibias_up = <0x1c>; 420 #clock-cells = <0>; 421 #phy-cells = <0>; 422 status = "disabled"; 423 }; 424 425 mipi_tx0: mipi-dphy@10215000 { 426 compatible = "mediatek,mt8173-mipi-tx"; 427 reg = <0 0x10215000 0 0x1000>; 428 clocks = <&clk26m>; 429 clock-output-names = "mipi_tx0_pll"; 430 #clock-cells = <0>; 431 #phy-cells = <0>; 432 status = "disabled"; 433 }; 434 435 mipi_tx1: mipi-dphy@10216000 { 436 compatible = "mediatek,mt8173-mipi-tx"; 437 reg = <0 0x10216000 0 0x1000>; 438 clocks = <&clk26m>; 439 clock-output-names = "mipi_tx1_pll"; 440 #clock-cells = <0>; 441 #phy-cells = <0>; 442 status = "disabled"; 443 }; 444 445 gic: interrupt-controller@10220000 { 446 compatible = "arm,gic-400"; 447 #interrupt-cells = <3>; 448 interrupt-parent = <&gic>; 449 interrupt-controller; 450 reg = <0 0x10221000 0 0x1000>, 451 <0 0x10222000 0 0x2000>, 452 <0 0x10224000 0 0x2000>, 453 <0 0x10226000 0 0x2000>; 454 interrupts = <GIC_PPI 9 455 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 456 }; 457 458 auxadc: auxadc@11001000 { 459 compatible = "mediatek,mt8173-auxadc"; 460 reg = <0 0x11001000 0 0x1000>; 461 clocks = <&pericfg CLK_PERI_AUXADC>; 462 clock-names = "main"; 463 #io-channel-cells = <1>; 464 }; 465 466 uart0: serial@11002000 { 467 compatible = "mediatek,mt8173-uart", 468 "mediatek,mt6577-uart"; 469 reg = <0 0x11002000 0 0x400>; 470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 471 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 472 clock-names = "baud", "bus"; 473 status = "disabled"; 474 }; 475 476 uart1: serial@11003000 { 477 compatible = "mediatek,mt8173-uart", 478 "mediatek,mt6577-uart"; 479 reg = <0 0x11003000 0 0x400>; 480 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 481 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 482 clock-names = "baud", "bus"; 483 status = "disabled"; 484 }; 485 486 uart2: serial@11004000 { 487 compatible = "mediatek,mt8173-uart", 488 "mediatek,mt6577-uart"; 489 reg = <0 0x11004000 0 0x400>; 490 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 491 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 492 clock-names = "baud", "bus"; 493 status = "disabled"; 494 }; 495 496 uart3: serial@11005000 { 497 compatible = "mediatek,mt8173-uart", 498 "mediatek,mt6577-uart"; 499 reg = <0 0x11005000 0 0x400>; 500 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 501 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 502 clock-names = "baud", "bus"; 503 status = "disabled"; 504 }; 505 506 i2c0: i2c@11007000 { 507 compatible = "mediatek,mt8173-i2c"; 508 reg = <0 0x11007000 0 0x70>, 509 <0 0x11000100 0 0x80>; 510 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 511 clock-div = <16>; 512 clocks = <&pericfg CLK_PERI_I2C0>, 513 <&pericfg CLK_PERI_AP_DMA>; 514 clock-names = "main", "dma"; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&i2c0_pins_a>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 i2c1: i2c@11008000 { 523 compatible = "mediatek,mt8173-i2c"; 524 reg = <0 0x11008000 0 0x70>, 525 <0 0x11000180 0 0x80>; 526 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 527 clock-div = <16>; 528 clocks = <&pericfg CLK_PERI_I2C1>, 529 <&pericfg CLK_PERI_AP_DMA>; 530 clock-names = "main", "dma"; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&i2c1_pins_a>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 status = "disabled"; 536 }; 537 538 i2c2: i2c@11009000 { 539 compatible = "mediatek,mt8173-i2c"; 540 reg = <0 0x11009000 0 0x70>, 541 <0 0x11000200 0 0x80>; 542 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 543 clock-div = <16>; 544 clocks = <&pericfg CLK_PERI_I2C2>, 545 <&pericfg CLK_PERI_AP_DMA>; 546 clock-names = "main", "dma"; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c2_pins_a>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 spi: spi@1100a000 { 555 compatible = "mediatek,mt8173-spi"; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 reg = <0 0x1100a000 0 0x1000>; 559 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 560 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 561 <&topckgen CLK_TOP_SPI_SEL>, 562 <&pericfg CLK_PERI_SPI0>; 563 clock-names = "parent-clk", "sel-clk", "spi-clk"; 564 status = "disabled"; 565 }; 566 567 thermal: thermal@1100b000 { 568 #thermal-sensor-cells = <0>; 569 compatible = "mediatek,mt8173-thermal"; 570 reg = <0 0x1100b000 0 0x1000>; 571 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 572 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 573 clock-names = "therm", "auxadc"; 574 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 575 mediatek,auxadc = <&auxadc>; 576 mediatek,apmixedsys = <&apmixedsys>; 577 }; 578 579 nor_flash: spi@1100d000 { 580 compatible = "mediatek,mt8173-nor"; 581 reg = <0 0x1100d000 0 0xe0>; 582 clocks = <&pericfg CLK_PERI_SPI>, 583 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 584 clock-names = "spi", "sf"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 i2c3: i2c@11010000 { 591 compatible = "mediatek,mt8173-i2c"; 592 reg = <0 0x11010000 0 0x70>, 593 <0 0x11000280 0 0x80>; 594 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 595 clock-div = <16>; 596 clocks = <&pericfg CLK_PERI_I2C3>, 597 <&pericfg CLK_PERI_AP_DMA>; 598 clock-names = "main", "dma"; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&i2c3_pins_a>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 i2c4: i2c@11011000 { 607 compatible = "mediatek,mt8173-i2c"; 608 reg = <0 0x11011000 0 0x70>, 609 <0 0x11000300 0 0x80>; 610 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 611 clock-div = <16>; 612 clocks = <&pericfg CLK_PERI_I2C4>, 613 <&pericfg CLK_PERI_AP_DMA>; 614 clock-names = "main", "dma"; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&i2c4_pins_a>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 status = "disabled"; 620 }; 621 622 hdmiddc0: i2c@11012000 { 623 compatible = "mediatek,mt8173-hdmi-ddc"; 624 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 625 reg = <0 0x11012000 0 0x1C>; 626 clocks = <&pericfg CLK_PERI_I2C5>; 627 clock-names = "ddc-i2c"; 628 }; 629 630 i2c6: i2c@11013000 { 631 compatible = "mediatek,mt8173-i2c"; 632 reg = <0 0x11013000 0 0x70>, 633 <0 0x11000080 0 0x80>; 634 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 635 clock-div = <16>; 636 clocks = <&pericfg CLK_PERI_I2C6>, 637 <&pericfg CLK_PERI_AP_DMA>; 638 clock-names = "main", "dma"; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&i2c6_pins_a>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 status = "disabled"; 644 }; 645 646 afe: audio-controller@11220000 { 647 compatible = "mediatek,mt8173-afe-pcm"; 648 reg = <0 0x11220000 0 0x1000>; 649 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 650 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 651 clocks = <&infracfg CLK_INFRA_AUDIO>, 652 <&topckgen CLK_TOP_AUDIO_SEL>, 653 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 654 <&topckgen CLK_TOP_APLL1_DIV0>, 655 <&topckgen CLK_TOP_APLL2_DIV0>, 656 <&topckgen CLK_TOP_I2S0_M_SEL>, 657 <&topckgen CLK_TOP_I2S1_M_SEL>, 658 <&topckgen CLK_TOP_I2S2_M_SEL>, 659 <&topckgen CLK_TOP_I2S3_M_SEL>, 660 <&topckgen CLK_TOP_I2S3_B_SEL>; 661 clock-names = "infra_sys_audio_clk", 662 "top_pdn_audio", 663 "top_pdn_aud_intbus", 664 "bck0", 665 "bck1", 666 "i2s0_m", 667 "i2s1_m", 668 "i2s2_m", 669 "i2s3_m", 670 "i2s3_b"; 671 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 672 <&topckgen CLK_TOP_AUD_2_SEL>; 673 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 674 <&topckgen CLK_TOP_APLL2>; 675 }; 676 677 mmc0: mmc@11230000 { 678 compatible = "mediatek,mt8173-mmc", 679 "mediatek,mt8135-mmc"; 680 reg = <0 0x11230000 0 0x1000>; 681 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 682 clocks = <&pericfg CLK_PERI_MSDC30_0>, 683 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 684 clock-names = "source", "hclk"; 685 status = "disabled"; 686 }; 687 688 mmc1: mmc@11240000 { 689 compatible = "mediatek,mt8173-mmc", 690 "mediatek,mt8135-mmc"; 691 reg = <0 0x11240000 0 0x1000>; 692 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 693 clocks = <&pericfg CLK_PERI_MSDC30_1>, 694 <&topckgen CLK_TOP_AXI_SEL>; 695 clock-names = "source", "hclk"; 696 status = "disabled"; 697 }; 698 699 mmc2: mmc@11250000 { 700 compatible = "mediatek,mt8173-mmc", 701 "mediatek,mt8135-mmc"; 702 reg = <0 0x11250000 0 0x1000>; 703 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 704 clocks = <&pericfg CLK_PERI_MSDC30_2>, 705 <&topckgen CLK_TOP_AXI_SEL>; 706 clock-names = "source", "hclk"; 707 status = "disabled"; 708 }; 709 710 mmc3: mmc@11260000 { 711 compatible = "mediatek,mt8173-mmc", 712 "mediatek,mt8135-mmc"; 713 reg = <0 0x11260000 0 0x1000>; 714 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 715 clocks = <&pericfg CLK_PERI_MSDC30_3>, 716 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 717 clock-names = "source", "hclk"; 718 status = "disabled"; 719 }; 720 721 ssusb: usb@11271000 { 722 compatible = "mediatek,mt8173-mtu3"; 723 reg = <0 0x11271000 0 0x3000>, 724 <0 0x11280700 0 0x0100>; 725 reg-names = "mac", "ippc"; 726 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 727 phys = <&phy_port0 PHY_TYPE_USB3>, 728 <&phy_port1 PHY_TYPE_USB2>; 729 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 730 clocks = <&topckgen CLK_TOP_USB30_SEL>, 731 <&pericfg CLK_PERI_USB0>, 732 <&pericfg CLK_PERI_USB1>; 733 clock-names = "sys_ck", 734 "wakeup_deb_p0", 735 "wakeup_deb_p1"; 736 mediatek,syscon-wakeup = <&pericfg>; 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges; 740 status = "disabled"; 741 742 usb_host: xhci@11270000 { 743 compatible = "mediatek,mt8173-xhci"; 744 reg = <0 0x11270000 0 0x1000>; 745 reg-names = "mac"; 746 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 747 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 748 clocks = <&topckgen CLK_TOP_USB30_SEL>; 749 clock-names = "sys_ck"; 750 status = "disabled"; 751 }; 752 }; 753 754 u3phy: usb-phy@11290000 { 755 compatible = "mediatek,mt8173-u3phy"; 756 reg = <0 0x11290000 0 0x800>; 757 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 758 clock-names = "u3phya_ref"; 759 #address-cells = <2>; 760 #size-cells = <2>; 761 ranges; 762 status = "okay"; 763 764 phy_port0: port@11290800 { 765 reg = <0 0x11290800 0 0x800>; 766 #phy-cells = <1>; 767 status = "okay"; 768 }; 769 770 phy_port1: port@11291000 { 771 reg = <0 0x11291000 0 0x800>; 772 #phy-cells = <1>; 773 status = "okay"; 774 }; 775 }; 776 777 mmsys: clock-controller@14000000 { 778 compatible = "mediatek,mt8173-mmsys", "syscon"; 779 reg = <0 0x14000000 0 0x1000>; 780 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 781 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 782 assigned-clock-rates = <400000000>; 783 #clock-cells = <1>; 784 }; 785 786 mdp { 787 compatible = "mediatek,mt8173-mdp"; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 ranges; 791 mediatek,vpu = <&vpu>; 792 793 mdp_rdma0: rdma@14001000 { 794 compatible = "mediatek,mt8173-mdp-rdma"; 795 reg = <0 0x14001000 0 0x1000>; 796 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 797 <&mmsys CLK_MM_MUTEX_32K>; 798 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 799 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 800 mediatek,larb = <&larb0>; 801 }; 802 803 mdp_rdma1: rdma@14002000 { 804 compatible = "mediatek,mt8173-mdp-rdma"; 805 reg = <0 0x14002000 0 0x1000>; 806 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 807 <&mmsys CLK_MM_MUTEX_32K>; 808 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 809 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 810 mediatek,larb = <&larb4>; 811 }; 812 813 mdp_rsz0: rsz@14003000 { 814 compatible = "mediatek,mt8173-mdp-rsz"; 815 reg = <0 0x14003000 0 0x1000>; 816 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 817 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 818 }; 819 820 mdp_rsz1: rsz@14004000 { 821 compatible = "mediatek,mt8173-mdp-rsz"; 822 reg = <0 0x14004000 0 0x1000>; 823 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 824 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 825 }; 826 827 mdp_rsz2: rsz@14005000 { 828 compatible = "mediatek,mt8173-mdp-rsz"; 829 reg = <0 0x14005000 0 0x1000>; 830 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 831 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 832 }; 833 834 mdp_wdma0: wdma@14006000 { 835 compatible = "mediatek,mt8173-mdp-wdma"; 836 reg = <0 0x14006000 0 0x1000>; 837 clocks = <&mmsys CLK_MM_MDP_WDMA>; 838 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 839 iommus = <&iommu M4U_PORT_MDP_WDMA>; 840 mediatek,larb = <&larb0>; 841 }; 842 843 mdp_wrot0: wrot@14007000 { 844 compatible = "mediatek,mt8173-mdp-wrot"; 845 reg = <0 0x14007000 0 0x1000>; 846 clocks = <&mmsys CLK_MM_MDP_WROT0>; 847 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 848 iommus = <&iommu M4U_PORT_MDP_WROT0>; 849 mediatek,larb = <&larb0>; 850 }; 851 852 mdp_wrot1: wrot@14008000 { 853 compatible = "mediatek,mt8173-mdp-wrot"; 854 reg = <0 0x14008000 0 0x1000>; 855 clocks = <&mmsys CLK_MM_MDP_WROT1>; 856 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 857 iommus = <&iommu M4U_PORT_MDP_WROT1>; 858 mediatek,larb = <&larb4>; 859 }; 860 }; 861 862 ovl0: ovl@1400c000 { 863 compatible = "mediatek,mt8173-disp-ovl"; 864 reg = <0 0x1400c000 0 0x1000>; 865 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 866 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 867 clocks = <&mmsys CLK_MM_DISP_OVL0>; 868 iommus = <&iommu M4U_PORT_DISP_OVL0>; 869 mediatek,larb = <&larb0>; 870 }; 871 872 ovl1: ovl@1400d000 { 873 compatible = "mediatek,mt8173-disp-ovl"; 874 reg = <0 0x1400d000 0 0x1000>; 875 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 876 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 877 clocks = <&mmsys CLK_MM_DISP_OVL1>; 878 iommus = <&iommu M4U_PORT_DISP_OVL1>; 879 mediatek,larb = <&larb4>; 880 }; 881 882 rdma0: rdma@1400e000 { 883 compatible = "mediatek,mt8173-disp-rdma"; 884 reg = <0 0x1400e000 0 0x1000>; 885 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 886 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 887 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 888 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 889 mediatek,larb = <&larb0>; 890 }; 891 892 rdma1: rdma@1400f000 { 893 compatible = "mediatek,mt8173-disp-rdma"; 894 reg = <0 0x1400f000 0 0x1000>; 895 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 896 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 897 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 898 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 899 mediatek,larb = <&larb4>; 900 }; 901 902 rdma2: rdma@14010000 { 903 compatible = "mediatek,mt8173-disp-rdma"; 904 reg = <0 0x14010000 0 0x1000>; 905 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 906 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 907 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 908 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 909 mediatek,larb = <&larb4>; 910 }; 911 912 wdma0: wdma@14011000 { 913 compatible = "mediatek,mt8173-disp-wdma"; 914 reg = <0 0x14011000 0 0x1000>; 915 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 916 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 917 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 918 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 919 mediatek,larb = <&larb0>; 920 }; 921 922 wdma1: wdma@14012000 { 923 compatible = "mediatek,mt8173-disp-wdma"; 924 reg = <0 0x14012000 0 0x1000>; 925 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 926 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 928 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 929 mediatek,larb = <&larb4>; 930 }; 931 932 color0: color@14013000 { 933 compatible = "mediatek,mt8173-disp-color"; 934 reg = <0 0x14013000 0 0x1000>; 935 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 936 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 937 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 938 }; 939 940 color1: color@14014000 { 941 compatible = "mediatek,mt8173-disp-color"; 942 reg = <0 0x14014000 0 0x1000>; 943 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 944 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 945 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 946 }; 947 948 aal@14015000 { 949 compatible = "mediatek,mt8173-disp-aal"; 950 reg = <0 0x14015000 0 0x1000>; 951 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 952 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 953 clocks = <&mmsys CLK_MM_DISP_AAL>; 954 }; 955 956 gamma@14016000 { 957 compatible = "mediatek,mt8173-disp-gamma"; 958 reg = <0 0x14016000 0 0x1000>; 959 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 960 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 961 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 962 }; 963 964 merge@14017000 { 965 compatible = "mediatek,mt8173-disp-merge"; 966 reg = <0 0x14017000 0 0x1000>; 967 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 968 clocks = <&mmsys CLK_MM_DISP_MERGE>; 969 }; 970 971 split0: split@14018000 { 972 compatible = "mediatek,mt8173-disp-split"; 973 reg = <0 0x14018000 0 0x1000>; 974 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 975 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 976 }; 977 978 split1: split@14019000 { 979 compatible = "mediatek,mt8173-disp-split"; 980 reg = <0 0x14019000 0 0x1000>; 981 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 982 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 983 }; 984 985 ufoe@1401a000 { 986 compatible = "mediatek,mt8173-disp-ufoe"; 987 reg = <0 0x1401a000 0 0x1000>; 988 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 989 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 990 clocks = <&mmsys CLK_MM_DISP_UFOE>; 991 }; 992 993 dsi0: dsi@1401b000 { 994 compatible = "mediatek,mt8173-dsi"; 995 reg = <0 0x1401b000 0 0x1000>; 996 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 997 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 998 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 999 <&mmsys CLK_MM_DSI0_DIGITAL>, 1000 <&mipi_tx0>; 1001 clock-names = "engine", "digital", "hs"; 1002 phys = <&mipi_tx0>; 1003 phy-names = "dphy"; 1004 status = "disabled"; 1005 }; 1006 1007 dsi1: dsi@1401c000 { 1008 compatible = "mediatek,mt8173-dsi"; 1009 reg = <0 0x1401c000 0 0x1000>; 1010 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1011 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1012 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1013 <&mmsys CLK_MM_DSI1_DIGITAL>, 1014 <&mipi_tx1>; 1015 clock-names = "engine", "digital", "hs"; 1016 phy = <&mipi_tx1>; 1017 phy-names = "dphy"; 1018 status = "disabled"; 1019 }; 1020 1021 dpi0: dpi@1401d000 { 1022 compatible = "mediatek,mt8173-dpi"; 1023 reg = <0 0x1401d000 0 0x1000>; 1024 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1025 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1026 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1027 <&mmsys CLK_MM_DPI_ENGINE>, 1028 <&apmixedsys CLK_APMIXED_TVDPLL>; 1029 clock-names = "pixel", "engine", "pll"; 1030 status = "disabled"; 1031 1032 port { 1033 dpi0_out: endpoint { 1034 remote-endpoint = <&hdmi0_in>; 1035 }; 1036 }; 1037 }; 1038 1039 pwm0: pwm@1401e000 { 1040 compatible = "mediatek,mt8173-disp-pwm", 1041 "mediatek,mt6595-disp-pwm"; 1042 reg = <0 0x1401e000 0 0x1000>; 1043 #pwm-cells = <2>; 1044 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1045 <&mmsys CLK_MM_DISP_PWM0MM>; 1046 clock-names = "main", "mm"; 1047 status = "disabled"; 1048 }; 1049 1050 pwm1: pwm@1401f000 { 1051 compatible = "mediatek,mt8173-disp-pwm", 1052 "mediatek,mt6595-disp-pwm"; 1053 reg = <0 0x1401f000 0 0x1000>; 1054 #pwm-cells = <2>; 1055 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1056 <&mmsys CLK_MM_DISP_PWM1MM>; 1057 clock-names = "main", "mm"; 1058 status = "disabled"; 1059 }; 1060 1061 mutex: mutex@14020000 { 1062 compatible = "mediatek,mt8173-disp-mutex"; 1063 reg = <0 0x14020000 0 0x1000>; 1064 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1065 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1066 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1067 }; 1068 1069 larb0: larb@14021000 { 1070 compatible = "mediatek,mt8173-smi-larb"; 1071 reg = <0 0x14021000 0 0x1000>; 1072 mediatek,smi = <&smi_common>; 1073 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1074 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1075 <&mmsys CLK_MM_SMI_LARB0>; 1076 clock-names = "apb", "smi"; 1077 }; 1078 1079 smi_common: smi@14022000 { 1080 compatible = "mediatek,mt8173-smi-common"; 1081 reg = <0 0x14022000 0 0x1000>; 1082 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1083 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1084 <&mmsys CLK_MM_SMI_COMMON>; 1085 clock-names = "apb", "smi"; 1086 }; 1087 1088 od@14023000 { 1089 compatible = "mediatek,mt8173-disp-od"; 1090 reg = <0 0x14023000 0 0x1000>; 1091 clocks = <&mmsys CLK_MM_DISP_OD>; 1092 }; 1093 1094 hdmi0: hdmi@14025000 { 1095 compatible = "mediatek,mt8173-hdmi"; 1096 reg = <0 0x14025000 0 0x400>; 1097 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1098 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1099 <&mmsys CLK_MM_HDMI_PLLCK>, 1100 <&mmsys CLK_MM_HDMI_AUDIO>, 1101 <&mmsys CLK_MM_HDMI_SPDIF>; 1102 clock-names = "pixel", "pll", "bclk", "spdif"; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&hdmi_pin>; 1105 phys = <&hdmi_phy>; 1106 phy-names = "hdmi"; 1107 mediatek,syscon-hdmi = <&mmsys 0x900>; 1108 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1109 assigned-clock-parents = <&hdmi_phy>; 1110 status = "disabled"; 1111 1112 ports { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 1116 port@0 { 1117 reg = <0>; 1118 1119 hdmi0_in: endpoint { 1120 remote-endpoint = <&dpi0_out>; 1121 }; 1122 }; 1123 }; 1124 }; 1125 1126 larb4: larb@14027000 { 1127 compatible = "mediatek,mt8173-smi-larb"; 1128 reg = <0 0x14027000 0 0x1000>; 1129 mediatek,smi = <&smi_common>; 1130 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1131 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1132 <&mmsys CLK_MM_SMI_LARB4>; 1133 clock-names = "apb", "smi"; 1134 }; 1135 1136 imgsys: clock-controller@15000000 { 1137 compatible = "mediatek,mt8173-imgsys", "syscon"; 1138 reg = <0 0x15000000 0 0x1000>; 1139 #clock-cells = <1>; 1140 }; 1141 1142 larb2: larb@15001000 { 1143 compatible = "mediatek,mt8173-smi-larb"; 1144 reg = <0 0x15001000 0 0x1000>; 1145 mediatek,smi = <&smi_common>; 1146 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1147 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1148 <&imgsys CLK_IMG_LARB2_SMI>; 1149 clock-names = "apb", "smi"; 1150 }; 1151 1152 vdecsys: clock-controller@16000000 { 1153 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1154 reg = <0 0x16000000 0 0x1000>; 1155 #clock-cells = <1>; 1156 }; 1157 1158 vcodec_dec: vcodec@16000000 { 1159 compatible = "mediatek,mt8173-vcodec-dec"; 1160 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1161 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1162 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1163 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1164 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1165 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1166 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1167 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1168 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1169 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1170 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1171 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1172 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1173 mediatek,larb = <&larb1>; 1174 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1175 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1176 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1177 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1178 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1179 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1180 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1181 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1182 mediatek,vpu = <&vpu>; 1183 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1184 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1185 <&topckgen CLK_TOP_UNIVPLL_D2>, 1186 <&topckgen CLK_TOP_CCI400_SEL>, 1187 <&topckgen CLK_TOP_VDEC_SEL>, 1188 <&topckgen CLK_TOP_VCODECPLL>, 1189 <&apmixedsys CLK_APMIXED_VENCPLL>, 1190 <&topckgen CLK_TOP_VENC_LT_SEL>, 1191 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1192 clock-names = "vcodecpll", 1193 "univpll_d2", 1194 "clk_cci400_sel", 1195 "vdec_sel", 1196 "vdecpll", 1197 "vencpll", 1198 "venc_lt_sel", 1199 "vdec_bus_clk_src"; 1200 }; 1201 1202 larb1: larb@16010000 { 1203 compatible = "mediatek,mt8173-smi-larb"; 1204 reg = <0 0x16010000 0 0x1000>; 1205 mediatek,smi = <&smi_common>; 1206 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1207 clocks = <&vdecsys CLK_VDEC_CKEN>, 1208 <&vdecsys CLK_VDEC_LARB_CKEN>; 1209 clock-names = "apb", "smi"; 1210 }; 1211 1212 vencsys: clock-controller@18000000 { 1213 compatible = "mediatek,mt8173-vencsys", "syscon"; 1214 reg = <0 0x18000000 0 0x1000>; 1215 #clock-cells = <1>; 1216 }; 1217 1218 larb3: larb@18001000 { 1219 compatible = "mediatek,mt8173-smi-larb"; 1220 reg = <0 0x18001000 0 0x1000>; 1221 mediatek,smi = <&smi_common>; 1222 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1223 clocks = <&vencsys CLK_VENC_CKE1>, 1224 <&vencsys CLK_VENC_CKE0>; 1225 clock-names = "apb", "smi"; 1226 }; 1227 1228 vcodec_enc: vcodec@18002000 { 1229 compatible = "mediatek,mt8173-vcodec-enc"; 1230 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1231 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1232 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1233 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1234 mediatek,larb = <&larb3>, 1235 <&larb5>; 1236 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1237 <&iommu M4U_PORT_VENC_REC>, 1238 <&iommu M4U_PORT_VENC_BSDMA>, 1239 <&iommu M4U_PORT_VENC_SV_COMV>, 1240 <&iommu M4U_PORT_VENC_RD_COMV>, 1241 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1242 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1243 <&iommu M4U_PORT_VENC_REF_LUMA>, 1244 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1245 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1246 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1247 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1248 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1249 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1250 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1251 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1252 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1253 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1254 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1255 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1256 mediatek,vpu = <&vpu>; 1257 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1258 <&topckgen CLK_TOP_VENC_SEL>, 1259 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1260 <&topckgen CLK_TOP_VENC_LT_SEL>; 1261 clock-names = "venc_sel_src", 1262 "venc_sel", 1263 "venc_lt_sel_src", 1264 "venc_lt_sel"; 1265 }; 1266 1267 vencltsys: clock-controller@19000000 { 1268 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1269 reg = <0 0x19000000 0 0x1000>; 1270 #clock-cells = <1>; 1271 }; 1272 1273 larb5: larb@19001000 { 1274 compatible = "mediatek,mt8173-smi-larb"; 1275 reg = <0 0x19001000 0 0x1000>; 1276 mediatek,smi = <&smi_common>; 1277 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1278 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1279 <&vencltsys CLK_VENCLT_CKE0>; 1280 clock-names = "apb", "smi"; 1281 }; 1282 }; 1283}; 1284 1285