1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include "mt8173-pinfunc.h" 18 19/ { 20 compatible = "mediatek,mt8173"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 }; 38 39 cluster1 { 40 core0 { 41 cpu = <&cpu2>; 42 }; 43 core1 { 44 cpu = <&cpu3>; 45 }; 46 }; 47 }; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x000>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x001>; 59 enable-method = "psci"; 60 }; 61 62 cpu2: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a57"; 65 reg = <0x100>; 66 enable-method = "psci"; 67 }; 68 69 cpu3: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a57"; 72 reg = <0x101>; 73 enable-method = "psci"; 74 }; 75 }; 76 77 psci { 78 compatible = "arm,psci"; 79 method = "smc"; 80 cpu_suspend = <0x84000001>; 81 cpu_off = <0x84000002>; 82 cpu_on = <0x84000003>; 83 }; 84 85 uart_clk: dummy26m { 86 compatible = "fixed-clock"; 87 clock-frequency = <26000000>; 88 #clock-cells = <0>; 89 }; 90 91 clk26m: oscillator@0 { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <26000000>; 95 clock-output-names = "clk26m"; 96 }; 97 98 clk32k: oscillator@1 { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <32000>; 102 clock-output-names = "clk32k"; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupt-parent = <&gic>; 108 interrupts = <GIC_PPI 13 109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 14 111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 11 113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 10 115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 116 }; 117 118 soc { 119 #address-cells = <2>; 120 #size-cells = <2>; 121 compatible = "simple-bus"; 122 ranges; 123 124 topckgen: clock-controller@10000000 { 125 compatible = "mediatek,mt8173-topckgen"; 126 reg = <0 0x10000000 0 0x1000>; 127 #clock-cells = <1>; 128 }; 129 130 infracfg: power-controller@10001000 { 131 compatible = "mediatek,mt8173-infracfg", "syscon"; 132 reg = <0 0x10001000 0 0x1000>; 133 #clock-cells = <1>; 134 #reset-cells = <1>; 135 }; 136 137 pericfg: power-controller@10003000 { 138 compatible = "mediatek,mt8173-pericfg", "syscon"; 139 reg = <0 0x10003000 0 0x1000>; 140 #clock-cells = <1>; 141 #reset-cells = <1>; 142 }; 143 144 syscfg_pctl_a: syscfg_pctl_a@10005000 { 145 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 146 reg = <0 0x10005000 0 0x1000>; 147 }; 148 149 pio: pinctrl@0x10005000 { 150 compatible = "mediatek,mt8173-pinctrl"; 151 reg = <0 0x1000b000 0 0x1000>; 152 mediatek,pctl-regmap = <&syscfg_pctl_a>; 153 pins-are-numbered; 154 gpio-controller; 155 #gpio-cells = <2>; 156 interrupt-controller; 157 #interrupt-cells = <2>; 158 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 161 }; 162 163 syscfg_pctl_a: syscfg_pctl_a@10005000 { 164 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 165 reg = <0 0x10005000 0 0x1000>; 166 }; 167 168 sysirq: intpol-controller@10200620 { 169 compatible = "mediatek,mt8173-sysirq", 170 "mediatek,mt6577-sysirq"; 171 interrupt-controller; 172 #interrupt-cells = <3>; 173 interrupt-parent = <&gic>; 174 reg = <0 0x10200620 0 0x20>; 175 }; 176 177 apmixedsys: clock-controller@10209000 { 178 compatible = "mediatek,mt8173-apmixedsys"; 179 reg = <0 0x10209000 0 0x1000>; 180 #clock-cells = <1>; 181 }; 182 183 gic: interrupt-controller@10220000 { 184 compatible = "arm,gic-400"; 185 #interrupt-cells = <3>; 186 interrupt-parent = <&gic>; 187 interrupt-controller; 188 reg = <0 0x10221000 0 0x1000>, 189 <0 0x10222000 0 0x2000>, 190 <0 0x10224000 0 0x2000>, 191 <0 0x10226000 0 0x2000>; 192 interrupts = <GIC_PPI 9 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 194 }; 195 196 uart0: serial@11002000 { 197 compatible = "mediatek,mt8173-uart", 198 "mediatek,mt6577-uart"; 199 reg = <0 0x11002000 0 0x400>; 200 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 201 clocks = <&uart_clk>; 202 status = "disabled"; 203 }; 204 205 uart1: serial@11003000 { 206 compatible = "mediatek,mt8173-uart", 207 "mediatek,mt6577-uart"; 208 reg = <0 0x11003000 0 0x400>; 209 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 210 clocks = <&uart_clk>; 211 status = "disabled"; 212 }; 213 214 uart2: serial@11004000 { 215 compatible = "mediatek,mt8173-uart", 216 "mediatek,mt6577-uart"; 217 reg = <0 0x11004000 0 0x400>; 218 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 219 clocks = <&uart_clk>; 220 status = "disabled"; 221 }; 222 223 uart3: serial@11005000 { 224 compatible = "mediatek,mt8173-uart", 225 "mediatek,mt6577-uart"; 226 reg = <0 0x11005000 0 0x400>; 227 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 228 clocks = <&uart_clk>; 229 status = "disabled"; 230 }; 231 }; 232}; 233 234