1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 mdp_rdma0 = &mdp_rdma0; 45 mdp_rdma1 = &mdp_rdma1; 46 mdp_rsz0 = &mdp_rsz0; 47 mdp_rsz1 = &mdp_rsz1; 48 mdp_rsz2 = &mdp_rsz2; 49 mdp_wdma0 = &mdp_wdma0; 50 mdp_wrot0 = &mdp_wrot0; 51 mdp_wrot1 = &mdp_wrot1; 52 }; 53 54 cluster0_opp: opp_table0 { 55 compatible = "operating-points-v2"; 56 opp-shared; 57 opp-507000000 { 58 opp-hz = /bits/ 64 <507000000>; 59 opp-microvolt = <859000>; 60 }; 61 opp-702000000 { 62 opp-hz = /bits/ 64 <702000000>; 63 opp-microvolt = <908000>; 64 }; 65 opp-1001000000 { 66 opp-hz = /bits/ 64 <1001000000>; 67 opp-microvolt = <983000>; 68 }; 69 opp-1105000000 { 70 opp-hz = /bits/ 64 <1105000000>; 71 opp-microvolt = <1009000>; 72 }; 73 opp-1209000000 { 74 opp-hz = /bits/ 64 <1209000000>; 75 opp-microvolt = <1034000>; 76 }; 77 opp-1300000000 { 78 opp-hz = /bits/ 64 <1300000000>; 79 opp-microvolt = <1057000>; 80 }; 81 opp-1508000000 { 82 opp-hz = /bits/ 64 <1508000000>; 83 opp-microvolt = <1109000>; 84 }; 85 opp-1703000000 { 86 opp-hz = /bits/ 64 <1703000000>; 87 opp-microvolt = <1125000>; 88 }; 89 }; 90 91 cluster1_opp: opp_table1 { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 opp-507000000 { 95 opp-hz = /bits/ 64 <507000000>; 96 opp-microvolt = <828000>; 97 }; 98 opp-702000000 { 99 opp-hz = /bits/ 64 <702000000>; 100 opp-microvolt = <867000>; 101 }; 102 opp-1001000000 { 103 opp-hz = /bits/ 64 <1001000000>; 104 opp-microvolt = <927000>; 105 }; 106 opp-1209000000 { 107 opp-hz = /bits/ 64 <1209000000>; 108 opp-microvolt = <968000>; 109 }; 110 opp-1404000000 { 111 opp-hz = /bits/ 64 <1404000000>; 112 opp-microvolt = <1007000>; 113 }; 114 opp-1612000000 { 115 opp-hz = /bits/ 64 <1612000000>; 116 opp-microvolt = <1049000>; 117 }; 118 opp-1807000000 { 119 opp-hz = /bits/ 64 <1807000000>; 120 opp-microvolt = <1089000>; 121 }; 122 opp-2106000000 { 123 opp-hz = /bits/ 64 <2106000000>; 124 opp-microvolt = <1125000>; 125 }; 126 }; 127 128 cpus { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 cpu-map { 133 cluster0 { 134 core0 { 135 cpu = <&cpu0>; 136 }; 137 core1 { 138 cpu = <&cpu1>; 139 }; 140 }; 141 142 cluster1 { 143 core0 { 144 cpu = <&cpu2>; 145 }; 146 core1 { 147 cpu = <&cpu3>; 148 }; 149 }; 150 }; 151 152 cpu0: cpu@0 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53"; 155 reg = <0x000>; 156 enable-method = "psci"; 157 cpu-idle-states = <&CPU_SLEEP_0>; 158 clocks = <&infracfg CLK_INFRA_CA53SEL>, 159 <&apmixedsys CLK_APMIXED_MAINPLL>; 160 clock-names = "cpu", "intermediate"; 161 operating-points-v2 = <&cluster0_opp>; 162 }; 163 164 cpu1: cpu@1 { 165 device_type = "cpu"; 166 compatible = "arm,cortex-a53"; 167 reg = <0x001>; 168 enable-method = "psci"; 169 cpu-idle-states = <&CPU_SLEEP_0>; 170 clocks = <&infracfg CLK_INFRA_CA53SEL>, 171 <&apmixedsys CLK_APMIXED_MAINPLL>; 172 clock-names = "cpu", "intermediate"; 173 operating-points-v2 = <&cluster0_opp>; 174 }; 175 176 cpu2: cpu@100 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a57"; 179 reg = <0x100>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_0>; 182 clocks = <&infracfg CLK_INFRA_CA57SEL>, 183 <&apmixedsys CLK_APMIXED_MAINPLL>; 184 clock-names = "cpu", "intermediate"; 185 operating-points-v2 = <&cluster1_opp>; 186 }; 187 188 cpu3: cpu@101 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a57"; 191 reg = <0x101>; 192 enable-method = "psci"; 193 cpu-idle-states = <&CPU_SLEEP_0>; 194 clocks = <&infracfg CLK_INFRA_CA57SEL>, 195 <&apmixedsys CLK_APMIXED_MAINPLL>; 196 clock-names = "cpu", "intermediate"; 197 operating-points-v2 = <&cluster1_opp>; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 CPU_SLEEP_0: cpu-sleep-0 { 204 compatible = "arm,idle-state"; 205 local-timer-stop; 206 entry-latency-us = <639>; 207 exit-latency-us = <680>; 208 min-residency-us = <1088>; 209 arm,psci-suspend-param = <0x0010000>; 210 }; 211 }; 212 }; 213 214 psci { 215 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 216 method = "smc"; 217 cpu_suspend = <0x84000001>; 218 cpu_off = <0x84000002>; 219 cpu_on = <0x84000003>; 220 }; 221 222 clk26m: oscillator@0 { 223 compatible = "fixed-clock"; 224 #clock-cells = <0>; 225 clock-frequency = <26000000>; 226 clock-output-names = "clk26m"; 227 }; 228 229 clk32k: oscillator@1 { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <32000>; 233 clock-output-names = "clk32k"; 234 }; 235 236 cpum_ck: oscillator@2 { 237 compatible = "fixed-clock"; 238 #clock-cells = <0>; 239 clock-frequency = <0>; 240 clock-output-names = "cpum_ck"; 241 }; 242 243 thermal-zones { 244 cpu_thermal: cpu_thermal { 245 polling-delay-passive = <1000>; /* milliseconds */ 246 polling-delay = <1000>; /* milliseconds */ 247 248 thermal-sensors = <&thermal>; 249 sustainable-power = <1500>; /* milliwatts */ 250 251 trips { 252 threshold: trip-point@0 { 253 temperature = <68000>; 254 hysteresis = <2000>; 255 type = "passive"; 256 }; 257 258 target: trip-point@1 { 259 temperature = <85000>; 260 hysteresis = <2000>; 261 type = "passive"; 262 }; 263 264 cpu_crit: cpu_crit@0 { 265 temperature = <115000>; 266 hysteresis = <2000>; 267 type = "critical"; 268 }; 269 }; 270 271 cooling-maps { 272 map@0 { 273 trip = <&target>; 274 cooling-device = <&cpu0 0 0>; 275 contribution = <3072>; 276 }; 277 map@1 { 278 trip = <&target>; 279 cooling-device = <&cpu2 0 0>; 280 contribution = <1024>; 281 }; 282 }; 283 }; 284 }; 285 286 reserved-memory { 287 #address-cells = <2>; 288 #size-cells = <2>; 289 ranges; 290 vpu_dma_reserved: vpu_dma_mem_region { 291 compatible = "shared-dma-pool"; 292 reg = <0 0xb7000000 0 0x500000>; 293 alignment = <0x1000>; 294 no-map; 295 }; 296 }; 297 298 timer { 299 compatible = "arm,armv8-timer"; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_PPI 13 302 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 303 <GIC_PPI 14 304 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 305 <GIC_PPI 11 306 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 307 <GIC_PPI 10 308 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 309 }; 310 311 soc { 312 #address-cells = <2>; 313 #size-cells = <2>; 314 compatible = "simple-bus"; 315 ranges; 316 317 topckgen: clock-controller@10000000 { 318 compatible = "mediatek,mt8173-topckgen"; 319 reg = <0 0x10000000 0 0x1000>; 320 #clock-cells = <1>; 321 }; 322 323 infracfg: power-controller@10001000 { 324 compatible = "mediatek,mt8173-infracfg", "syscon"; 325 reg = <0 0x10001000 0 0x1000>; 326 #clock-cells = <1>; 327 #reset-cells = <1>; 328 }; 329 330 pericfg: power-controller@10003000 { 331 compatible = "mediatek,mt8173-pericfg", "syscon"; 332 reg = <0 0x10003000 0 0x1000>; 333 #clock-cells = <1>; 334 #reset-cells = <1>; 335 }; 336 337 syscfg_pctl_a: syscfg_pctl_a@10005000 { 338 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 339 reg = <0 0x10005000 0 0x1000>; 340 }; 341 342 pio: pinctrl@0x10005000 { 343 compatible = "mediatek,mt8173-pinctrl"; 344 reg = <0 0x1000b000 0 0x1000>; 345 mediatek,pctl-regmap = <&syscfg_pctl_a>; 346 pins-are-numbered; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 354 355 hdmi_pin: xxx { 356 357 /*hdmi htplg pin*/ 358 pins1 { 359 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 360 input-enable; 361 bias-pull-down; 362 }; 363 }; 364 365 i2c0_pins_a: i2c0 { 366 pins1 { 367 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 368 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 369 bias-disable; 370 }; 371 }; 372 373 i2c1_pins_a: i2c1 { 374 pins1 { 375 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 376 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 377 bias-disable; 378 }; 379 }; 380 381 i2c2_pins_a: i2c2 { 382 pins1 { 383 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 384 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 385 bias-disable; 386 }; 387 }; 388 389 i2c3_pins_a: i2c3 { 390 pins1 { 391 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 392 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 393 bias-disable; 394 }; 395 }; 396 397 i2c4_pins_a: i2c4 { 398 pins1 { 399 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 400 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 401 bias-disable; 402 }; 403 }; 404 405 i2c6_pins_a: i2c6 { 406 pins1 { 407 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 408 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 409 bias-disable; 410 }; 411 }; 412 }; 413 414 scpsys: scpsys@10006000 { 415 compatible = "mediatek,mt8173-scpsys"; 416 #power-domain-cells = <1>; 417 reg = <0 0x10006000 0 0x1000>; 418 clocks = <&clk26m>, 419 <&topckgen CLK_TOP_MM_SEL>, 420 <&topckgen CLK_TOP_VENC_SEL>, 421 <&topckgen CLK_TOP_VENC_LT_SEL>; 422 clock-names = "mfg", "mm", "venc", "venc_lt"; 423 infracfg = <&infracfg>; 424 }; 425 426 watchdog: watchdog@10007000 { 427 compatible = "mediatek,mt8173-wdt", 428 "mediatek,mt6589-wdt"; 429 reg = <0 0x10007000 0 0x100>; 430 }; 431 432 timer: timer@10008000 { 433 compatible = "mediatek,mt8173-timer", 434 "mediatek,mt6577-timer"; 435 reg = <0 0x10008000 0 0x1000>; 436 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 437 clocks = <&infracfg CLK_INFRA_CLK_13M>, 438 <&topckgen CLK_TOP_RTC_SEL>; 439 }; 440 441 pwrap: pwrap@1000d000 { 442 compatible = "mediatek,mt8173-pwrap"; 443 reg = <0 0x1000d000 0 0x1000>; 444 reg-names = "pwrap"; 445 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 446 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 447 reset-names = "pwrap"; 448 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 449 clock-names = "spi", "wrap"; 450 }; 451 452 cec: cec@10013000 { 453 compatible = "mediatek,mt8173-cec"; 454 reg = <0 0x10013000 0 0xbc>; 455 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 456 clocks = <&infracfg CLK_INFRA_CEC>; 457 status = "disabled"; 458 }; 459 460 vpu: vpu@10020000 { 461 compatible = "mediatek,mt8173-vpu"; 462 reg = <0 0x10020000 0 0x30000>, 463 <0 0x10050000 0 0x100>; 464 reg-names = "tcm", "cfg_reg"; 465 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&topckgen CLK_TOP_SCP_SEL>; 467 clock-names = "main"; 468 memory-region = <&vpu_dma_reserved>; 469 }; 470 471 sysirq: intpol-controller@10200620 { 472 compatible = "mediatek,mt8173-sysirq", 473 "mediatek,mt6577-sysirq"; 474 interrupt-controller; 475 #interrupt-cells = <3>; 476 interrupt-parent = <&gic>; 477 reg = <0 0x10200620 0 0x20>; 478 }; 479 480 iommu: iommu@10205000 { 481 compatible = "mediatek,mt8173-m4u"; 482 reg = <0 0x10205000 0 0x1000>; 483 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 484 clocks = <&infracfg CLK_INFRA_M4U>; 485 clock-names = "bclk"; 486 mediatek,larbs = <&larb0 &larb1 &larb2 487 &larb3 &larb4 &larb5>; 488 #iommu-cells = <1>; 489 }; 490 491 efuse: efuse@10206000 { 492 compatible = "mediatek,mt8173-efuse"; 493 reg = <0 0x10206000 0 0x1000>; 494 #address-cells = <1>; 495 #size-cells = <1>; 496 thermal_calibration: calib@528 { 497 reg = <0x528 0xc>; 498 }; 499 }; 500 501 apmixedsys: clock-controller@10209000 { 502 compatible = "mediatek,mt8173-apmixedsys"; 503 reg = <0 0x10209000 0 0x1000>; 504 #clock-cells = <1>; 505 }; 506 507 hdmi_phy: hdmi-phy@10209100 { 508 compatible = "mediatek,mt8173-hdmi-phy"; 509 reg = <0 0x10209100 0 0x24>; 510 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 511 clock-names = "pll_ref"; 512 clock-output-names = "hdmitx_dig_cts"; 513 mediatek,ibias = <0xa>; 514 mediatek,ibias_up = <0x1c>; 515 #clock-cells = <0>; 516 #phy-cells = <0>; 517 status = "disabled"; 518 }; 519 520 mipi_tx0: mipi-dphy@10215000 { 521 compatible = "mediatek,mt8173-mipi-tx"; 522 reg = <0 0x10215000 0 0x1000>; 523 clocks = <&clk26m>; 524 clock-output-names = "mipi_tx0_pll"; 525 #clock-cells = <0>; 526 #phy-cells = <0>; 527 status = "disabled"; 528 }; 529 530 mipi_tx1: mipi-dphy@10216000 { 531 compatible = "mediatek,mt8173-mipi-tx"; 532 reg = <0 0x10216000 0 0x1000>; 533 clocks = <&clk26m>; 534 clock-output-names = "mipi_tx1_pll"; 535 #clock-cells = <0>; 536 #phy-cells = <0>; 537 status = "disabled"; 538 }; 539 540 gic: interrupt-controller@10220000 { 541 compatible = "arm,gic-400"; 542 #interrupt-cells = <3>; 543 interrupt-parent = <&gic>; 544 interrupt-controller; 545 reg = <0 0x10221000 0 0x1000>, 546 <0 0x10222000 0 0x2000>, 547 <0 0x10224000 0 0x2000>, 548 <0 0x10226000 0 0x2000>; 549 interrupts = <GIC_PPI 9 550 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 551 }; 552 553 auxadc: auxadc@11001000 { 554 compatible = "mediatek,mt8173-auxadc"; 555 reg = <0 0x11001000 0 0x1000>; 556 clocks = <&pericfg CLK_PERI_AUXADC>; 557 clock-names = "main"; 558 #io-channel-cells = <1>; 559 }; 560 561 uart0: serial@11002000 { 562 compatible = "mediatek,mt8173-uart", 563 "mediatek,mt6577-uart"; 564 reg = <0 0x11002000 0 0x400>; 565 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 566 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 567 clock-names = "baud", "bus"; 568 status = "disabled"; 569 }; 570 571 uart1: serial@11003000 { 572 compatible = "mediatek,mt8173-uart", 573 "mediatek,mt6577-uart"; 574 reg = <0 0x11003000 0 0x400>; 575 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 576 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 577 clock-names = "baud", "bus"; 578 status = "disabled"; 579 }; 580 581 uart2: serial@11004000 { 582 compatible = "mediatek,mt8173-uart", 583 "mediatek,mt6577-uart"; 584 reg = <0 0x11004000 0 0x400>; 585 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 586 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 587 clock-names = "baud", "bus"; 588 status = "disabled"; 589 }; 590 591 uart3: serial@11005000 { 592 compatible = "mediatek,mt8173-uart", 593 "mediatek,mt6577-uart"; 594 reg = <0 0x11005000 0 0x400>; 595 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 596 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 597 clock-names = "baud", "bus"; 598 status = "disabled"; 599 }; 600 601 i2c0: i2c@11007000 { 602 compatible = "mediatek,mt8173-i2c"; 603 reg = <0 0x11007000 0 0x70>, 604 <0 0x11000100 0 0x80>; 605 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 606 clock-div = <16>; 607 clocks = <&pericfg CLK_PERI_I2C0>, 608 <&pericfg CLK_PERI_AP_DMA>; 609 clock-names = "main", "dma"; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&i2c0_pins_a>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 i2c1: i2c@11008000 { 618 compatible = "mediatek,mt8173-i2c"; 619 reg = <0 0x11008000 0 0x70>, 620 <0 0x11000180 0 0x80>; 621 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 622 clock-div = <16>; 623 clocks = <&pericfg CLK_PERI_I2C1>, 624 <&pericfg CLK_PERI_AP_DMA>; 625 clock-names = "main", "dma"; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&i2c1_pins_a>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 i2c2: i2c@11009000 { 634 compatible = "mediatek,mt8173-i2c"; 635 reg = <0 0x11009000 0 0x70>, 636 <0 0x11000200 0 0x80>; 637 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 638 clock-div = <16>; 639 clocks = <&pericfg CLK_PERI_I2C2>, 640 <&pericfg CLK_PERI_AP_DMA>; 641 clock-names = "main", "dma"; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&i2c2_pins_a>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 status = "disabled"; 647 }; 648 649 spi: spi@1100a000 { 650 compatible = "mediatek,mt8173-spi"; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 reg = <0 0x1100a000 0 0x1000>; 654 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 655 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 656 <&topckgen CLK_TOP_SPI_SEL>, 657 <&pericfg CLK_PERI_SPI0>; 658 clock-names = "parent-clk", "sel-clk", "spi-clk"; 659 status = "disabled"; 660 }; 661 662 thermal: thermal@1100b000 { 663 #thermal-sensor-cells = <0>; 664 compatible = "mediatek,mt8173-thermal"; 665 reg = <0 0x1100b000 0 0x1000>; 666 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 667 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 668 clock-names = "therm", "auxadc"; 669 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 670 mediatek,auxadc = <&auxadc>; 671 mediatek,apmixedsys = <&apmixedsys>; 672 nvmem-cells = <&thermal_calibration>; 673 nvmem-cell-names = "calibration-data"; 674 }; 675 676 nor_flash: spi@1100d000 { 677 compatible = "mediatek,mt8173-nor"; 678 reg = <0 0x1100d000 0 0xe0>; 679 clocks = <&pericfg CLK_PERI_SPI>, 680 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 681 clock-names = "spi", "sf"; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 status = "disabled"; 685 }; 686 687 i2c3: i2c@11010000 { 688 compatible = "mediatek,mt8173-i2c"; 689 reg = <0 0x11010000 0 0x70>, 690 <0 0x11000280 0 0x80>; 691 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 692 clock-div = <16>; 693 clocks = <&pericfg CLK_PERI_I2C3>, 694 <&pericfg CLK_PERI_AP_DMA>; 695 clock-names = "main", "dma"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&i2c3_pins_a>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 i2c4: i2c@11011000 { 704 compatible = "mediatek,mt8173-i2c"; 705 reg = <0 0x11011000 0 0x70>, 706 <0 0x11000300 0 0x80>; 707 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 708 clock-div = <16>; 709 clocks = <&pericfg CLK_PERI_I2C4>, 710 <&pericfg CLK_PERI_AP_DMA>; 711 clock-names = "main", "dma"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&i2c4_pins_a>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 status = "disabled"; 717 }; 718 719 hdmiddc0: i2c@11012000 { 720 compatible = "mediatek,mt8173-hdmi-ddc"; 721 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 722 reg = <0 0x11012000 0 0x1C>; 723 clocks = <&pericfg CLK_PERI_I2C5>; 724 clock-names = "ddc-i2c"; 725 }; 726 727 i2c6: i2c@11013000 { 728 compatible = "mediatek,mt8173-i2c"; 729 reg = <0 0x11013000 0 0x70>, 730 <0 0x11000080 0 0x80>; 731 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 732 clock-div = <16>; 733 clocks = <&pericfg CLK_PERI_I2C6>, 734 <&pericfg CLK_PERI_AP_DMA>; 735 clock-names = "main", "dma"; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&i2c6_pins_a>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 status = "disabled"; 741 }; 742 743 afe: audio-controller@11220000 { 744 compatible = "mediatek,mt8173-afe-pcm"; 745 reg = <0 0x11220000 0 0x1000>; 746 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 747 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 748 clocks = <&infracfg CLK_INFRA_AUDIO>, 749 <&topckgen CLK_TOP_AUDIO_SEL>, 750 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 751 <&topckgen CLK_TOP_APLL1_DIV0>, 752 <&topckgen CLK_TOP_APLL2_DIV0>, 753 <&topckgen CLK_TOP_I2S0_M_SEL>, 754 <&topckgen CLK_TOP_I2S1_M_SEL>, 755 <&topckgen CLK_TOP_I2S2_M_SEL>, 756 <&topckgen CLK_TOP_I2S3_M_SEL>, 757 <&topckgen CLK_TOP_I2S3_B_SEL>; 758 clock-names = "infra_sys_audio_clk", 759 "top_pdn_audio", 760 "top_pdn_aud_intbus", 761 "bck0", 762 "bck1", 763 "i2s0_m", 764 "i2s1_m", 765 "i2s2_m", 766 "i2s3_m", 767 "i2s3_b"; 768 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 769 <&topckgen CLK_TOP_AUD_2_SEL>; 770 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 771 <&topckgen CLK_TOP_APLL2>; 772 }; 773 774 mmc0: mmc@11230000 { 775 compatible = "mediatek,mt8173-mmc"; 776 reg = <0 0x11230000 0 0x1000>; 777 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 778 clocks = <&pericfg CLK_PERI_MSDC30_0>, 779 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 780 clock-names = "source", "hclk"; 781 status = "disabled"; 782 }; 783 784 mmc1: mmc@11240000 { 785 compatible = "mediatek,mt8173-mmc"; 786 reg = <0 0x11240000 0 0x1000>; 787 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 788 clocks = <&pericfg CLK_PERI_MSDC30_1>, 789 <&topckgen CLK_TOP_AXI_SEL>; 790 clock-names = "source", "hclk"; 791 status = "disabled"; 792 }; 793 794 mmc2: mmc@11250000 { 795 compatible = "mediatek,mt8173-mmc"; 796 reg = <0 0x11250000 0 0x1000>; 797 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 798 clocks = <&pericfg CLK_PERI_MSDC30_2>, 799 <&topckgen CLK_TOP_AXI_SEL>; 800 clock-names = "source", "hclk"; 801 status = "disabled"; 802 }; 803 804 mmc3: mmc@11260000 { 805 compatible = "mediatek,mt8173-mmc"; 806 reg = <0 0x11260000 0 0x1000>; 807 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 808 clocks = <&pericfg CLK_PERI_MSDC30_3>, 809 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 810 clock-names = "source", "hclk"; 811 status = "disabled"; 812 }; 813 814 ssusb: usb@11271000 { 815 compatible = "mediatek,mt8173-mtu3"; 816 reg = <0 0x11271000 0 0x3000>, 817 <0 0x11280700 0 0x0100>; 818 reg-names = "mac", "ippc"; 819 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 820 phys = <&u2port0 PHY_TYPE_USB2>, 821 <&u3port0 PHY_TYPE_USB3>, 822 <&u2port1 PHY_TYPE_USB2>; 823 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 824 clocks = <&topckgen CLK_TOP_USB30_SEL>, 825 <&clk26m>, 826 <&pericfg CLK_PERI_USB0>, 827 <&pericfg CLK_PERI_USB1>; 828 clock-names = "sys_ck", 829 "ref_ck", 830 "wakeup_deb_p0", 831 "wakeup_deb_p1"; 832 mediatek,syscon-wakeup = <&pericfg>; 833 #address-cells = <2>; 834 #size-cells = <2>; 835 ranges; 836 status = "disabled"; 837 838 usb_host: xhci@11270000 { 839 compatible = "mediatek,mt8173-xhci"; 840 reg = <0 0x11270000 0 0x1000>; 841 reg-names = "mac"; 842 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 843 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 844 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 845 clock-names = "sys_ck", "ref_ck"; 846 status = "disabled"; 847 }; 848 }; 849 850 u3phy: usb-phy@11290000 { 851 compatible = "mediatek,mt8173-u3phy"; 852 reg = <0 0x11290000 0 0x800>; 853 #address-cells = <2>; 854 #size-cells = <2>; 855 ranges; 856 status = "okay"; 857 858 u2port0: usb-phy@11290800 { 859 reg = <0 0x11290800 0 0x100>; 860 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 861 clock-names = "ref"; 862 #phy-cells = <1>; 863 status = "okay"; 864 }; 865 866 u3port0: usb-phy@11290900 { 867 reg = <0 0x11290900 0 0x700>; 868 clocks = <&clk26m>; 869 clock-names = "ref"; 870 #phy-cells = <1>; 871 status = "okay"; 872 }; 873 874 u2port1: usb-phy@11291000 { 875 reg = <0 0x11291000 0 0x100>; 876 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 877 clock-names = "ref"; 878 #phy-cells = <1>; 879 status = "okay"; 880 }; 881 }; 882 883 mmsys: clock-controller@14000000 { 884 compatible = "mediatek,mt8173-mmsys", "syscon"; 885 reg = <0 0x14000000 0 0x1000>; 886 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 887 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 888 assigned-clock-rates = <400000000>; 889 #clock-cells = <1>; 890 }; 891 892 mdp_rdma0: rdma@14001000 { 893 compatible = "mediatek,mt8173-mdp-rdma", 894 "mediatek,mt8173-mdp"; 895 reg = <0 0x14001000 0 0x1000>; 896 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 897 <&mmsys CLK_MM_MUTEX_32K>; 898 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 899 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 900 mediatek,larb = <&larb0>; 901 mediatek,vpu = <&vpu>; 902 }; 903 904 mdp_rdma1: rdma@14002000 { 905 compatible = "mediatek,mt8173-mdp-rdma"; 906 reg = <0 0x14002000 0 0x1000>; 907 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 908 <&mmsys CLK_MM_MUTEX_32K>; 909 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 910 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 911 mediatek,larb = <&larb4>; 912 }; 913 914 mdp_rsz0: rsz@14003000 { 915 compatible = "mediatek,mt8173-mdp-rsz"; 916 reg = <0 0x14003000 0 0x1000>; 917 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 918 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 919 }; 920 921 mdp_rsz1: rsz@14004000 { 922 compatible = "mediatek,mt8173-mdp-rsz"; 923 reg = <0 0x14004000 0 0x1000>; 924 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 925 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 926 }; 927 928 mdp_rsz2: rsz@14005000 { 929 compatible = "mediatek,mt8173-mdp-rsz"; 930 reg = <0 0x14005000 0 0x1000>; 931 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 932 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 933 }; 934 935 mdp_wdma0: wdma@14006000 { 936 compatible = "mediatek,mt8173-mdp-wdma"; 937 reg = <0 0x14006000 0 0x1000>; 938 clocks = <&mmsys CLK_MM_MDP_WDMA>; 939 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 940 iommus = <&iommu M4U_PORT_MDP_WDMA>; 941 mediatek,larb = <&larb0>; 942 }; 943 944 mdp_wrot0: wrot@14007000 { 945 compatible = "mediatek,mt8173-mdp-wrot"; 946 reg = <0 0x14007000 0 0x1000>; 947 clocks = <&mmsys CLK_MM_MDP_WROT0>; 948 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 949 iommus = <&iommu M4U_PORT_MDP_WROT0>; 950 mediatek,larb = <&larb0>; 951 }; 952 953 mdp_wrot1: wrot@14008000 { 954 compatible = "mediatek,mt8173-mdp-wrot"; 955 reg = <0 0x14008000 0 0x1000>; 956 clocks = <&mmsys CLK_MM_MDP_WROT1>; 957 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 958 iommus = <&iommu M4U_PORT_MDP_WROT1>; 959 mediatek,larb = <&larb4>; 960 }; 961 962 ovl0: ovl@1400c000 { 963 compatible = "mediatek,mt8173-disp-ovl"; 964 reg = <0 0x1400c000 0 0x1000>; 965 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 966 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 967 clocks = <&mmsys CLK_MM_DISP_OVL0>; 968 iommus = <&iommu M4U_PORT_DISP_OVL0>; 969 mediatek,larb = <&larb0>; 970 }; 971 972 ovl1: ovl@1400d000 { 973 compatible = "mediatek,mt8173-disp-ovl"; 974 reg = <0 0x1400d000 0 0x1000>; 975 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 976 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 977 clocks = <&mmsys CLK_MM_DISP_OVL1>; 978 iommus = <&iommu M4U_PORT_DISP_OVL1>; 979 mediatek,larb = <&larb4>; 980 }; 981 982 rdma0: rdma@1400e000 { 983 compatible = "mediatek,mt8173-disp-rdma"; 984 reg = <0 0x1400e000 0 0x1000>; 985 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 986 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 987 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 988 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 989 mediatek,larb = <&larb0>; 990 }; 991 992 rdma1: rdma@1400f000 { 993 compatible = "mediatek,mt8173-disp-rdma"; 994 reg = <0 0x1400f000 0 0x1000>; 995 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 996 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 997 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 998 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 999 mediatek,larb = <&larb4>; 1000 }; 1001 1002 rdma2: rdma@14010000 { 1003 compatible = "mediatek,mt8173-disp-rdma"; 1004 reg = <0 0x14010000 0 0x1000>; 1005 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1006 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1007 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1008 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1009 mediatek,larb = <&larb4>; 1010 }; 1011 1012 wdma0: wdma@14011000 { 1013 compatible = "mediatek,mt8173-disp-wdma"; 1014 reg = <0 0x14011000 0 0x1000>; 1015 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1016 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1017 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1018 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1019 mediatek,larb = <&larb0>; 1020 }; 1021 1022 wdma1: wdma@14012000 { 1023 compatible = "mediatek,mt8173-disp-wdma"; 1024 reg = <0 0x14012000 0 0x1000>; 1025 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1026 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1027 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1028 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1029 mediatek,larb = <&larb4>; 1030 }; 1031 1032 color0: color@14013000 { 1033 compatible = "mediatek,mt8173-disp-color"; 1034 reg = <0 0x14013000 0 0x1000>; 1035 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1036 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1037 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1038 }; 1039 1040 color1: color@14014000 { 1041 compatible = "mediatek,mt8173-disp-color"; 1042 reg = <0 0x14014000 0 0x1000>; 1043 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1044 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1045 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1046 }; 1047 1048 aal@14015000 { 1049 compatible = "mediatek,mt8173-disp-aal"; 1050 reg = <0 0x14015000 0 0x1000>; 1051 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1052 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1053 clocks = <&mmsys CLK_MM_DISP_AAL>; 1054 }; 1055 1056 gamma@14016000 { 1057 compatible = "mediatek,mt8173-disp-gamma"; 1058 reg = <0 0x14016000 0 0x1000>; 1059 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1060 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1061 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1062 }; 1063 1064 merge@14017000 { 1065 compatible = "mediatek,mt8173-disp-merge"; 1066 reg = <0 0x14017000 0 0x1000>; 1067 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1068 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1069 }; 1070 1071 split0: split@14018000 { 1072 compatible = "mediatek,mt8173-disp-split"; 1073 reg = <0 0x14018000 0 0x1000>; 1074 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1075 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1076 }; 1077 1078 split1: split@14019000 { 1079 compatible = "mediatek,mt8173-disp-split"; 1080 reg = <0 0x14019000 0 0x1000>; 1081 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1082 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1083 }; 1084 1085 ufoe@1401a000 { 1086 compatible = "mediatek,mt8173-disp-ufoe"; 1087 reg = <0 0x1401a000 0 0x1000>; 1088 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1089 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1090 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1091 }; 1092 1093 dsi0: dsi@1401b000 { 1094 compatible = "mediatek,mt8173-dsi"; 1095 reg = <0 0x1401b000 0 0x1000>; 1096 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1097 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1098 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1099 <&mmsys CLK_MM_DSI0_DIGITAL>, 1100 <&mipi_tx0>; 1101 clock-names = "engine", "digital", "hs"; 1102 phys = <&mipi_tx0>; 1103 phy-names = "dphy"; 1104 status = "disabled"; 1105 }; 1106 1107 dsi1: dsi@1401c000 { 1108 compatible = "mediatek,mt8173-dsi"; 1109 reg = <0 0x1401c000 0 0x1000>; 1110 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1111 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1112 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1113 <&mmsys CLK_MM_DSI1_DIGITAL>, 1114 <&mipi_tx1>; 1115 clock-names = "engine", "digital", "hs"; 1116 phy = <&mipi_tx1>; 1117 phy-names = "dphy"; 1118 status = "disabled"; 1119 }; 1120 1121 dpi0: dpi@1401d000 { 1122 compatible = "mediatek,mt8173-dpi"; 1123 reg = <0 0x1401d000 0 0x1000>; 1124 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1125 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1126 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1127 <&mmsys CLK_MM_DPI_ENGINE>, 1128 <&apmixedsys CLK_APMIXED_TVDPLL>; 1129 clock-names = "pixel", "engine", "pll"; 1130 status = "disabled"; 1131 1132 port { 1133 dpi0_out: endpoint { 1134 remote-endpoint = <&hdmi0_in>; 1135 }; 1136 }; 1137 }; 1138 1139 pwm0: pwm@1401e000 { 1140 compatible = "mediatek,mt8173-disp-pwm", 1141 "mediatek,mt6595-disp-pwm"; 1142 reg = <0 0x1401e000 0 0x1000>; 1143 #pwm-cells = <2>; 1144 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1145 <&mmsys CLK_MM_DISP_PWM0MM>; 1146 clock-names = "main", "mm"; 1147 status = "disabled"; 1148 }; 1149 1150 pwm1: pwm@1401f000 { 1151 compatible = "mediatek,mt8173-disp-pwm", 1152 "mediatek,mt6595-disp-pwm"; 1153 reg = <0 0x1401f000 0 0x1000>; 1154 #pwm-cells = <2>; 1155 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1156 <&mmsys CLK_MM_DISP_PWM1MM>; 1157 clock-names = "main", "mm"; 1158 status = "disabled"; 1159 }; 1160 1161 mutex: mutex@14020000 { 1162 compatible = "mediatek,mt8173-disp-mutex"; 1163 reg = <0 0x14020000 0 0x1000>; 1164 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1165 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1166 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1167 }; 1168 1169 larb0: larb@14021000 { 1170 compatible = "mediatek,mt8173-smi-larb"; 1171 reg = <0 0x14021000 0 0x1000>; 1172 mediatek,smi = <&smi_common>; 1173 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1174 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1175 <&mmsys CLK_MM_SMI_LARB0>; 1176 clock-names = "apb", "smi"; 1177 }; 1178 1179 smi_common: smi@14022000 { 1180 compatible = "mediatek,mt8173-smi-common"; 1181 reg = <0 0x14022000 0 0x1000>; 1182 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1183 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1184 <&mmsys CLK_MM_SMI_COMMON>; 1185 clock-names = "apb", "smi"; 1186 }; 1187 1188 od@14023000 { 1189 compatible = "mediatek,mt8173-disp-od"; 1190 reg = <0 0x14023000 0 0x1000>; 1191 clocks = <&mmsys CLK_MM_DISP_OD>; 1192 }; 1193 1194 hdmi0: hdmi@14025000 { 1195 compatible = "mediatek,mt8173-hdmi"; 1196 reg = <0 0x14025000 0 0x400>; 1197 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1198 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1199 <&mmsys CLK_MM_HDMI_PLLCK>, 1200 <&mmsys CLK_MM_HDMI_AUDIO>, 1201 <&mmsys CLK_MM_HDMI_SPDIF>; 1202 clock-names = "pixel", "pll", "bclk", "spdif"; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&hdmi_pin>; 1205 phys = <&hdmi_phy>; 1206 phy-names = "hdmi"; 1207 mediatek,syscon-hdmi = <&mmsys 0x900>; 1208 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1209 assigned-clock-parents = <&hdmi_phy>; 1210 status = "disabled"; 1211 1212 ports { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 port@0 { 1217 reg = <0>; 1218 1219 hdmi0_in: endpoint { 1220 remote-endpoint = <&dpi0_out>; 1221 }; 1222 }; 1223 }; 1224 }; 1225 1226 larb4: larb@14027000 { 1227 compatible = "mediatek,mt8173-smi-larb"; 1228 reg = <0 0x14027000 0 0x1000>; 1229 mediatek,smi = <&smi_common>; 1230 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1231 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1232 <&mmsys CLK_MM_SMI_LARB4>; 1233 clock-names = "apb", "smi"; 1234 }; 1235 1236 imgsys: clock-controller@15000000 { 1237 compatible = "mediatek,mt8173-imgsys", "syscon"; 1238 reg = <0 0x15000000 0 0x1000>; 1239 #clock-cells = <1>; 1240 }; 1241 1242 larb2: larb@15001000 { 1243 compatible = "mediatek,mt8173-smi-larb"; 1244 reg = <0 0x15001000 0 0x1000>; 1245 mediatek,smi = <&smi_common>; 1246 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1247 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1248 <&imgsys CLK_IMG_LARB2_SMI>; 1249 clock-names = "apb", "smi"; 1250 }; 1251 1252 vdecsys: clock-controller@16000000 { 1253 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1254 reg = <0 0x16000000 0 0x1000>; 1255 #clock-cells = <1>; 1256 }; 1257 1258 vcodec_dec: vcodec@16000000 { 1259 compatible = "mediatek,mt8173-vcodec-dec"; 1260 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1261 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1262 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1263 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1264 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1265 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1266 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1267 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1268 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1269 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1270 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1271 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1272 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1273 mediatek,larb = <&larb1>; 1274 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1275 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1276 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1277 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1278 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1279 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1280 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1281 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1282 mediatek,vpu = <&vpu>; 1283 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1284 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1285 <&topckgen CLK_TOP_UNIVPLL_D2>, 1286 <&topckgen CLK_TOP_CCI400_SEL>, 1287 <&topckgen CLK_TOP_VDEC_SEL>, 1288 <&topckgen CLK_TOP_VCODECPLL>, 1289 <&apmixedsys CLK_APMIXED_VENCPLL>, 1290 <&topckgen CLK_TOP_VENC_LT_SEL>, 1291 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1292 clock-names = "vcodecpll", 1293 "univpll_d2", 1294 "clk_cci400_sel", 1295 "vdec_sel", 1296 "vdecpll", 1297 "vencpll", 1298 "venc_lt_sel", 1299 "vdec_bus_clk_src"; 1300 }; 1301 1302 larb1: larb@16010000 { 1303 compatible = "mediatek,mt8173-smi-larb"; 1304 reg = <0 0x16010000 0 0x1000>; 1305 mediatek,smi = <&smi_common>; 1306 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1307 clocks = <&vdecsys CLK_VDEC_CKEN>, 1308 <&vdecsys CLK_VDEC_LARB_CKEN>; 1309 clock-names = "apb", "smi"; 1310 }; 1311 1312 vencsys: clock-controller@18000000 { 1313 compatible = "mediatek,mt8173-vencsys", "syscon"; 1314 reg = <0 0x18000000 0 0x1000>; 1315 #clock-cells = <1>; 1316 }; 1317 1318 larb3: larb@18001000 { 1319 compatible = "mediatek,mt8173-smi-larb"; 1320 reg = <0 0x18001000 0 0x1000>; 1321 mediatek,smi = <&smi_common>; 1322 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1323 clocks = <&vencsys CLK_VENC_CKE1>, 1324 <&vencsys CLK_VENC_CKE0>; 1325 clock-names = "apb", "smi"; 1326 }; 1327 1328 vcodec_enc: vcodec@18002000 { 1329 compatible = "mediatek,mt8173-vcodec-enc"; 1330 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1331 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1332 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1333 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1334 mediatek,larb = <&larb3>, 1335 <&larb5>; 1336 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1337 <&iommu M4U_PORT_VENC_REC>, 1338 <&iommu M4U_PORT_VENC_BSDMA>, 1339 <&iommu M4U_PORT_VENC_SV_COMV>, 1340 <&iommu M4U_PORT_VENC_RD_COMV>, 1341 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1342 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1343 <&iommu M4U_PORT_VENC_REF_LUMA>, 1344 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1345 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1346 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1347 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1348 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1349 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1350 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1351 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1352 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1353 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1354 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1355 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1356 mediatek,vpu = <&vpu>; 1357 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1358 <&topckgen CLK_TOP_VENC_SEL>, 1359 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1360 <&topckgen CLK_TOP_VENC_LT_SEL>; 1361 clock-names = "venc_sel_src", 1362 "venc_sel", 1363 "venc_lt_sel_src", 1364 "venc_lt_sel"; 1365 }; 1366 1367 vencltsys: clock-controller@19000000 { 1368 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1369 reg = <0 0x19000000 0 0x1000>; 1370 #clock-cells = <1>; 1371 }; 1372 1373 larb5: larb@19001000 { 1374 compatible = "mediatek,mt8173-smi-larb"; 1375 reg = <0 0x19001000 0 0x1000>; 1376 mediatek,smi = <&smi_common>; 1377 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1378 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1379 <&vencltsys CLK_VENCLT_CKE0>; 1380 clock-names = "apb", "smi"; 1381 }; 1382 }; 1383}; 1384 1385