1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include "mt8173-pinfunc.h" 23 24/ { 25 compatible = "mediatek,mt8173"; 26 interrupt-parent = <&sysirq>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 ovl0 = &ovl0; 32 ovl1 = &ovl1; 33 rdma0 = &rdma0; 34 rdma1 = &rdma1; 35 rdma2 = &rdma2; 36 wdma0 = &wdma0; 37 wdma1 = &wdma1; 38 color0 = &color0; 39 color1 = &color1; 40 split0 = &split0; 41 split1 = &split1; 42 dpi0 = &dpi0; 43 dsi0 = &dsi0; 44 dsi1 = &dsi1; 45 mdp_rdma0 = &mdp_rdma0; 46 mdp_rdma1 = &mdp_rdma1; 47 mdp_rsz0 = &mdp_rsz0; 48 mdp_rsz1 = &mdp_rsz1; 49 mdp_rsz2 = &mdp_rsz2; 50 mdp_wdma0 = &mdp_wdma0; 51 mdp_wrot0 = &mdp_wrot0; 52 mdp_wrot1 = &mdp_wrot1; 53 }; 54 55 cluster0_opp: opp_table0 { 56 compatible = "operating-points-v2"; 57 opp-shared; 58 opp-507000000 { 59 opp-hz = /bits/ 64 <507000000>; 60 opp-microvolt = <859000>; 61 }; 62 opp-702000000 { 63 opp-hz = /bits/ 64 <702000000>; 64 opp-microvolt = <908000>; 65 }; 66 opp-1001000000 { 67 opp-hz = /bits/ 64 <1001000000>; 68 opp-microvolt = <983000>; 69 }; 70 opp-1105000000 { 71 opp-hz = /bits/ 64 <1105000000>; 72 opp-microvolt = <1009000>; 73 }; 74 opp-1209000000 { 75 opp-hz = /bits/ 64 <1209000000>; 76 opp-microvolt = <1034000>; 77 }; 78 opp-1300000000 { 79 opp-hz = /bits/ 64 <1300000000>; 80 opp-microvolt = <1057000>; 81 }; 82 opp-1508000000 { 83 opp-hz = /bits/ 64 <1508000000>; 84 opp-microvolt = <1109000>; 85 }; 86 opp-1703000000 { 87 opp-hz = /bits/ 64 <1703000000>; 88 opp-microvolt = <1125000>; 89 }; 90 }; 91 92 cluster1_opp: opp_table1 { 93 compatible = "operating-points-v2"; 94 opp-shared; 95 opp-507000000 { 96 opp-hz = /bits/ 64 <507000000>; 97 opp-microvolt = <828000>; 98 }; 99 opp-702000000 { 100 opp-hz = /bits/ 64 <702000000>; 101 opp-microvolt = <867000>; 102 }; 103 opp-1001000000 { 104 opp-hz = /bits/ 64 <1001000000>; 105 opp-microvolt = <927000>; 106 }; 107 opp-1209000000 { 108 opp-hz = /bits/ 64 <1209000000>; 109 opp-microvolt = <968000>; 110 }; 111 opp-1404000000 { 112 opp-hz = /bits/ 64 <1404000000>; 113 opp-microvolt = <1007000>; 114 }; 115 opp-1612000000 { 116 opp-hz = /bits/ 64 <1612000000>; 117 opp-microvolt = <1049000>; 118 }; 119 opp-1807000000 { 120 opp-hz = /bits/ 64 <1807000000>; 121 opp-microvolt = <1089000>; 122 }; 123 opp-2106000000 { 124 opp-hz = /bits/ 64 <2106000000>; 125 opp-microvolt = <1125000>; 126 }; 127 }; 128 129 cpus { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 cpu-map { 134 cluster0 { 135 core0 { 136 cpu = <&cpu0>; 137 }; 138 core1 { 139 cpu = <&cpu1>; 140 }; 141 }; 142 143 cluster1 { 144 core0 { 145 cpu = <&cpu2>; 146 }; 147 core1 { 148 cpu = <&cpu3>; 149 }; 150 }; 151 }; 152 153 cpu0: cpu@0 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a53"; 156 reg = <0x000>; 157 enable-method = "psci"; 158 cpu-idle-states = <&CPU_SLEEP_0>; 159 #cooling-cells = <2>; 160 clocks = <&infracfg CLK_INFRA_CA53SEL>, 161 <&apmixedsys CLK_APMIXED_MAINPLL>; 162 clock-names = "cpu", "intermediate"; 163 operating-points-v2 = <&cluster0_opp>; 164 }; 165 166 cpu1: cpu@1 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x001>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_SLEEP_0>; 172 #cooling-cells = <2>; 173 clocks = <&infracfg CLK_INFRA_CA53SEL>, 174 <&apmixedsys CLK_APMIXED_MAINPLL>; 175 clock-names = "cpu", "intermediate"; 176 operating-points-v2 = <&cluster0_opp>; 177 }; 178 179 cpu2: cpu@100 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a57"; 182 reg = <0x100>; 183 enable-method = "psci"; 184 cpu-idle-states = <&CPU_SLEEP_0>; 185 #cooling-cells = <2>; 186 clocks = <&infracfg CLK_INFRA_CA57SEL>, 187 <&apmixedsys CLK_APMIXED_MAINPLL>; 188 clock-names = "cpu", "intermediate"; 189 operating-points-v2 = <&cluster1_opp>; 190 }; 191 192 cpu3: cpu@101 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-a57"; 195 reg = <0x101>; 196 enable-method = "psci"; 197 cpu-idle-states = <&CPU_SLEEP_0>; 198 #cooling-cells = <2>; 199 clocks = <&infracfg CLK_INFRA_CA57SEL>, 200 <&apmixedsys CLK_APMIXED_MAINPLL>; 201 clock-names = "cpu", "intermediate"; 202 operating-points-v2 = <&cluster1_opp>; 203 }; 204 205 idle-states { 206 entry-method = "psci"; 207 208 CPU_SLEEP_0: cpu-sleep-0 { 209 compatible = "arm,idle-state"; 210 local-timer-stop; 211 entry-latency-us = <639>; 212 exit-latency-us = <680>; 213 min-residency-us = <1088>; 214 arm,psci-suspend-param = <0x0010000>; 215 }; 216 }; 217 }; 218 219 psci { 220 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 221 method = "smc"; 222 cpu_suspend = <0x84000001>; 223 cpu_off = <0x84000002>; 224 cpu_on = <0x84000003>; 225 }; 226 227 clk26m: oscillator@0 { 228 compatible = "fixed-clock"; 229 #clock-cells = <0>; 230 clock-frequency = <26000000>; 231 clock-output-names = "clk26m"; 232 }; 233 234 clk32k: oscillator@1 { 235 compatible = "fixed-clock"; 236 #clock-cells = <0>; 237 clock-frequency = <32000>; 238 clock-output-names = "clk32k"; 239 }; 240 241 cpum_ck: oscillator@2 { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <0>; 245 clock-output-names = "cpum_ck"; 246 }; 247 248 thermal-zones { 249 cpu_thermal: cpu_thermal { 250 polling-delay-passive = <1000>; /* milliseconds */ 251 polling-delay = <1000>; /* milliseconds */ 252 253 thermal-sensors = <&thermal>; 254 sustainable-power = <1500>; /* milliwatts */ 255 256 trips { 257 threshold: trip-point@0 { 258 temperature = <68000>; 259 hysteresis = <2000>; 260 type = "passive"; 261 }; 262 263 target: trip-point@1 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 cpu_crit: cpu_crit@0 { 270 temperature = <115000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map@0 { 278 trip = <&target>; 279 cooling-device = <&cpu0 0 0>; 280 contribution = <3072>; 281 }; 282 map@1 { 283 trip = <&target>; 284 cooling-device = <&cpu2 0 0>; 285 contribution = <1024>; 286 }; 287 }; 288 }; 289 }; 290 291 reserved-memory { 292 #address-cells = <2>; 293 #size-cells = <2>; 294 ranges; 295 vpu_dma_reserved: vpu_dma_mem_region { 296 compatible = "shared-dma-pool"; 297 reg = <0 0xb7000000 0 0x500000>; 298 alignment = <0x1000>; 299 no-map; 300 }; 301 }; 302 303 timer { 304 compatible = "arm,armv8-timer"; 305 interrupt-parent = <&gic>; 306 interrupts = <GIC_PPI 13 307 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 308 <GIC_PPI 14 309 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 310 <GIC_PPI 11 311 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 312 <GIC_PPI 10 313 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 314 }; 315 316 soc { 317 #address-cells = <2>; 318 #size-cells = <2>; 319 compatible = "simple-bus"; 320 ranges; 321 322 topckgen: clock-controller@10000000 { 323 compatible = "mediatek,mt8173-topckgen"; 324 reg = <0 0x10000000 0 0x1000>; 325 #clock-cells = <1>; 326 }; 327 328 infracfg: power-controller@10001000 { 329 compatible = "mediatek,mt8173-infracfg", "syscon"; 330 reg = <0 0x10001000 0 0x1000>; 331 #clock-cells = <1>; 332 #reset-cells = <1>; 333 }; 334 335 pericfg: power-controller@10003000 { 336 compatible = "mediatek,mt8173-pericfg", "syscon"; 337 reg = <0 0x10003000 0 0x1000>; 338 #clock-cells = <1>; 339 #reset-cells = <1>; 340 }; 341 342 syscfg_pctl_a: syscfg_pctl_a@10005000 { 343 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 344 reg = <0 0x10005000 0 0x1000>; 345 }; 346 347 pio: pinctrl@10005000 { 348 compatible = "mediatek,mt8173-pinctrl"; 349 reg = <0 0x1000b000 0 0x1000>; 350 mediatek,pctl-regmap = <&syscfg_pctl_a>; 351 pins-are-numbered; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 359 360 hdmi_pin: xxx { 361 362 /*hdmi htplg pin*/ 363 pins1 { 364 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 365 input-enable; 366 bias-pull-down; 367 }; 368 }; 369 370 i2c0_pins_a: i2c0 { 371 pins1 { 372 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 373 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 374 bias-disable; 375 }; 376 }; 377 378 i2c1_pins_a: i2c1 { 379 pins1 { 380 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 381 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 382 bias-disable; 383 }; 384 }; 385 386 i2c2_pins_a: i2c2 { 387 pins1 { 388 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 389 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 390 bias-disable; 391 }; 392 }; 393 394 i2c3_pins_a: i2c3 { 395 pins1 { 396 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 397 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 398 bias-disable; 399 }; 400 }; 401 402 i2c4_pins_a: i2c4 { 403 pins1 { 404 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 405 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 406 bias-disable; 407 }; 408 }; 409 410 i2c6_pins_a: i2c6 { 411 pins1 { 412 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 413 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 414 bias-disable; 415 }; 416 }; 417 }; 418 419 scpsys: scpsys@10006000 { 420 compatible = "mediatek,mt8173-scpsys"; 421 #power-domain-cells = <1>; 422 reg = <0 0x10006000 0 0x1000>; 423 clocks = <&clk26m>, 424 <&topckgen CLK_TOP_MM_SEL>, 425 <&topckgen CLK_TOP_VENC_SEL>, 426 <&topckgen CLK_TOP_VENC_LT_SEL>; 427 clock-names = "mfg", "mm", "venc", "venc_lt"; 428 infracfg = <&infracfg>; 429 }; 430 431 watchdog: watchdog@10007000 { 432 compatible = "mediatek,mt8173-wdt", 433 "mediatek,mt6589-wdt"; 434 reg = <0 0x10007000 0 0x100>; 435 }; 436 437 timer: timer@10008000 { 438 compatible = "mediatek,mt8173-timer", 439 "mediatek,mt6577-timer"; 440 reg = <0 0x10008000 0 0x1000>; 441 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 442 clocks = <&infracfg CLK_INFRA_CLK_13M>, 443 <&topckgen CLK_TOP_RTC_SEL>; 444 }; 445 446 pwrap: pwrap@1000d000 { 447 compatible = "mediatek,mt8173-pwrap"; 448 reg = <0 0x1000d000 0 0x1000>; 449 reg-names = "pwrap"; 450 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 451 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 452 reset-names = "pwrap"; 453 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 454 clock-names = "spi", "wrap"; 455 }; 456 457 cec: cec@10013000 { 458 compatible = "mediatek,mt8173-cec"; 459 reg = <0 0x10013000 0 0xbc>; 460 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 461 clocks = <&infracfg CLK_INFRA_CEC>; 462 status = "disabled"; 463 }; 464 465 vpu: vpu@10020000 { 466 compatible = "mediatek,mt8173-vpu"; 467 reg = <0 0x10020000 0 0x30000>, 468 <0 0x10050000 0 0x100>; 469 reg-names = "tcm", "cfg_reg"; 470 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&topckgen CLK_TOP_SCP_SEL>; 472 clock-names = "main"; 473 memory-region = <&vpu_dma_reserved>; 474 }; 475 476 sysirq: intpol-controller@10200620 { 477 compatible = "mediatek,mt8173-sysirq", 478 "mediatek,mt6577-sysirq"; 479 interrupt-controller; 480 #interrupt-cells = <3>; 481 interrupt-parent = <&gic>; 482 reg = <0 0x10200620 0 0x20>; 483 }; 484 485 iommu: iommu@10205000 { 486 compatible = "mediatek,mt8173-m4u"; 487 reg = <0 0x10205000 0 0x1000>; 488 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 489 clocks = <&infracfg CLK_INFRA_M4U>; 490 clock-names = "bclk"; 491 mediatek,larbs = <&larb0 &larb1 &larb2 492 &larb3 &larb4 &larb5>; 493 #iommu-cells = <1>; 494 }; 495 496 efuse: efuse@10206000 { 497 compatible = "mediatek,mt8173-efuse"; 498 reg = <0 0x10206000 0 0x1000>; 499 #address-cells = <1>; 500 #size-cells = <1>; 501 thermal_calibration: calib@528 { 502 reg = <0x528 0xc>; 503 }; 504 }; 505 506 apmixedsys: clock-controller@10209000 { 507 compatible = "mediatek,mt8173-apmixedsys"; 508 reg = <0 0x10209000 0 0x1000>; 509 #clock-cells = <1>; 510 }; 511 512 hdmi_phy: hdmi-phy@10209100 { 513 compatible = "mediatek,mt8173-hdmi-phy"; 514 reg = <0 0x10209100 0 0x24>; 515 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 516 clock-names = "pll_ref"; 517 clock-output-names = "hdmitx_dig_cts"; 518 mediatek,ibias = <0xa>; 519 mediatek,ibias_up = <0x1c>; 520 #clock-cells = <0>; 521 #phy-cells = <0>; 522 status = "disabled"; 523 }; 524 525 gce: mailbox@10212000 { 526 compatible = "mediatek,mt8173-gce"; 527 reg = <0 0x10212000 0 0x1000>; 528 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 529 clocks = <&infracfg CLK_INFRA_GCE>; 530 clock-names = "gce"; 531 #mbox-cells = <3>; 532 }; 533 534 mipi_tx0: mipi-dphy@10215000 { 535 compatible = "mediatek,mt8173-mipi-tx"; 536 reg = <0 0x10215000 0 0x1000>; 537 clocks = <&clk26m>; 538 clock-output-names = "mipi_tx0_pll"; 539 #clock-cells = <0>; 540 #phy-cells = <0>; 541 status = "disabled"; 542 }; 543 544 mipi_tx1: mipi-dphy@10216000 { 545 compatible = "mediatek,mt8173-mipi-tx"; 546 reg = <0 0x10216000 0 0x1000>; 547 clocks = <&clk26m>; 548 clock-output-names = "mipi_tx1_pll"; 549 #clock-cells = <0>; 550 #phy-cells = <0>; 551 status = "disabled"; 552 }; 553 554 gic: interrupt-controller@10220000 { 555 compatible = "arm,gic-400"; 556 #interrupt-cells = <3>; 557 interrupt-parent = <&gic>; 558 interrupt-controller; 559 reg = <0 0x10221000 0 0x1000>, 560 <0 0x10222000 0 0x2000>, 561 <0 0x10224000 0 0x2000>, 562 <0 0x10226000 0 0x2000>; 563 interrupts = <GIC_PPI 9 564 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 565 }; 566 567 auxadc: auxadc@11001000 { 568 compatible = "mediatek,mt8173-auxadc"; 569 reg = <0 0x11001000 0 0x1000>; 570 clocks = <&pericfg CLK_PERI_AUXADC>; 571 clock-names = "main"; 572 #io-channel-cells = <1>; 573 }; 574 575 uart0: serial@11002000 { 576 compatible = "mediatek,mt8173-uart", 577 "mediatek,mt6577-uart"; 578 reg = <0 0x11002000 0 0x400>; 579 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 580 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 581 clock-names = "baud", "bus"; 582 status = "disabled"; 583 }; 584 585 uart1: serial@11003000 { 586 compatible = "mediatek,mt8173-uart", 587 "mediatek,mt6577-uart"; 588 reg = <0 0x11003000 0 0x400>; 589 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 590 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 591 clock-names = "baud", "bus"; 592 status = "disabled"; 593 }; 594 595 uart2: serial@11004000 { 596 compatible = "mediatek,mt8173-uart", 597 "mediatek,mt6577-uart"; 598 reg = <0 0x11004000 0 0x400>; 599 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 600 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 601 clock-names = "baud", "bus"; 602 status = "disabled"; 603 }; 604 605 uart3: serial@11005000 { 606 compatible = "mediatek,mt8173-uart", 607 "mediatek,mt6577-uart"; 608 reg = <0 0x11005000 0 0x400>; 609 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 610 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 611 clock-names = "baud", "bus"; 612 status = "disabled"; 613 }; 614 615 i2c0: i2c@11007000 { 616 compatible = "mediatek,mt8173-i2c"; 617 reg = <0 0x11007000 0 0x70>, 618 <0 0x11000100 0 0x80>; 619 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 620 clock-div = <16>; 621 clocks = <&pericfg CLK_PERI_I2C0>, 622 <&pericfg CLK_PERI_AP_DMA>; 623 clock-names = "main", "dma"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&i2c0_pins_a>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c1: i2c@11008000 { 632 compatible = "mediatek,mt8173-i2c"; 633 reg = <0 0x11008000 0 0x70>, 634 <0 0x11000180 0 0x80>; 635 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 636 clock-div = <16>; 637 clocks = <&pericfg CLK_PERI_I2C1>, 638 <&pericfg CLK_PERI_AP_DMA>; 639 clock-names = "main", "dma"; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&i2c1_pins_a>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 status = "disabled"; 645 }; 646 647 i2c2: i2c@11009000 { 648 compatible = "mediatek,mt8173-i2c"; 649 reg = <0 0x11009000 0 0x70>, 650 <0 0x11000200 0 0x80>; 651 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 652 clock-div = <16>; 653 clocks = <&pericfg CLK_PERI_I2C2>, 654 <&pericfg CLK_PERI_AP_DMA>; 655 clock-names = "main", "dma"; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&i2c2_pins_a>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 663 spi: spi@1100a000 { 664 compatible = "mediatek,mt8173-spi"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 reg = <0 0x1100a000 0 0x1000>; 668 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 669 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 670 <&topckgen CLK_TOP_SPI_SEL>, 671 <&pericfg CLK_PERI_SPI0>; 672 clock-names = "parent-clk", "sel-clk", "spi-clk"; 673 status = "disabled"; 674 }; 675 676 thermal: thermal@1100b000 { 677 #thermal-sensor-cells = <0>; 678 compatible = "mediatek,mt8173-thermal"; 679 reg = <0 0x1100b000 0 0x1000>; 680 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 681 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 682 clock-names = "therm", "auxadc"; 683 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 684 mediatek,auxadc = <&auxadc>; 685 mediatek,apmixedsys = <&apmixedsys>; 686 nvmem-cells = <&thermal_calibration>; 687 nvmem-cell-names = "calibration-data"; 688 }; 689 690 nor_flash: spi@1100d000 { 691 compatible = "mediatek,mt8173-nor"; 692 reg = <0 0x1100d000 0 0xe0>; 693 clocks = <&pericfg CLK_PERI_SPI>, 694 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 695 clock-names = "spi", "sf"; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 i2c3: i2c@11010000 { 702 compatible = "mediatek,mt8173-i2c"; 703 reg = <0 0x11010000 0 0x70>, 704 <0 0x11000280 0 0x80>; 705 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 706 clock-div = <16>; 707 clocks = <&pericfg CLK_PERI_I2C3>, 708 <&pericfg CLK_PERI_AP_DMA>; 709 clock-names = "main", "dma"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&i2c3_pins_a>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 status = "disabled"; 715 }; 716 717 i2c4: i2c@11011000 { 718 compatible = "mediatek,mt8173-i2c"; 719 reg = <0 0x11011000 0 0x70>, 720 <0 0x11000300 0 0x80>; 721 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 722 clock-div = <16>; 723 clocks = <&pericfg CLK_PERI_I2C4>, 724 <&pericfg CLK_PERI_AP_DMA>; 725 clock-names = "main", "dma"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&i2c4_pins_a>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 status = "disabled"; 731 }; 732 733 hdmiddc0: i2c@11012000 { 734 compatible = "mediatek,mt8173-hdmi-ddc"; 735 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 736 reg = <0 0x11012000 0 0x1C>; 737 clocks = <&pericfg CLK_PERI_I2C5>; 738 clock-names = "ddc-i2c"; 739 }; 740 741 i2c6: i2c@11013000 { 742 compatible = "mediatek,mt8173-i2c"; 743 reg = <0 0x11013000 0 0x70>, 744 <0 0x11000080 0 0x80>; 745 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 746 clock-div = <16>; 747 clocks = <&pericfg CLK_PERI_I2C6>, 748 <&pericfg CLK_PERI_AP_DMA>; 749 clock-names = "main", "dma"; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&i2c6_pins_a>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 afe: audio-controller@11220000 { 758 compatible = "mediatek,mt8173-afe-pcm"; 759 reg = <0 0x11220000 0 0x1000>; 760 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 761 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 762 clocks = <&infracfg CLK_INFRA_AUDIO>, 763 <&topckgen CLK_TOP_AUDIO_SEL>, 764 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 765 <&topckgen CLK_TOP_APLL1_DIV0>, 766 <&topckgen CLK_TOP_APLL2_DIV0>, 767 <&topckgen CLK_TOP_I2S0_M_SEL>, 768 <&topckgen CLK_TOP_I2S1_M_SEL>, 769 <&topckgen CLK_TOP_I2S2_M_SEL>, 770 <&topckgen CLK_TOP_I2S3_M_SEL>, 771 <&topckgen CLK_TOP_I2S3_B_SEL>; 772 clock-names = "infra_sys_audio_clk", 773 "top_pdn_audio", 774 "top_pdn_aud_intbus", 775 "bck0", 776 "bck1", 777 "i2s0_m", 778 "i2s1_m", 779 "i2s2_m", 780 "i2s3_m", 781 "i2s3_b"; 782 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 783 <&topckgen CLK_TOP_AUD_2_SEL>; 784 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 785 <&topckgen CLK_TOP_APLL2>; 786 }; 787 788 mmc0: mmc@11230000 { 789 compatible = "mediatek,mt8173-mmc"; 790 reg = <0 0x11230000 0 0x1000>; 791 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 792 clocks = <&pericfg CLK_PERI_MSDC30_0>, 793 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 794 clock-names = "source", "hclk"; 795 status = "disabled"; 796 }; 797 798 mmc1: mmc@11240000 { 799 compatible = "mediatek,mt8173-mmc"; 800 reg = <0 0x11240000 0 0x1000>; 801 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 802 clocks = <&pericfg CLK_PERI_MSDC30_1>, 803 <&topckgen CLK_TOP_AXI_SEL>; 804 clock-names = "source", "hclk"; 805 status = "disabled"; 806 }; 807 808 mmc2: mmc@11250000 { 809 compatible = "mediatek,mt8173-mmc"; 810 reg = <0 0x11250000 0 0x1000>; 811 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 812 clocks = <&pericfg CLK_PERI_MSDC30_2>, 813 <&topckgen CLK_TOP_AXI_SEL>; 814 clock-names = "source", "hclk"; 815 status = "disabled"; 816 }; 817 818 mmc3: mmc@11260000 { 819 compatible = "mediatek,mt8173-mmc"; 820 reg = <0 0x11260000 0 0x1000>; 821 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 822 clocks = <&pericfg CLK_PERI_MSDC30_3>, 823 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 824 clock-names = "source", "hclk"; 825 status = "disabled"; 826 }; 827 828 ssusb: usb@11271000 { 829 compatible = "mediatek,mt8173-mtu3"; 830 reg = <0 0x11271000 0 0x3000>, 831 <0 0x11280700 0 0x0100>; 832 reg-names = "mac", "ippc"; 833 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 834 phys = <&u2port0 PHY_TYPE_USB2>, 835 <&u3port0 PHY_TYPE_USB3>, 836 <&u2port1 PHY_TYPE_USB2>; 837 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 838 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 839 clock-names = "sys_ck", "ref_ck"; 840 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 841 #address-cells = <2>; 842 #size-cells = <2>; 843 ranges; 844 status = "disabled"; 845 846 usb_host: xhci@11270000 { 847 compatible = "mediatek,mt8173-xhci"; 848 reg = <0 0x11270000 0 0x1000>; 849 reg-names = "mac"; 850 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 851 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 852 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 853 clock-names = "sys_ck", "ref_ck"; 854 status = "disabled"; 855 }; 856 }; 857 858 u3phy: usb-phy@11290000 { 859 compatible = "mediatek,mt8173-u3phy"; 860 reg = <0 0x11290000 0 0x800>; 861 #address-cells = <2>; 862 #size-cells = <2>; 863 ranges; 864 status = "okay"; 865 866 u2port0: usb-phy@11290800 { 867 reg = <0 0x11290800 0 0x100>; 868 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 869 clock-names = "ref"; 870 #phy-cells = <1>; 871 status = "okay"; 872 }; 873 874 u3port0: usb-phy@11290900 { 875 reg = <0 0x11290900 0 0x700>; 876 clocks = <&clk26m>; 877 clock-names = "ref"; 878 #phy-cells = <1>; 879 status = "okay"; 880 }; 881 882 u2port1: usb-phy@11291000 { 883 reg = <0 0x11291000 0 0x100>; 884 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 885 clock-names = "ref"; 886 #phy-cells = <1>; 887 status = "okay"; 888 }; 889 }; 890 891 mmsys: clock-controller@14000000 { 892 compatible = "mediatek,mt8173-mmsys", "syscon"; 893 reg = <0 0x14000000 0 0x1000>; 894 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 895 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 896 assigned-clock-rates = <400000000>; 897 #clock-cells = <1>; 898 }; 899 900 mdp_rdma0: rdma@14001000 { 901 compatible = "mediatek,mt8173-mdp-rdma", 902 "mediatek,mt8173-mdp"; 903 reg = <0 0x14001000 0 0x1000>; 904 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 905 <&mmsys CLK_MM_MUTEX_32K>; 906 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 907 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 908 mediatek,larb = <&larb0>; 909 mediatek,vpu = <&vpu>; 910 }; 911 912 mdp_rdma1: rdma@14002000 { 913 compatible = "mediatek,mt8173-mdp-rdma"; 914 reg = <0 0x14002000 0 0x1000>; 915 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 916 <&mmsys CLK_MM_MUTEX_32K>; 917 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 918 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 919 mediatek,larb = <&larb4>; 920 }; 921 922 mdp_rsz0: rsz@14003000 { 923 compatible = "mediatek,mt8173-mdp-rsz"; 924 reg = <0 0x14003000 0 0x1000>; 925 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 926 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927 }; 928 929 mdp_rsz1: rsz@14004000 { 930 compatible = "mediatek,mt8173-mdp-rsz"; 931 reg = <0 0x14004000 0 0x1000>; 932 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 933 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 934 }; 935 936 mdp_rsz2: rsz@14005000 { 937 compatible = "mediatek,mt8173-mdp-rsz"; 938 reg = <0 0x14005000 0 0x1000>; 939 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 940 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 941 }; 942 943 mdp_wdma0: wdma@14006000 { 944 compatible = "mediatek,mt8173-mdp-wdma"; 945 reg = <0 0x14006000 0 0x1000>; 946 clocks = <&mmsys CLK_MM_MDP_WDMA>; 947 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 948 iommus = <&iommu M4U_PORT_MDP_WDMA>; 949 mediatek,larb = <&larb0>; 950 }; 951 952 mdp_wrot0: wrot@14007000 { 953 compatible = "mediatek,mt8173-mdp-wrot"; 954 reg = <0 0x14007000 0 0x1000>; 955 clocks = <&mmsys CLK_MM_MDP_WROT0>; 956 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 957 iommus = <&iommu M4U_PORT_MDP_WROT0>; 958 mediatek,larb = <&larb0>; 959 }; 960 961 mdp_wrot1: wrot@14008000 { 962 compatible = "mediatek,mt8173-mdp-wrot"; 963 reg = <0 0x14008000 0 0x1000>; 964 clocks = <&mmsys CLK_MM_MDP_WROT1>; 965 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 966 iommus = <&iommu M4U_PORT_MDP_WROT1>; 967 mediatek,larb = <&larb4>; 968 }; 969 970 ovl0: ovl@1400c000 { 971 compatible = "mediatek,mt8173-disp-ovl"; 972 reg = <0 0x1400c000 0 0x1000>; 973 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 974 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 975 clocks = <&mmsys CLK_MM_DISP_OVL0>; 976 iommus = <&iommu M4U_PORT_DISP_OVL0>; 977 mediatek,larb = <&larb0>; 978 }; 979 980 ovl1: ovl@1400d000 { 981 compatible = "mediatek,mt8173-disp-ovl"; 982 reg = <0 0x1400d000 0 0x1000>; 983 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 984 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 985 clocks = <&mmsys CLK_MM_DISP_OVL1>; 986 iommus = <&iommu M4U_PORT_DISP_OVL1>; 987 mediatek,larb = <&larb4>; 988 }; 989 990 rdma0: rdma@1400e000 { 991 compatible = "mediatek,mt8173-disp-rdma"; 992 reg = <0 0x1400e000 0 0x1000>; 993 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 994 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 995 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 996 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 997 mediatek,larb = <&larb0>; 998 }; 999 1000 rdma1: rdma@1400f000 { 1001 compatible = "mediatek,mt8173-disp-rdma"; 1002 reg = <0 0x1400f000 0 0x1000>; 1003 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1004 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1005 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1006 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1007 mediatek,larb = <&larb4>; 1008 }; 1009 1010 rdma2: rdma@14010000 { 1011 compatible = "mediatek,mt8173-disp-rdma"; 1012 reg = <0 0x14010000 0 0x1000>; 1013 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1014 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1015 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1016 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1017 mediatek,larb = <&larb4>; 1018 }; 1019 1020 wdma0: wdma@14011000 { 1021 compatible = "mediatek,mt8173-disp-wdma"; 1022 reg = <0 0x14011000 0 0x1000>; 1023 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1024 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1025 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1026 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1027 mediatek,larb = <&larb0>; 1028 }; 1029 1030 wdma1: wdma@14012000 { 1031 compatible = "mediatek,mt8173-disp-wdma"; 1032 reg = <0 0x14012000 0 0x1000>; 1033 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1034 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1035 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1036 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1037 mediatek,larb = <&larb4>; 1038 }; 1039 1040 color0: color@14013000 { 1041 compatible = "mediatek,mt8173-disp-color"; 1042 reg = <0 0x14013000 0 0x1000>; 1043 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1044 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1045 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1046 }; 1047 1048 color1: color@14014000 { 1049 compatible = "mediatek,mt8173-disp-color"; 1050 reg = <0 0x14014000 0 0x1000>; 1051 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1052 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1053 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1054 }; 1055 1056 aal@14015000 { 1057 compatible = "mediatek,mt8173-disp-aal"; 1058 reg = <0 0x14015000 0 0x1000>; 1059 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1060 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1061 clocks = <&mmsys CLK_MM_DISP_AAL>; 1062 }; 1063 1064 gamma@14016000 { 1065 compatible = "mediatek,mt8173-disp-gamma"; 1066 reg = <0 0x14016000 0 0x1000>; 1067 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1068 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1069 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1070 }; 1071 1072 merge@14017000 { 1073 compatible = "mediatek,mt8173-disp-merge"; 1074 reg = <0 0x14017000 0 0x1000>; 1075 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1076 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1077 }; 1078 1079 split0: split@14018000 { 1080 compatible = "mediatek,mt8173-disp-split"; 1081 reg = <0 0x14018000 0 0x1000>; 1082 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1083 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1084 }; 1085 1086 split1: split@14019000 { 1087 compatible = "mediatek,mt8173-disp-split"; 1088 reg = <0 0x14019000 0 0x1000>; 1089 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1090 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1091 }; 1092 1093 ufoe@1401a000 { 1094 compatible = "mediatek,mt8173-disp-ufoe"; 1095 reg = <0 0x1401a000 0 0x1000>; 1096 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1097 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1098 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1099 }; 1100 1101 dsi0: dsi@1401b000 { 1102 compatible = "mediatek,mt8173-dsi"; 1103 reg = <0 0x1401b000 0 0x1000>; 1104 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1105 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1106 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1107 <&mmsys CLK_MM_DSI0_DIGITAL>, 1108 <&mipi_tx0>; 1109 clock-names = "engine", "digital", "hs"; 1110 phys = <&mipi_tx0>; 1111 phy-names = "dphy"; 1112 status = "disabled"; 1113 }; 1114 1115 dsi1: dsi@1401c000 { 1116 compatible = "mediatek,mt8173-dsi"; 1117 reg = <0 0x1401c000 0 0x1000>; 1118 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1119 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1120 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1121 <&mmsys CLK_MM_DSI1_DIGITAL>, 1122 <&mipi_tx1>; 1123 clock-names = "engine", "digital", "hs"; 1124 phy = <&mipi_tx1>; 1125 phy-names = "dphy"; 1126 status = "disabled"; 1127 }; 1128 1129 dpi0: dpi@1401d000 { 1130 compatible = "mediatek,mt8173-dpi"; 1131 reg = <0 0x1401d000 0 0x1000>; 1132 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1133 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1134 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1135 <&mmsys CLK_MM_DPI_ENGINE>, 1136 <&apmixedsys CLK_APMIXED_TVDPLL>; 1137 clock-names = "pixel", "engine", "pll"; 1138 status = "disabled"; 1139 1140 port { 1141 dpi0_out: endpoint { 1142 remote-endpoint = <&hdmi0_in>; 1143 }; 1144 }; 1145 }; 1146 1147 pwm0: pwm@1401e000 { 1148 compatible = "mediatek,mt8173-disp-pwm", 1149 "mediatek,mt6595-disp-pwm"; 1150 reg = <0 0x1401e000 0 0x1000>; 1151 #pwm-cells = <2>; 1152 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1153 <&mmsys CLK_MM_DISP_PWM0MM>; 1154 clock-names = "main", "mm"; 1155 status = "disabled"; 1156 }; 1157 1158 pwm1: pwm@1401f000 { 1159 compatible = "mediatek,mt8173-disp-pwm", 1160 "mediatek,mt6595-disp-pwm"; 1161 reg = <0 0x1401f000 0 0x1000>; 1162 #pwm-cells = <2>; 1163 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1164 <&mmsys CLK_MM_DISP_PWM1MM>; 1165 clock-names = "main", "mm"; 1166 status = "disabled"; 1167 }; 1168 1169 mutex: mutex@14020000 { 1170 compatible = "mediatek,mt8173-disp-mutex"; 1171 reg = <0 0x14020000 0 0x1000>; 1172 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1173 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1174 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1175 }; 1176 1177 larb0: larb@14021000 { 1178 compatible = "mediatek,mt8173-smi-larb"; 1179 reg = <0 0x14021000 0 0x1000>; 1180 mediatek,smi = <&smi_common>; 1181 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1182 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1183 <&mmsys CLK_MM_SMI_LARB0>; 1184 clock-names = "apb", "smi"; 1185 }; 1186 1187 smi_common: smi@14022000 { 1188 compatible = "mediatek,mt8173-smi-common"; 1189 reg = <0 0x14022000 0 0x1000>; 1190 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1191 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1192 <&mmsys CLK_MM_SMI_COMMON>; 1193 clock-names = "apb", "smi"; 1194 }; 1195 1196 od@14023000 { 1197 compatible = "mediatek,mt8173-disp-od"; 1198 reg = <0 0x14023000 0 0x1000>; 1199 clocks = <&mmsys CLK_MM_DISP_OD>; 1200 }; 1201 1202 hdmi0: hdmi@14025000 { 1203 compatible = "mediatek,mt8173-hdmi"; 1204 reg = <0 0x14025000 0 0x400>; 1205 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1206 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1207 <&mmsys CLK_MM_HDMI_PLLCK>, 1208 <&mmsys CLK_MM_HDMI_AUDIO>, 1209 <&mmsys CLK_MM_HDMI_SPDIF>; 1210 clock-names = "pixel", "pll", "bclk", "spdif"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&hdmi_pin>; 1213 phys = <&hdmi_phy>; 1214 phy-names = "hdmi"; 1215 mediatek,syscon-hdmi = <&mmsys 0x900>; 1216 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1217 assigned-clock-parents = <&hdmi_phy>; 1218 status = "disabled"; 1219 1220 ports { 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 1224 port@0 { 1225 reg = <0>; 1226 1227 hdmi0_in: endpoint { 1228 remote-endpoint = <&dpi0_out>; 1229 }; 1230 }; 1231 }; 1232 }; 1233 1234 larb4: larb@14027000 { 1235 compatible = "mediatek,mt8173-smi-larb"; 1236 reg = <0 0x14027000 0 0x1000>; 1237 mediatek,smi = <&smi_common>; 1238 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1239 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1240 <&mmsys CLK_MM_SMI_LARB4>; 1241 clock-names = "apb", "smi"; 1242 }; 1243 1244 imgsys: clock-controller@15000000 { 1245 compatible = "mediatek,mt8173-imgsys", "syscon"; 1246 reg = <0 0x15000000 0 0x1000>; 1247 #clock-cells = <1>; 1248 }; 1249 1250 larb2: larb@15001000 { 1251 compatible = "mediatek,mt8173-smi-larb"; 1252 reg = <0 0x15001000 0 0x1000>; 1253 mediatek,smi = <&smi_common>; 1254 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1255 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1256 <&imgsys CLK_IMG_LARB2_SMI>; 1257 clock-names = "apb", "smi"; 1258 }; 1259 1260 vdecsys: clock-controller@16000000 { 1261 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1262 reg = <0 0x16000000 0 0x1000>; 1263 #clock-cells = <1>; 1264 }; 1265 1266 vcodec_dec: vcodec@16000000 { 1267 compatible = "mediatek,mt8173-vcodec-dec"; 1268 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1269 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1270 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1271 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1272 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1273 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1274 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1275 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1276 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1277 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1278 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1279 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1280 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1281 mediatek,larb = <&larb1>; 1282 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1283 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1284 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1285 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1286 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1287 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1288 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1289 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1290 mediatek,vpu = <&vpu>; 1291 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1292 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1293 <&topckgen CLK_TOP_UNIVPLL_D2>, 1294 <&topckgen CLK_TOP_CCI400_SEL>, 1295 <&topckgen CLK_TOP_VDEC_SEL>, 1296 <&topckgen CLK_TOP_VCODECPLL>, 1297 <&apmixedsys CLK_APMIXED_VENCPLL>, 1298 <&topckgen CLK_TOP_VENC_LT_SEL>, 1299 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1300 clock-names = "vcodecpll", 1301 "univpll_d2", 1302 "clk_cci400_sel", 1303 "vdec_sel", 1304 "vdecpll", 1305 "vencpll", 1306 "venc_lt_sel", 1307 "vdec_bus_clk_src"; 1308 }; 1309 1310 larb1: larb@16010000 { 1311 compatible = "mediatek,mt8173-smi-larb"; 1312 reg = <0 0x16010000 0 0x1000>; 1313 mediatek,smi = <&smi_common>; 1314 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1315 clocks = <&vdecsys CLK_VDEC_CKEN>, 1316 <&vdecsys CLK_VDEC_LARB_CKEN>; 1317 clock-names = "apb", "smi"; 1318 }; 1319 1320 vencsys: clock-controller@18000000 { 1321 compatible = "mediatek,mt8173-vencsys", "syscon"; 1322 reg = <0 0x18000000 0 0x1000>; 1323 #clock-cells = <1>; 1324 }; 1325 1326 larb3: larb@18001000 { 1327 compatible = "mediatek,mt8173-smi-larb"; 1328 reg = <0 0x18001000 0 0x1000>; 1329 mediatek,smi = <&smi_common>; 1330 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1331 clocks = <&vencsys CLK_VENC_CKE1>, 1332 <&vencsys CLK_VENC_CKE0>; 1333 clock-names = "apb", "smi"; 1334 }; 1335 1336 vcodec_enc: vcodec@18002000 { 1337 compatible = "mediatek,mt8173-vcodec-enc"; 1338 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1339 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1340 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1341 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1342 mediatek,larb = <&larb3>, 1343 <&larb5>; 1344 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1345 <&iommu M4U_PORT_VENC_REC>, 1346 <&iommu M4U_PORT_VENC_BSDMA>, 1347 <&iommu M4U_PORT_VENC_SV_COMV>, 1348 <&iommu M4U_PORT_VENC_RD_COMV>, 1349 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1350 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1351 <&iommu M4U_PORT_VENC_REF_LUMA>, 1352 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1353 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1354 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1355 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1356 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1357 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1358 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1359 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1360 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1361 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1362 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1363 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1364 mediatek,vpu = <&vpu>; 1365 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1366 <&topckgen CLK_TOP_VENC_SEL>, 1367 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1368 <&topckgen CLK_TOP_VENC_LT_SEL>; 1369 clock-names = "venc_sel_src", 1370 "venc_sel", 1371 "venc_lt_sel_src", 1372 "venc_lt_sel"; 1373 }; 1374 1375 vencltsys: clock-controller@19000000 { 1376 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1377 reg = <0 0x19000000 0 0x1000>; 1378 #clock-cells = <1>; 1379 }; 1380 1381 larb5: larb@19001000 { 1382 compatible = "mediatek,mt8173-smi-larb"; 1383 reg = <0 0x19001000 0 0x1000>; 1384 mediatek,smi = <&smi_common>; 1385 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1386 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1387 <&vencltsys CLK_VENCLT_CKE0>; 1388 clock-names = "apb", "smi"; 1389 }; 1390 }; 1391}; 1392 1393