1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/reset-controller/mt8173-resets.h> 18#include "mt8173-pinfunc.h" 19 20/ { 21 compatible = "mediatek,mt8173"; 22 interrupt-parent = <&sysirq>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu-map { 31 cluster0 { 32 core0 { 33 cpu = <&cpu0>; 34 }; 35 core1 { 36 cpu = <&cpu1>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu2>; 43 }; 44 core1 { 45 cpu = <&cpu3>; 46 }; 47 }; 48 }; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x000>; 54 }; 55 56 cpu1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x001>; 60 enable-method = "psci"; 61 }; 62 63 cpu2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a57"; 66 reg = <0x100>; 67 enable-method = "psci"; 68 }; 69 70 cpu3: cpu@101 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a57"; 73 reg = <0x101>; 74 enable-method = "psci"; 75 }; 76 }; 77 78 psci { 79 compatible = "arm,psci"; 80 method = "smc"; 81 cpu_suspend = <0x84000001>; 82 cpu_off = <0x84000002>; 83 cpu_on = <0x84000003>; 84 }; 85 86 clk26m: oscillator@0 { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <26000000>; 90 clock-output-names = "clk26m"; 91 }; 92 93 clk32k: oscillator@1 { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <32000>; 97 clock-output-names = "clk32k"; 98 }; 99 100 timer { 101 compatible = "arm,armv8-timer"; 102 interrupt-parent = <&gic>; 103 interrupts = <GIC_PPI 13 104 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 105 <GIC_PPI 14 106 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 107 <GIC_PPI 11 108 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 10 110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 111 }; 112 113 soc { 114 #address-cells = <2>; 115 #size-cells = <2>; 116 compatible = "simple-bus"; 117 ranges; 118 119 topckgen: clock-controller@10000000 { 120 compatible = "mediatek,mt8173-topckgen"; 121 reg = <0 0x10000000 0 0x1000>; 122 #clock-cells = <1>; 123 }; 124 125 infracfg: power-controller@10001000 { 126 compatible = "mediatek,mt8173-infracfg", "syscon"; 127 reg = <0 0x10001000 0 0x1000>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 pericfg: power-controller@10003000 { 133 compatible = "mediatek,mt8173-pericfg", "syscon"; 134 reg = <0 0x10003000 0 0x1000>; 135 #clock-cells = <1>; 136 #reset-cells = <1>; 137 }; 138 139 syscfg_pctl_a: syscfg_pctl_a@10005000 { 140 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 141 reg = <0 0x10005000 0 0x1000>; 142 }; 143 144 pio: pinctrl@0x10005000 { 145 compatible = "mediatek,mt8173-pinctrl"; 146 reg = <0 0x1000b000 0 0x1000>; 147 mediatek,pctl-regmap = <&syscfg_pctl_a>; 148 pins-are-numbered; 149 gpio-controller; 150 #gpio-cells = <2>; 151 interrupt-controller; 152 #interrupt-cells = <2>; 153 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 156 157 i2c0_pins_a: i2c0 { 158 pins1 { 159 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 160 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 161 bias-disable; 162 }; 163 }; 164 165 i2c1_pins_a: i2c1 { 166 pins1 { 167 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 168 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 169 bias-disable; 170 }; 171 }; 172 173 i2c2_pins_a: i2c2 { 174 pins1 { 175 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 176 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 177 bias-disable; 178 }; 179 }; 180 181 i2c3_pins_a: i2c3 { 182 pins1 { 183 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 184 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 185 bias-disable; 186 }; 187 }; 188 189 i2c4_pins_a: i2c4 { 190 pins1 { 191 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 192 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 193 bias-disable; 194 }; 195 }; 196 197 i2c6_pins_a: i2c6 { 198 pins1 { 199 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 200 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 201 bias-disable; 202 }; 203 }; 204 }; 205 206 scpsys: scpsys@10006000 { 207 compatible = "mediatek,mt8173-scpsys"; 208 #power-domain-cells = <1>; 209 reg = <0 0x10006000 0 0x1000>; 210 clocks = <&clk26m>, 211 <&topckgen CLK_TOP_MM_SEL>; 212 clock-names = "mfg", "mm"; 213 infracfg = <&infracfg>; 214 }; 215 216 watchdog: watchdog@10007000 { 217 compatible = "mediatek,mt8173-wdt", 218 "mediatek,mt6589-wdt"; 219 reg = <0 0x10007000 0 0x100>; 220 }; 221 222 pwrap: pwrap@1000d000 { 223 compatible = "mediatek,mt8173-pwrap"; 224 reg = <0 0x1000d000 0 0x1000>; 225 reg-names = "pwrap"; 226 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 227 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 228 reset-names = "pwrap"; 229 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 230 clock-names = "spi", "wrap"; 231 }; 232 233 sysirq: intpol-controller@10200620 { 234 compatible = "mediatek,mt8173-sysirq", 235 "mediatek,mt6577-sysirq"; 236 interrupt-controller; 237 #interrupt-cells = <3>; 238 interrupt-parent = <&gic>; 239 reg = <0 0x10200620 0 0x20>; 240 }; 241 242 apmixedsys: clock-controller@10209000 { 243 compatible = "mediatek,mt8173-apmixedsys"; 244 reg = <0 0x10209000 0 0x1000>; 245 #clock-cells = <1>; 246 }; 247 248 gic: interrupt-controller@10220000 { 249 compatible = "arm,gic-400"; 250 #interrupt-cells = <3>; 251 interrupt-parent = <&gic>; 252 interrupt-controller; 253 reg = <0 0x10221000 0 0x1000>, 254 <0 0x10222000 0 0x2000>, 255 <0 0x10224000 0 0x2000>, 256 <0 0x10226000 0 0x2000>; 257 interrupts = <GIC_PPI 9 258 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 259 }; 260 261 uart0: serial@11002000 { 262 compatible = "mediatek,mt8173-uart", 263 "mediatek,mt6577-uart"; 264 reg = <0 0x11002000 0 0x400>; 265 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 266 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 267 clock-names = "baud", "bus"; 268 status = "disabled"; 269 }; 270 271 uart1: serial@11003000 { 272 compatible = "mediatek,mt8173-uart", 273 "mediatek,mt6577-uart"; 274 reg = <0 0x11003000 0 0x400>; 275 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 276 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 277 clock-names = "baud", "bus"; 278 status = "disabled"; 279 }; 280 281 uart2: serial@11004000 { 282 compatible = "mediatek,mt8173-uart", 283 "mediatek,mt6577-uart"; 284 reg = <0 0x11004000 0 0x400>; 285 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 286 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 287 clock-names = "baud", "bus"; 288 status = "disabled"; 289 }; 290 291 uart3: serial@11005000 { 292 compatible = "mediatek,mt8173-uart", 293 "mediatek,mt6577-uart"; 294 reg = <0 0x11005000 0 0x400>; 295 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 296 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 297 clock-names = "baud", "bus"; 298 status = "disabled"; 299 }; 300 301 i2c0: i2c@11007000 { 302 compatible = "mediatek,mt8173-i2c"; 303 reg = <0 0x11007000 0 0x70>, 304 <0 0x11000100 0 0x80>; 305 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 306 clock-div = <16>; 307 clocks = <&pericfg CLK_PERI_I2C0>, 308 <&pericfg CLK_PERI_AP_DMA>; 309 clock-names = "main", "dma"; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2c0_pins_a>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 status = "disabled"; 315 }; 316 317 i2c1: i2c@11008000 { 318 compatible = "mediatek,mt8173-i2c"; 319 reg = <0 0x11008000 0 0x70>, 320 <0 0x11000180 0 0x80>; 321 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 322 clock-div = <16>; 323 clocks = <&pericfg CLK_PERI_I2C1>, 324 <&pericfg CLK_PERI_AP_DMA>; 325 clock-names = "main", "dma"; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&i2c1_pins_a>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 status = "disabled"; 331 }; 332 333 i2c2: i2c@11009000 { 334 compatible = "mediatek,mt8173-i2c"; 335 reg = <0 0x11009000 0 0x70>, 336 <0 0x11000200 0 0x80>; 337 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 338 clock-div = <16>; 339 clocks = <&pericfg CLK_PERI_I2C2>, 340 <&pericfg CLK_PERI_AP_DMA>; 341 clock-names = "main", "dma"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&i2c2_pins_a>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 status = "disabled"; 347 }; 348 349 i2c3: i2c3@11010000 { 350 compatible = "mediatek,mt8173-i2c"; 351 reg = <0 0x11010000 0 0x70>, 352 <0 0x11000280 0 0x80>; 353 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 354 clock-div = <16>; 355 clocks = <&pericfg CLK_PERI_I2C3>, 356 <&pericfg CLK_PERI_AP_DMA>; 357 clock-names = "main", "dma"; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&i2c3_pins_a>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 i2c4: i2c4@11011000 { 366 compatible = "mediatek,mt8173-i2c"; 367 reg = <0 0x11011000 0 0x70>, 368 <0 0x11000300 0 0x80>; 369 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 370 clock-div = <16>; 371 clocks = <&pericfg CLK_PERI_I2C4>, 372 <&pericfg CLK_PERI_AP_DMA>; 373 clock-names = "main", "dma"; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&i2c4_pins_a>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 status = "disabled"; 379 }; 380 381 i2c6: i2c6@11013000 { 382 compatible = "mediatek,mt8173-i2c"; 383 reg = <0 0x11013000 0 0x70>, 384 <0 0x11000080 0 0x80>; 385 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 386 clock-div = <16>; 387 clocks = <&pericfg CLK_PERI_I2C6>, 388 <&pericfg CLK_PERI_AP_DMA>; 389 clock-names = "main", "dma"; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&i2c6_pins_a>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 }; 397}; 398 399