1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include "mt8173-pinfunc.h" 23 24/ { 25 compatible = "mediatek,mt8173"; 26 interrupt-parent = <&sysirq>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 ovl0 = &ovl0; 32 ovl1 = &ovl1; 33 rdma0 = &rdma0; 34 rdma1 = &rdma1; 35 rdma2 = &rdma2; 36 wdma0 = &wdma0; 37 wdma1 = &wdma1; 38 color0 = &color0; 39 color1 = &color1; 40 split0 = &split0; 41 split1 = &split1; 42 dpi0 = &dpi0; 43 dsi0 = &dsi0; 44 dsi1 = &dsi1; 45 mdp_rdma0 = &mdp_rdma0; 46 mdp_rdma1 = &mdp_rdma1; 47 mdp_rsz0 = &mdp_rsz0; 48 mdp_rsz1 = &mdp_rsz1; 49 mdp_rsz2 = &mdp_rsz2; 50 mdp_wdma0 = &mdp_wdma0; 51 mdp_wrot0 = &mdp_wrot0; 52 mdp_wrot1 = &mdp_wrot1; 53 }; 54 55 cluster0_opp: opp_table0 { 56 compatible = "operating-points-v2"; 57 opp-shared; 58 opp-507000000 { 59 opp-hz = /bits/ 64 <507000000>; 60 opp-microvolt = <859000>; 61 }; 62 opp-702000000 { 63 opp-hz = /bits/ 64 <702000000>; 64 opp-microvolt = <908000>; 65 }; 66 opp-1001000000 { 67 opp-hz = /bits/ 64 <1001000000>; 68 opp-microvolt = <983000>; 69 }; 70 opp-1105000000 { 71 opp-hz = /bits/ 64 <1105000000>; 72 opp-microvolt = <1009000>; 73 }; 74 opp-1209000000 { 75 opp-hz = /bits/ 64 <1209000000>; 76 opp-microvolt = <1034000>; 77 }; 78 opp-1300000000 { 79 opp-hz = /bits/ 64 <1300000000>; 80 opp-microvolt = <1057000>; 81 }; 82 opp-1508000000 { 83 opp-hz = /bits/ 64 <1508000000>; 84 opp-microvolt = <1109000>; 85 }; 86 opp-1703000000 { 87 opp-hz = /bits/ 64 <1703000000>; 88 opp-microvolt = <1125000>; 89 }; 90 }; 91 92 cluster1_opp: opp_table1 { 93 compatible = "operating-points-v2"; 94 opp-shared; 95 opp-507000000 { 96 opp-hz = /bits/ 64 <507000000>; 97 opp-microvolt = <828000>; 98 }; 99 opp-702000000 { 100 opp-hz = /bits/ 64 <702000000>; 101 opp-microvolt = <867000>; 102 }; 103 opp-1001000000 { 104 opp-hz = /bits/ 64 <1001000000>; 105 opp-microvolt = <927000>; 106 }; 107 opp-1209000000 { 108 opp-hz = /bits/ 64 <1209000000>; 109 opp-microvolt = <968000>; 110 }; 111 opp-1404000000 { 112 opp-hz = /bits/ 64 <1404000000>; 113 opp-microvolt = <1007000>; 114 }; 115 opp-1612000000 { 116 opp-hz = /bits/ 64 <1612000000>; 117 opp-microvolt = <1049000>; 118 }; 119 opp-1807000000 { 120 opp-hz = /bits/ 64 <1807000000>; 121 opp-microvolt = <1089000>; 122 }; 123 opp-2106000000 { 124 opp-hz = /bits/ 64 <2106000000>; 125 opp-microvolt = <1125000>; 126 }; 127 }; 128 129 cpus { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 cpu-map { 134 cluster0 { 135 core0 { 136 cpu = <&cpu0>; 137 }; 138 core1 { 139 cpu = <&cpu1>; 140 }; 141 }; 142 143 cluster1 { 144 core0 { 145 cpu = <&cpu2>; 146 }; 147 core1 { 148 cpu = <&cpu3>; 149 }; 150 }; 151 }; 152 153 cpu0: cpu@0 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a53"; 156 reg = <0x000>; 157 enable-method = "psci"; 158 cpu-idle-states = <&CPU_SLEEP_0>; 159 #cooling-cells = <2>; 160 dynamic-power-coefficient = <263>; 161 clocks = <&infracfg CLK_INFRA_CA53SEL>, 162 <&apmixedsys CLK_APMIXED_MAINPLL>; 163 clock-names = "cpu", "intermediate"; 164 operating-points-v2 = <&cluster0_opp>; 165 }; 166 167 cpu1: cpu@1 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53"; 170 reg = <0x001>; 171 enable-method = "psci"; 172 cpu-idle-states = <&CPU_SLEEP_0>; 173 #cooling-cells = <2>; 174 dynamic-power-coefficient = <263>; 175 clocks = <&infracfg CLK_INFRA_CA53SEL>, 176 <&apmixedsys CLK_APMIXED_MAINPLL>; 177 clock-names = "cpu", "intermediate"; 178 operating-points-v2 = <&cluster0_opp>; 179 }; 180 181 cpu2: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a72"; 184 reg = <0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <530>; 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cluster1_opp>; 193 }; 194 195 cpu3: cpu@101 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a72"; 198 reg = <0x101>; 199 enable-method = "psci"; 200 cpu-idle-states = <&CPU_SLEEP_0>; 201 #cooling-cells = <2>; 202 dynamic-power-coefficient = <530>; 203 clocks = <&infracfg CLK_INFRA_CA72SEL>, 204 <&apmixedsys CLK_APMIXED_MAINPLL>; 205 clock-names = "cpu", "intermediate"; 206 operating-points-v2 = <&cluster1_opp>; 207 }; 208 209 idle-states { 210 entry-method = "psci"; 211 212 CPU_SLEEP_0: cpu-sleep-0 { 213 compatible = "arm,idle-state"; 214 local-timer-stop; 215 entry-latency-us = <639>; 216 exit-latency-us = <680>; 217 min-residency-us = <1088>; 218 arm,psci-suspend-param = <0x0010000>; 219 }; 220 }; 221 }; 222 223 pmu_a53 { 224 compatible = "arm,cortex-a53-pmu"; 225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 226 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 227 interrupt-affinity = <&cpu0>, <&cpu1>; 228 }; 229 230 pmu_a72 { 231 compatible = "arm,cortex-a72-pmu"; 232 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 233 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 234 interrupt-affinity = <&cpu2>, <&cpu3>; 235 }; 236 237 psci { 238 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 239 method = "smc"; 240 cpu_suspend = <0x84000001>; 241 cpu_off = <0x84000002>; 242 cpu_on = <0x84000003>; 243 }; 244 245 clk26m: oscillator@0 { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <26000000>; 249 clock-output-names = "clk26m"; 250 }; 251 252 clk32k: oscillator@1 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency = <32000>; 256 clock-output-names = "clk32k"; 257 }; 258 259 cpum_ck: oscillator@2 { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 clock-frequency = <0>; 263 clock-output-names = "cpum_ck"; 264 }; 265 266 thermal-zones { 267 cpu_thermal: cpu_thermal { 268 polling-delay-passive = <1000>; /* milliseconds */ 269 polling-delay = <1000>; /* milliseconds */ 270 271 thermal-sensors = <&thermal>; 272 sustainable-power = <1500>; /* milliwatts */ 273 274 trips { 275 threshold: trip-point@0 { 276 temperature = <68000>; 277 hysteresis = <2000>; 278 type = "passive"; 279 }; 280 281 target: trip-point@1 { 282 temperature = <85000>; 283 hysteresis = <2000>; 284 type = "passive"; 285 }; 286 287 cpu_crit: cpu_crit@0 { 288 temperature = <115000>; 289 hysteresis = <2000>; 290 type = "critical"; 291 }; 292 }; 293 294 cooling-maps { 295 map@0 { 296 trip = <&target>; 297 cooling-device = <&cpu0 0 0>, 298 <&cpu1 0 0>; 299 contribution = <3072>; 300 }; 301 map@1 { 302 trip = <&target>; 303 cooling-device = <&cpu2 0 0>, 304 <&cpu3 0 0>; 305 contribution = <1024>; 306 }; 307 }; 308 }; 309 }; 310 311 reserved-memory { 312 #address-cells = <2>; 313 #size-cells = <2>; 314 ranges; 315 vpu_dma_reserved: vpu_dma_mem_region { 316 compatible = "shared-dma-pool"; 317 reg = <0 0xb7000000 0 0x500000>; 318 alignment = <0x1000>; 319 no-map; 320 }; 321 }; 322 323 timer { 324 compatible = "arm,armv8-timer"; 325 interrupt-parent = <&gic>; 326 interrupts = <GIC_PPI 13 327 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 328 <GIC_PPI 14 329 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 330 <GIC_PPI 11 331 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 332 <GIC_PPI 10 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 334 arm,no-tick-in-suspend; 335 }; 336 337 soc { 338 #address-cells = <2>; 339 #size-cells = <2>; 340 compatible = "simple-bus"; 341 ranges; 342 343 topckgen: clock-controller@10000000 { 344 compatible = "mediatek,mt8173-topckgen"; 345 reg = <0 0x10000000 0 0x1000>; 346 #clock-cells = <1>; 347 }; 348 349 infracfg: power-controller@10001000 { 350 compatible = "mediatek,mt8173-infracfg", "syscon"; 351 reg = <0 0x10001000 0 0x1000>; 352 #clock-cells = <1>; 353 #reset-cells = <1>; 354 }; 355 356 pericfg: power-controller@10003000 { 357 compatible = "mediatek,mt8173-pericfg", "syscon"; 358 reg = <0 0x10003000 0 0x1000>; 359 #clock-cells = <1>; 360 #reset-cells = <1>; 361 }; 362 363 syscfg_pctl_a: syscfg_pctl_a@10005000 { 364 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 365 reg = <0 0x10005000 0 0x1000>; 366 }; 367 368 pio: pinctrl@10005000 { 369 compatible = "mediatek,mt8173-pinctrl"; 370 reg = <0 0x1000b000 0 0x1000>; 371 mediatek,pctl-regmap = <&syscfg_pctl_a>; 372 pins-are-numbered; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 380 381 hdmi_pin: xxx { 382 383 /*hdmi htplg pin*/ 384 pins1 { 385 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 386 input-enable; 387 bias-pull-down; 388 }; 389 }; 390 391 i2c0_pins_a: i2c0 { 392 pins1 { 393 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 394 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 395 bias-disable; 396 }; 397 }; 398 399 i2c1_pins_a: i2c1 { 400 pins1 { 401 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 402 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 403 bias-disable; 404 }; 405 }; 406 407 i2c2_pins_a: i2c2 { 408 pins1 { 409 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 410 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 411 bias-disable; 412 }; 413 }; 414 415 i2c3_pins_a: i2c3 { 416 pins1 { 417 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 418 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 419 bias-disable; 420 }; 421 }; 422 423 i2c4_pins_a: i2c4 { 424 pins1 { 425 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 426 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 427 bias-disable; 428 }; 429 }; 430 431 i2c6_pins_a: i2c6 { 432 pins1 { 433 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 434 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 435 bias-disable; 436 }; 437 }; 438 }; 439 440 scpsys: scpsys@10006000 { 441 compatible = "mediatek,mt8173-scpsys"; 442 #power-domain-cells = <1>; 443 reg = <0 0x10006000 0 0x1000>; 444 clocks = <&clk26m>, 445 <&topckgen CLK_TOP_MM_SEL>, 446 <&topckgen CLK_TOP_VENC_SEL>, 447 <&topckgen CLK_TOP_VENC_LT_SEL>; 448 clock-names = "mfg", "mm", "venc", "venc_lt"; 449 infracfg = <&infracfg>; 450 }; 451 452 watchdog: watchdog@10007000 { 453 compatible = "mediatek,mt8173-wdt", 454 "mediatek,mt6589-wdt"; 455 reg = <0 0x10007000 0 0x100>; 456 }; 457 458 timer: timer@10008000 { 459 compatible = "mediatek,mt8173-timer", 460 "mediatek,mt6577-timer"; 461 reg = <0 0x10008000 0 0x1000>; 462 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 463 clocks = <&infracfg CLK_INFRA_CLK_13M>, 464 <&topckgen CLK_TOP_RTC_SEL>; 465 }; 466 467 pwrap: pwrap@1000d000 { 468 compatible = "mediatek,mt8173-pwrap"; 469 reg = <0 0x1000d000 0 0x1000>; 470 reg-names = "pwrap"; 471 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 472 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 473 reset-names = "pwrap"; 474 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 475 clock-names = "spi", "wrap"; 476 }; 477 478 cec: cec@10013000 { 479 compatible = "mediatek,mt8173-cec"; 480 reg = <0 0x10013000 0 0xbc>; 481 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 482 clocks = <&infracfg CLK_INFRA_CEC>; 483 status = "disabled"; 484 }; 485 486 vpu: vpu@10020000 { 487 compatible = "mediatek,mt8173-vpu"; 488 reg = <0 0x10020000 0 0x30000>, 489 <0 0x10050000 0 0x100>; 490 reg-names = "tcm", "cfg_reg"; 491 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&topckgen CLK_TOP_SCP_SEL>; 493 clock-names = "main"; 494 memory-region = <&vpu_dma_reserved>; 495 }; 496 497 sysirq: intpol-controller@10200620 { 498 compatible = "mediatek,mt8173-sysirq", 499 "mediatek,mt6577-sysirq"; 500 interrupt-controller; 501 #interrupt-cells = <3>; 502 interrupt-parent = <&gic>; 503 reg = <0 0x10200620 0 0x20>; 504 }; 505 506 iommu: iommu@10205000 { 507 compatible = "mediatek,mt8173-m4u"; 508 reg = <0 0x10205000 0 0x1000>; 509 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 510 clocks = <&infracfg CLK_INFRA_M4U>; 511 clock-names = "bclk"; 512 mediatek,larbs = <&larb0 &larb1 &larb2 513 &larb3 &larb4 &larb5>; 514 #iommu-cells = <1>; 515 }; 516 517 efuse: efuse@10206000 { 518 compatible = "mediatek,mt8173-efuse"; 519 reg = <0 0x10206000 0 0x1000>; 520 #address-cells = <1>; 521 #size-cells = <1>; 522 thermal_calibration: calib@528 { 523 reg = <0x528 0xc>; 524 }; 525 }; 526 527 apmixedsys: clock-controller@10209000 { 528 compatible = "mediatek,mt8173-apmixedsys"; 529 reg = <0 0x10209000 0 0x1000>; 530 #clock-cells = <1>; 531 }; 532 533 hdmi_phy: hdmi-phy@10209100 { 534 compatible = "mediatek,mt8173-hdmi-phy"; 535 reg = <0 0x10209100 0 0x24>; 536 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 537 clock-names = "pll_ref"; 538 clock-output-names = "hdmitx_dig_cts"; 539 mediatek,ibias = <0xa>; 540 mediatek,ibias_up = <0x1c>; 541 #clock-cells = <0>; 542 #phy-cells = <0>; 543 status = "disabled"; 544 }; 545 546 gce: mailbox@10212000 { 547 compatible = "mediatek,mt8173-gce"; 548 reg = <0 0x10212000 0 0x1000>; 549 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 550 clocks = <&infracfg CLK_INFRA_GCE>; 551 clock-names = "gce"; 552 #mbox-cells = <3>; 553 }; 554 555 mipi_tx0: mipi-dphy@10215000 { 556 compatible = "mediatek,mt8173-mipi-tx"; 557 reg = <0 0x10215000 0 0x1000>; 558 clocks = <&clk26m>; 559 clock-output-names = "mipi_tx0_pll"; 560 #clock-cells = <0>; 561 #phy-cells = <0>; 562 status = "disabled"; 563 }; 564 565 mipi_tx1: mipi-dphy@10216000 { 566 compatible = "mediatek,mt8173-mipi-tx"; 567 reg = <0 0x10216000 0 0x1000>; 568 clocks = <&clk26m>; 569 clock-output-names = "mipi_tx1_pll"; 570 #clock-cells = <0>; 571 #phy-cells = <0>; 572 status = "disabled"; 573 }; 574 575 gic: interrupt-controller@10220000 { 576 compatible = "arm,gic-400"; 577 #interrupt-cells = <3>; 578 interrupt-parent = <&gic>; 579 interrupt-controller; 580 reg = <0 0x10221000 0 0x1000>, 581 <0 0x10222000 0 0x2000>, 582 <0 0x10224000 0 0x2000>, 583 <0 0x10226000 0 0x2000>; 584 interrupts = <GIC_PPI 9 585 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 586 }; 587 588 auxadc: auxadc@11001000 { 589 compatible = "mediatek,mt8173-auxadc"; 590 reg = <0 0x11001000 0 0x1000>; 591 clocks = <&pericfg CLK_PERI_AUXADC>; 592 clock-names = "main"; 593 #io-channel-cells = <1>; 594 }; 595 596 uart0: serial@11002000 { 597 compatible = "mediatek,mt8173-uart", 598 "mediatek,mt6577-uart"; 599 reg = <0 0x11002000 0 0x400>; 600 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 601 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 602 clock-names = "baud", "bus"; 603 status = "disabled"; 604 }; 605 606 uart1: serial@11003000 { 607 compatible = "mediatek,mt8173-uart", 608 "mediatek,mt6577-uart"; 609 reg = <0 0x11003000 0 0x400>; 610 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 611 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 612 clock-names = "baud", "bus"; 613 status = "disabled"; 614 }; 615 616 uart2: serial@11004000 { 617 compatible = "mediatek,mt8173-uart", 618 "mediatek,mt6577-uart"; 619 reg = <0 0x11004000 0 0x400>; 620 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 621 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 622 clock-names = "baud", "bus"; 623 status = "disabled"; 624 }; 625 626 uart3: serial@11005000 { 627 compatible = "mediatek,mt8173-uart", 628 "mediatek,mt6577-uart"; 629 reg = <0 0x11005000 0 0x400>; 630 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 631 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 632 clock-names = "baud", "bus"; 633 status = "disabled"; 634 }; 635 636 i2c0: i2c@11007000 { 637 compatible = "mediatek,mt8173-i2c"; 638 reg = <0 0x11007000 0 0x70>, 639 <0 0x11000100 0 0x80>; 640 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 641 clock-div = <16>; 642 clocks = <&pericfg CLK_PERI_I2C0>, 643 <&pericfg CLK_PERI_AP_DMA>; 644 clock-names = "main", "dma"; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&i2c0_pins_a>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 i2c1: i2c@11008000 { 653 compatible = "mediatek,mt8173-i2c"; 654 reg = <0 0x11008000 0 0x70>, 655 <0 0x11000180 0 0x80>; 656 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 657 clock-div = <16>; 658 clocks = <&pericfg CLK_PERI_I2C1>, 659 <&pericfg CLK_PERI_AP_DMA>; 660 clock-names = "main", "dma"; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&i2c1_pins_a>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 i2c2: i2c@11009000 { 669 compatible = "mediatek,mt8173-i2c"; 670 reg = <0 0x11009000 0 0x70>, 671 <0 0x11000200 0 0x80>; 672 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 673 clock-div = <16>; 674 clocks = <&pericfg CLK_PERI_I2C2>, 675 <&pericfg CLK_PERI_AP_DMA>; 676 clock-names = "main", "dma"; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&i2c2_pins_a>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 spi: spi@1100a000 { 685 compatible = "mediatek,mt8173-spi"; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 reg = <0 0x1100a000 0 0x1000>; 689 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 690 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 691 <&topckgen CLK_TOP_SPI_SEL>, 692 <&pericfg CLK_PERI_SPI0>; 693 clock-names = "parent-clk", "sel-clk", "spi-clk"; 694 status = "disabled"; 695 }; 696 697 thermal: thermal@1100b000 { 698 #thermal-sensor-cells = <0>; 699 compatible = "mediatek,mt8173-thermal"; 700 reg = <0 0x1100b000 0 0x1000>; 701 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 702 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 703 clock-names = "therm", "auxadc"; 704 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 705 mediatek,auxadc = <&auxadc>; 706 mediatek,apmixedsys = <&apmixedsys>; 707 nvmem-cells = <&thermal_calibration>; 708 nvmem-cell-names = "calibration-data"; 709 }; 710 711 nor_flash: spi@1100d000 { 712 compatible = "mediatek,mt8173-nor"; 713 reg = <0 0x1100d000 0 0xe0>; 714 clocks = <&pericfg CLK_PERI_SPI>, 715 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 716 clock-names = "spi", "sf"; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 i2c3: i2c@11010000 { 723 compatible = "mediatek,mt8173-i2c"; 724 reg = <0 0x11010000 0 0x70>, 725 <0 0x11000280 0 0x80>; 726 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 727 clock-div = <16>; 728 clocks = <&pericfg CLK_PERI_I2C3>, 729 <&pericfg CLK_PERI_AP_DMA>; 730 clock-names = "main", "dma"; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&i2c3_pins_a>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 status = "disabled"; 736 }; 737 738 i2c4: i2c@11011000 { 739 compatible = "mediatek,mt8173-i2c"; 740 reg = <0 0x11011000 0 0x70>, 741 <0 0x11000300 0 0x80>; 742 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 743 clock-div = <16>; 744 clocks = <&pericfg CLK_PERI_I2C4>, 745 <&pericfg CLK_PERI_AP_DMA>; 746 clock-names = "main", "dma"; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&i2c4_pins_a>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 status = "disabled"; 752 }; 753 754 hdmiddc0: i2c@11012000 { 755 compatible = "mediatek,mt8173-hdmi-ddc"; 756 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 757 reg = <0 0x11012000 0 0x1C>; 758 clocks = <&pericfg CLK_PERI_I2C5>; 759 clock-names = "ddc-i2c"; 760 }; 761 762 i2c6: i2c@11013000 { 763 compatible = "mediatek,mt8173-i2c"; 764 reg = <0 0x11013000 0 0x70>, 765 <0 0x11000080 0 0x80>; 766 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 767 clock-div = <16>; 768 clocks = <&pericfg CLK_PERI_I2C6>, 769 <&pericfg CLK_PERI_AP_DMA>; 770 clock-names = "main", "dma"; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&i2c6_pins_a>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 afe: audio-controller@11220000 { 779 compatible = "mediatek,mt8173-afe-pcm"; 780 reg = <0 0x11220000 0 0x1000>; 781 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 782 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 783 clocks = <&infracfg CLK_INFRA_AUDIO>, 784 <&topckgen CLK_TOP_AUDIO_SEL>, 785 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 786 <&topckgen CLK_TOP_APLL1_DIV0>, 787 <&topckgen CLK_TOP_APLL2_DIV0>, 788 <&topckgen CLK_TOP_I2S0_M_SEL>, 789 <&topckgen CLK_TOP_I2S1_M_SEL>, 790 <&topckgen CLK_TOP_I2S2_M_SEL>, 791 <&topckgen CLK_TOP_I2S3_M_SEL>, 792 <&topckgen CLK_TOP_I2S3_B_SEL>; 793 clock-names = "infra_sys_audio_clk", 794 "top_pdn_audio", 795 "top_pdn_aud_intbus", 796 "bck0", 797 "bck1", 798 "i2s0_m", 799 "i2s1_m", 800 "i2s2_m", 801 "i2s3_m", 802 "i2s3_b"; 803 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 804 <&topckgen CLK_TOP_AUD_2_SEL>; 805 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 806 <&topckgen CLK_TOP_APLL2>; 807 }; 808 809 mmc0: mmc@11230000 { 810 compatible = "mediatek,mt8173-mmc"; 811 reg = <0 0x11230000 0 0x1000>; 812 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 813 clocks = <&pericfg CLK_PERI_MSDC30_0>, 814 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 815 clock-names = "source", "hclk"; 816 status = "disabled"; 817 }; 818 819 mmc1: mmc@11240000 { 820 compatible = "mediatek,mt8173-mmc"; 821 reg = <0 0x11240000 0 0x1000>; 822 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 823 clocks = <&pericfg CLK_PERI_MSDC30_1>, 824 <&topckgen CLK_TOP_AXI_SEL>; 825 clock-names = "source", "hclk"; 826 status = "disabled"; 827 }; 828 829 mmc2: mmc@11250000 { 830 compatible = "mediatek,mt8173-mmc"; 831 reg = <0 0x11250000 0 0x1000>; 832 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 833 clocks = <&pericfg CLK_PERI_MSDC30_2>, 834 <&topckgen CLK_TOP_AXI_SEL>; 835 clock-names = "source", "hclk"; 836 status = "disabled"; 837 }; 838 839 mmc3: mmc@11260000 { 840 compatible = "mediatek,mt8173-mmc"; 841 reg = <0 0x11260000 0 0x1000>; 842 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 843 clocks = <&pericfg CLK_PERI_MSDC30_3>, 844 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 845 clock-names = "source", "hclk"; 846 status = "disabled"; 847 }; 848 849 ssusb: usb@11271000 { 850 compatible = "mediatek,mt8173-mtu3"; 851 reg = <0 0x11271000 0 0x3000>, 852 <0 0x11280700 0 0x0100>; 853 reg-names = "mac", "ippc"; 854 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 855 phys = <&u2port0 PHY_TYPE_USB2>, 856 <&u3port0 PHY_TYPE_USB3>, 857 <&u2port1 PHY_TYPE_USB2>; 858 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 859 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 860 clock-names = "sys_ck", "ref_ck"; 861 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 862 #address-cells = <2>; 863 #size-cells = <2>; 864 ranges; 865 status = "disabled"; 866 867 usb_host: xhci@11270000 { 868 compatible = "mediatek,mt8173-xhci"; 869 reg = <0 0x11270000 0 0x1000>; 870 reg-names = "mac"; 871 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 872 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 873 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 874 clock-names = "sys_ck", "ref_ck"; 875 status = "disabled"; 876 }; 877 }; 878 879 u3phy: usb-phy@11290000 { 880 compatible = "mediatek,mt8173-u3phy"; 881 reg = <0 0x11290000 0 0x800>; 882 #address-cells = <2>; 883 #size-cells = <2>; 884 ranges; 885 status = "okay"; 886 887 u2port0: usb-phy@11290800 { 888 reg = <0 0x11290800 0 0x100>; 889 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 890 clock-names = "ref"; 891 #phy-cells = <1>; 892 status = "okay"; 893 }; 894 895 u3port0: usb-phy@11290900 { 896 reg = <0 0x11290900 0 0x700>; 897 clocks = <&clk26m>; 898 clock-names = "ref"; 899 #phy-cells = <1>; 900 status = "okay"; 901 }; 902 903 u2port1: usb-phy@11291000 { 904 reg = <0 0x11291000 0 0x100>; 905 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 906 clock-names = "ref"; 907 #phy-cells = <1>; 908 status = "okay"; 909 }; 910 }; 911 912 mmsys: clock-controller@14000000 { 913 compatible = "mediatek,mt8173-mmsys", "syscon"; 914 reg = <0 0x14000000 0 0x1000>; 915 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 916 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 917 assigned-clock-rates = <400000000>; 918 #clock-cells = <1>; 919 }; 920 921 mdp_rdma0: rdma@14001000 { 922 compatible = "mediatek,mt8173-mdp-rdma", 923 "mediatek,mt8173-mdp"; 924 reg = <0 0x14001000 0 0x1000>; 925 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 926 <&mmsys CLK_MM_MUTEX_32K>; 927 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 928 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 929 mediatek,larb = <&larb0>; 930 mediatek,vpu = <&vpu>; 931 }; 932 933 mdp_rdma1: rdma@14002000 { 934 compatible = "mediatek,mt8173-mdp-rdma"; 935 reg = <0 0x14002000 0 0x1000>; 936 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 937 <&mmsys CLK_MM_MUTEX_32K>; 938 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 939 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 940 mediatek,larb = <&larb4>; 941 }; 942 943 mdp_rsz0: rsz@14003000 { 944 compatible = "mediatek,mt8173-mdp-rsz"; 945 reg = <0 0x14003000 0 0x1000>; 946 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 947 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 948 }; 949 950 mdp_rsz1: rsz@14004000 { 951 compatible = "mediatek,mt8173-mdp-rsz"; 952 reg = <0 0x14004000 0 0x1000>; 953 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 954 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 955 }; 956 957 mdp_rsz2: rsz@14005000 { 958 compatible = "mediatek,mt8173-mdp-rsz"; 959 reg = <0 0x14005000 0 0x1000>; 960 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 961 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 962 }; 963 964 mdp_wdma0: wdma@14006000 { 965 compatible = "mediatek,mt8173-mdp-wdma"; 966 reg = <0 0x14006000 0 0x1000>; 967 clocks = <&mmsys CLK_MM_MDP_WDMA>; 968 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 969 iommus = <&iommu M4U_PORT_MDP_WDMA>; 970 mediatek,larb = <&larb0>; 971 }; 972 973 mdp_wrot0: wrot@14007000 { 974 compatible = "mediatek,mt8173-mdp-wrot"; 975 reg = <0 0x14007000 0 0x1000>; 976 clocks = <&mmsys CLK_MM_MDP_WROT0>; 977 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 978 iommus = <&iommu M4U_PORT_MDP_WROT0>; 979 mediatek,larb = <&larb0>; 980 }; 981 982 mdp_wrot1: wrot@14008000 { 983 compatible = "mediatek,mt8173-mdp-wrot"; 984 reg = <0 0x14008000 0 0x1000>; 985 clocks = <&mmsys CLK_MM_MDP_WROT1>; 986 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 987 iommus = <&iommu M4U_PORT_MDP_WROT1>; 988 mediatek,larb = <&larb4>; 989 }; 990 991 ovl0: ovl@1400c000 { 992 compatible = "mediatek,mt8173-disp-ovl"; 993 reg = <0 0x1400c000 0 0x1000>; 994 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 995 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 996 clocks = <&mmsys CLK_MM_DISP_OVL0>; 997 iommus = <&iommu M4U_PORT_DISP_OVL0>; 998 mediatek,larb = <&larb0>; 999 }; 1000 1001 ovl1: ovl@1400d000 { 1002 compatible = "mediatek,mt8173-disp-ovl"; 1003 reg = <0 0x1400d000 0 0x1000>; 1004 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1005 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1006 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1007 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1008 mediatek,larb = <&larb4>; 1009 }; 1010 1011 rdma0: rdma@1400e000 { 1012 compatible = "mediatek,mt8173-disp-rdma"; 1013 reg = <0 0x1400e000 0 0x1000>; 1014 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1015 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1016 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1017 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1018 mediatek,larb = <&larb0>; 1019 }; 1020 1021 rdma1: rdma@1400f000 { 1022 compatible = "mediatek,mt8173-disp-rdma"; 1023 reg = <0 0x1400f000 0 0x1000>; 1024 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1025 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1026 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1027 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1028 mediatek,larb = <&larb4>; 1029 }; 1030 1031 rdma2: rdma@14010000 { 1032 compatible = "mediatek,mt8173-disp-rdma"; 1033 reg = <0 0x14010000 0 0x1000>; 1034 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1035 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1036 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1037 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1038 mediatek,larb = <&larb4>; 1039 }; 1040 1041 wdma0: wdma@14011000 { 1042 compatible = "mediatek,mt8173-disp-wdma"; 1043 reg = <0 0x14011000 0 0x1000>; 1044 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1045 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1046 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1047 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1048 mediatek,larb = <&larb0>; 1049 }; 1050 1051 wdma1: wdma@14012000 { 1052 compatible = "mediatek,mt8173-disp-wdma"; 1053 reg = <0 0x14012000 0 0x1000>; 1054 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1055 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1056 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1057 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1058 mediatek,larb = <&larb4>; 1059 }; 1060 1061 color0: color@14013000 { 1062 compatible = "mediatek,mt8173-disp-color"; 1063 reg = <0 0x14013000 0 0x1000>; 1064 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1065 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1066 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1067 }; 1068 1069 color1: color@14014000 { 1070 compatible = "mediatek,mt8173-disp-color"; 1071 reg = <0 0x14014000 0 0x1000>; 1072 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1073 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1074 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1075 }; 1076 1077 aal@14015000 { 1078 compatible = "mediatek,mt8173-disp-aal"; 1079 reg = <0 0x14015000 0 0x1000>; 1080 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1081 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1082 clocks = <&mmsys CLK_MM_DISP_AAL>; 1083 }; 1084 1085 gamma@14016000 { 1086 compatible = "mediatek,mt8173-disp-gamma"; 1087 reg = <0 0x14016000 0 0x1000>; 1088 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1089 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1090 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1091 }; 1092 1093 merge@14017000 { 1094 compatible = "mediatek,mt8173-disp-merge"; 1095 reg = <0 0x14017000 0 0x1000>; 1096 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1097 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1098 }; 1099 1100 split0: split@14018000 { 1101 compatible = "mediatek,mt8173-disp-split"; 1102 reg = <0 0x14018000 0 0x1000>; 1103 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1104 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1105 }; 1106 1107 split1: split@14019000 { 1108 compatible = "mediatek,mt8173-disp-split"; 1109 reg = <0 0x14019000 0 0x1000>; 1110 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1111 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1112 }; 1113 1114 ufoe@1401a000 { 1115 compatible = "mediatek,mt8173-disp-ufoe"; 1116 reg = <0 0x1401a000 0 0x1000>; 1117 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1118 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1119 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1120 }; 1121 1122 dsi0: dsi@1401b000 { 1123 compatible = "mediatek,mt8173-dsi"; 1124 reg = <0 0x1401b000 0 0x1000>; 1125 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1126 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1127 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1128 <&mmsys CLK_MM_DSI0_DIGITAL>, 1129 <&mipi_tx0>; 1130 clock-names = "engine", "digital", "hs"; 1131 phys = <&mipi_tx0>; 1132 phy-names = "dphy"; 1133 status = "disabled"; 1134 }; 1135 1136 dsi1: dsi@1401c000 { 1137 compatible = "mediatek,mt8173-dsi"; 1138 reg = <0 0x1401c000 0 0x1000>; 1139 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1140 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1141 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1142 <&mmsys CLK_MM_DSI1_DIGITAL>, 1143 <&mipi_tx1>; 1144 clock-names = "engine", "digital", "hs"; 1145 phy = <&mipi_tx1>; 1146 phy-names = "dphy"; 1147 status = "disabled"; 1148 }; 1149 1150 dpi0: dpi@1401d000 { 1151 compatible = "mediatek,mt8173-dpi"; 1152 reg = <0 0x1401d000 0 0x1000>; 1153 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1154 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1155 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1156 <&mmsys CLK_MM_DPI_ENGINE>, 1157 <&apmixedsys CLK_APMIXED_TVDPLL>; 1158 clock-names = "pixel", "engine", "pll"; 1159 status = "disabled"; 1160 1161 port { 1162 dpi0_out: endpoint { 1163 remote-endpoint = <&hdmi0_in>; 1164 }; 1165 }; 1166 }; 1167 1168 pwm0: pwm@1401e000 { 1169 compatible = "mediatek,mt8173-disp-pwm", 1170 "mediatek,mt6595-disp-pwm"; 1171 reg = <0 0x1401e000 0 0x1000>; 1172 #pwm-cells = <2>; 1173 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1174 <&mmsys CLK_MM_DISP_PWM0MM>; 1175 clock-names = "main", "mm"; 1176 status = "disabled"; 1177 }; 1178 1179 pwm1: pwm@1401f000 { 1180 compatible = "mediatek,mt8173-disp-pwm", 1181 "mediatek,mt6595-disp-pwm"; 1182 reg = <0 0x1401f000 0 0x1000>; 1183 #pwm-cells = <2>; 1184 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1185 <&mmsys CLK_MM_DISP_PWM1MM>; 1186 clock-names = "main", "mm"; 1187 status = "disabled"; 1188 }; 1189 1190 mutex: mutex@14020000 { 1191 compatible = "mediatek,mt8173-disp-mutex"; 1192 reg = <0 0x14020000 0 0x1000>; 1193 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1194 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1195 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1196 }; 1197 1198 larb0: larb@14021000 { 1199 compatible = "mediatek,mt8173-smi-larb"; 1200 reg = <0 0x14021000 0 0x1000>; 1201 mediatek,smi = <&smi_common>; 1202 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1203 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1204 <&mmsys CLK_MM_SMI_LARB0>; 1205 clock-names = "apb", "smi"; 1206 }; 1207 1208 smi_common: smi@14022000 { 1209 compatible = "mediatek,mt8173-smi-common"; 1210 reg = <0 0x14022000 0 0x1000>; 1211 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1212 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1213 <&mmsys CLK_MM_SMI_COMMON>; 1214 clock-names = "apb", "smi"; 1215 }; 1216 1217 od@14023000 { 1218 compatible = "mediatek,mt8173-disp-od"; 1219 reg = <0 0x14023000 0 0x1000>; 1220 clocks = <&mmsys CLK_MM_DISP_OD>; 1221 }; 1222 1223 hdmi0: hdmi@14025000 { 1224 compatible = "mediatek,mt8173-hdmi"; 1225 reg = <0 0x14025000 0 0x400>; 1226 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1227 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1228 <&mmsys CLK_MM_HDMI_PLLCK>, 1229 <&mmsys CLK_MM_HDMI_AUDIO>, 1230 <&mmsys CLK_MM_HDMI_SPDIF>; 1231 clock-names = "pixel", "pll", "bclk", "spdif"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&hdmi_pin>; 1234 phys = <&hdmi_phy>; 1235 phy-names = "hdmi"; 1236 mediatek,syscon-hdmi = <&mmsys 0x900>; 1237 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1238 assigned-clock-parents = <&hdmi_phy>; 1239 status = "disabled"; 1240 1241 ports { 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 1245 port@0 { 1246 reg = <0>; 1247 1248 hdmi0_in: endpoint { 1249 remote-endpoint = <&dpi0_out>; 1250 }; 1251 }; 1252 }; 1253 }; 1254 1255 larb4: larb@14027000 { 1256 compatible = "mediatek,mt8173-smi-larb"; 1257 reg = <0 0x14027000 0 0x1000>; 1258 mediatek,smi = <&smi_common>; 1259 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1260 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1261 <&mmsys CLK_MM_SMI_LARB4>; 1262 clock-names = "apb", "smi"; 1263 }; 1264 1265 imgsys: clock-controller@15000000 { 1266 compatible = "mediatek,mt8173-imgsys", "syscon"; 1267 reg = <0 0x15000000 0 0x1000>; 1268 #clock-cells = <1>; 1269 }; 1270 1271 larb2: larb@15001000 { 1272 compatible = "mediatek,mt8173-smi-larb"; 1273 reg = <0 0x15001000 0 0x1000>; 1274 mediatek,smi = <&smi_common>; 1275 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1276 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1277 <&imgsys CLK_IMG_LARB2_SMI>; 1278 clock-names = "apb", "smi"; 1279 }; 1280 1281 vdecsys: clock-controller@16000000 { 1282 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1283 reg = <0 0x16000000 0 0x1000>; 1284 #clock-cells = <1>; 1285 }; 1286 1287 vcodec_dec: vcodec@16000000 { 1288 compatible = "mediatek,mt8173-vcodec-dec"; 1289 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1290 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1291 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1292 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1293 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1294 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1295 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1296 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1297 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1298 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1299 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1300 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1301 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1302 mediatek,larb = <&larb1>; 1303 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1304 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1305 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1306 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1307 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1308 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1309 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1310 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1311 mediatek,vpu = <&vpu>; 1312 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1313 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1314 <&topckgen CLK_TOP_UNIVPLL_D2>, 1315 <&topckgen CLK_TOP_CCI400_SEL>, 1316 <&topckgen CLK_TOP_VDEC_SEL>, 1317 <&topckgen CLK_TOP_VCODECPLL>, 1318 <&apmixedsys CLK_APMIXED_VENCPLL>, 1319 <&topckgen CLK_TOP_VENC_LT_SEL>, 1320 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1321 clock-names = "vcodecpll", 1322 "univpll_d2", 1323 "clk_cci400_sel", 1324 "vdec_sel", 1325 "vdecpll", 1326 "vencpll", 1327 "venc_lt_sel", 1328 "vdec_bus_clk_src"; 1329 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1330 <&topckgen CLK_TOP_CCI400_SEL>, 1331 <&topckgen CLK_TOP_VDEC_SEL>, 1332 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1333 <&apmixedsys CLK_APMIXED_VENCPLL>; 1334 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1335 <&topckgen CLK_TOP_UNIVPLL_D2>, 1336 <&topckgen CLK_TOP_VCODECPLL>; 1337 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1338 }; 1339 1340 larb1: larb@16010000 { 1341 compatible = "mediatek,mt8173-smi-larb"; 1342 reg = <0 0x16010000 0 0x1000>; 1343 mediatek,smi = <&smi_common>; 1344 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1345 clocks = <&vdecsys CLK_VDEC_CKEN>, 1346 <&vdecsys CLK_VDEC_LARB_CKEN>; 1347 clock-names = "apb", "smi"; 1348 }; 1349 1350 vencsys: clock-controller@18000000 { 1351 compatible = "mediatek,mt8173-vencsys", "syscon"; 1352 reg = <0 0x18000000 0 0x1000>; 1353 #clock-cells = <1>; 1354 }; 1355 1356 larb3: larb@18001000 { 1357 compatible = "mediatek,mt8173-smi-larb"; 1358 reg = <0 0x18001000 0 0x1000>; 1359 mediatek,smi = <&smi_common>; 1360 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1361 clocks = <&vencsys CLK_VENC_CKE1>, 1362 <&vencsys CLK_VENC_CKE0>; 1363 clock-names = "apb", "smi"; 1364 }; 1365 1366 vcodec_enc: vcodec@18002000 { 1367 compatible = "mediatek,mt8173-vcodec-enc"; 1368 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1369 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1370 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1371 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1372 mediatek,larb = <&larb3>, 1373 <&larb5>; 1374 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1375 <&iommu M4U_PORT_VENC_REC>, 1376 <&iommu M4U_PORT_VENC_BSDMA>, 1377 <&iommu M4U_PORT_VENC_SV_COMV>, 1378 <&iommu M4U_PORT_VENC_RD_COMV>, 1379 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1380 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1381 <&iommu M4U_PORT_VENC_REF_LUMA>, 1382 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1383 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1384 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1385 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1386 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1387 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1388 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1389 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1390 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1391 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1392 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1393 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1394 mediatek,vpu = <&vpu>; 1395 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1396 <&topckgen CLK_TOP_VENC_SEL>, 1397 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1398 <&topckgen CLK_TOP_VENC_LT_SEL>; 1399 clock-names = "venc_sel_src", 1400 "venc_sel", 1401 "venc_lt_sel_src", 1402 "venc_lt_sel"; 1403 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1404 <&topckgen CLK_TOP_VENC_LT_SEL>; 1405 assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1406 <&topckgen CLK_TOP_UNIVPLL1_D2>; 1407 }; 1408 1409 jpegdec: jpegdec@18004000 { 1410 compatible = "mediatek,mt8173-jpgdec"; 1411 reg = <0 0x18004000 0 0x1000>; 1412 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1413 clocks = <&vencsys CLK_VENC_CKE0>, 1414 <&vencsys CLK_VENC_CKE3>; 1415 clock-names = "jpgdec-smi", 1416 "jpgdec"; 1417 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1418 mediatek,larb = <&larb3>; 1419 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1420 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1421 }; 1422 1423 vencltsys: clock-controller@19000000 { 1424 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1425 reg = <0 0x19000000 0 0x1000>; 1426 #clock-cells = <1>; 1427 }; 1428 1429 larb5: larb@19001000 { 1430 compatible = "mediatek,mt8173-smi-larb"; 1431 reg = <0 0x19001000 0 0x1000>; 1432 mediatek,smi = <&smi_common>; 1433 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1434 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1435 <&vencltsys CLK_VENCLT_CKE0>; 1436 clock-names = "apb", "smi"; 1437 }; 1438 }; 1439}; 1440 1441