1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/power/mt8173-power.h> 18#include <dt-bindings/reset-controller/mt8173-resets.h> 19#include "mt8173-pinfunc.h" 20 21/ { 22 compatible = "mediatek,mt8173"; 23 interrupt-parent = <&sysirq>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu-map { 32 cluster0 { 33 core0 { 34 cpu = <&cpu0>; 35 }; 36 core1 { 37 cpu = <&cpu1>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu2>; 44 }; 45 core1 { 46 cpu = <&cpu3>; 47 }; 48 }; 49 }; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x000>; 55 enable-method = "psci"; 56 cpu-idle-states = <&CPU_SLEEP_0>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x001>; 63 enable-method = "psci"; 64 cpu-idle-states = <&CPU_SLEEP_0>; 65 }; 66 67 cpu2: cpu@100 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a57"; 70 reg = <0x100>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 }; 74 75 cpu3: cpu@101 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a57"; 78 reg = <0x101>; 79 enable-method = "psci"; 80 cpu-idle-states = <&CPU_SLEEP_0>; 81 }; 82 83 idle-states { 84 entry-method = "psci"; 85 86 CPU_SLEEP_0: cpu-sleep-0 { 87 compatible = "arm,idle-state"; 88 local-timer-stop; 89 entry-latency-us = <639>; 90 exit-latency-us = <680>; 91 min-residency-us = <1088>; 92 arm,psci-suspend-param = <0x0010000>; 93 }; 94 }; 95 }; 96 97 psci { 98 compatible = "arm,psci"; 99 method = "smc"; 100 cpu_suspend = <0x84000001>; 101 cpu_off = <0x84000002>; 102 cpu_on = <0x84000003>; 103 }; 104 105 clk26m: oscillator@0 { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <26000000>; 109 clock-output-names = "clk26m"; 110 }; 111 112 clk32k: oscillator@1 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <32000>; 116 clock-output-names = "clk32k"; 117 }; 118 119 cpum_ck: oscillator@2 { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <0>; 123 clock-output-names = "cpum_ck"; 124 }; 125 126 timer { 127 compatible = "arm,armv8-timer"; 128 interrupt-parent = <&gic>; 129 interrupts = <GIC_PPI 13 130 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 131 <GIC_PPI 14 132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 11 134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 10 136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 137 }; 138 139 soc { 140 #address-cells = <2>; 141 #size-cells = <2>; 142 compatible = "simple-bus"; 143 ranges; 144 145 topckgen: clock-controller@10000000 { 146 compatible = "mediatek,mt8173-topckgen"; 147 reg = <0 0x10000000 0 0x1000>; 148 #clock-cells = <1>; 149 }; 150 151 infracfg: power-controller@10001000 { 152 compatible = "mediatek,mt8173-infracfg", "syscon"; 153 reg = <0 0x10001000 0 0x1000>; 154 #clock-cells = <1>; 155 #reset-cells = <1>; 156 }; 157 158 pericfg: power-controller@10003000 { 159 compatible = "mediatek,mt8173-pericfg", "syscon"; 160 reg = <0 0x10003000 0 0x1000>; 161 #clock-cells = <1>; 162 #reset-cells = <1>; 163 }; 164 165 syscfg_pctl_a: syscfg_pctl_a@10005000 { 166 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 167 reg = <0 0x10005000 0 0x1000>; 168 }; 169 170 pio: pinctrl@0x10005000 { 171 compatible = "mediatek,mt8173-pinctrl"; 172 reg = <0 0x1000b000 0 0x1000>; 173 mediatek,pctl-regmap = <&syscfg_pctl_a>; 174 pins-are-numbered; 175 gpio-controller; 176 #gpio-cells = <2>; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 182 183 i2c0_pins_a: i2c0 { 184 pins1 { 185 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 186 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 187 bias-disable; 188 }; 189 }; 190 191 i2c1_pins_a: i2c1 { 192 pins1 { 193 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 194 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 195 bias-disable; 196 }; 197 }; 198 199 i2c2_pins_a: i2c2 { 200 pins1 { 201 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 202 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 203 bias-disable; 204 }; 205 }; 206 207 i2c3_pins_a: i2c3 { 208 pins1 { 209 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 210 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 211 bias-disable; 212 }; 213 }; 214 215 i2c4_pins_a: i2c4 { 216 pins1 { 217 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 218 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 219 bias-disable; 220 }; 221 }; 222 223 i2c6_pins_a: i2c6 { 224 pins1 { 225 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 226 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 227 bias-disable; 228 }; 229 }; 230 }; 231 232 scpsys: scpsys@10006000 { 233 compatible = "mediatek,mt8173-scpsys"; 234 #power-domain-cells = <1>; 235 reg = <0 0x10006000 0 0x1000>; 236 clocks = <&clk26m>, 237 <&topckgen CLK_TOP_MM_SEL>, 238 <&topckgen CLK_TOP_VENC_SEL>, 239 <&topckgen CLK_TOP_VENC_LT_SEL>; 240 clock-names = "mfg", "mm", "venc", "venc_lt"; 241 infracfg = <&infracfg>; 242 }; 243 244 watchdog: watchdog@10007000 { 245 compatible = "mediatek,mt8173-wdt", 246 "mediatek,mt6589-wdt"; 247 reg = <0 0x10007000 0 0x100>; 248 }; 249 250 timer: timer@10008000 { 251 compatible = "mediatek,mt8173-timer", 252 "mediatek,mt6577-timer"; 253 reg = <0 0x10008000 0 0x1000>; 254 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 255 clocks = <&infracfg CLK_INFRA_CLK_13M>, 256 <&topckgen CLK_TOP_RTC_SEL>; 257 }; 258 259 pwrap: pwrap@1000d000 { 260 compatible = "mediatek,mt8173-pwrap"; 261 reg = <0 0x1000d000 0 0x1000>; 262 reg-names = "pwrap"; 263 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 264 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 265 reset-names = "pwrap"; 266 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 267 clock-names = "spi", "wrap"; 268 }; 269 270 sysirq: intpol-controller@10200620 { 271 compatible = "mediatek,mt8173-sysirq", 272 "mediatek,mt6577-sysirq"; 273 interrupt-controller; 274 #interrupt-cells = <3>; 275 interrupt-parent = <&gic>; 276 reg = <0 0x10200620 0 0x20>; 277 }; 278 279 apmixedsys: clock-controller@10209000 { 280 compatible = "mediatek,mt8173-apmixedsys"; 281 reg = <0 0x10209000 0 0x1000>; 282 #clock-cells = <1>; 283 }; 284 285 gic: interrupt-controller@10220000 { 286 compatible = "arm,gic-400"; 287 #interrupt-cells = <3>; 288 interrupt-parent = <&gic>; 289 interrupt-controller; 290 reg = <0 0x10221000 0 0x1000>, 291 <0 0x10222000 0 0x2000>, 292 <0 0x10224000 0 0x2000>, 293 <0 0x10226000 0 0x2000>; 294 interrupts = <GIC_PPI 9 295 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 296 }; 297 298 uart0: serial@11002000 { 299 compatible = "mediatek,mt8173-uart", 300 "mediatek,mt6577-uart"; 301 reg = <0 0x11002000 0 0x400>; 302 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 303 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 304 clock-names = "baud", "bus"; 305 status = "disabled"; 306 }; 307 308 uart1: serial@11003000 { 309 compatible = "mediatek,mt8173-uart", 310 "mediatek,mt6577-uart"; 311 reg = <0 0x11003000 0 0x400>; 312 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 313 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 314 clock-names = "baud", "bus"; 315 status = "disabled"; 316 }; 317 318 uart2: serial@11004000 { 319 compatible = "mediatek,mt8173-uart", 320 "mediatek,mt6577-uart"; 321 reg = <0 0x11004000 0 0x400>; 322 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 323 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 324 clock-names = "baud", "bus"; 325 status = "disabled"; 326 }; 327 328 uart3: serial@11005000 { 329 compatible = "mediatek,mt8173-uart", 330 "mediatek,mt6577-uart"; 331 reg = <0 0x11005000 0 0x400>; 332 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 333 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 334 clock-names = "baud", "bus"; 335 status = "disabled"; 336 }; 337 338 i2c0: i2c@11007000 { 339 compatible = "mediatek,mt8173-i2c"; 340 reg = <0 0x11007000 0 0x70>, 341 <0 0x11000100 0 0x80>; 342 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 343 clock-div = <16>; 344 clocks = <&pericfg CLK_PERI_I2C0>, 345 <&pericfg CLK_PERI_AP_DMA>; 346 clock-names = "main", "dma"; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c0_pins_a>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 }; 353 354 i2c1: i2c@11008000 { 355 compatible = "mediatek,mt8173-i2c"; 356 reg = <0 0x11008000 0 0x70>, 357 <0 0x11000180 0 0x80>; 358 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 359 clock-div = <16>; 360 clocks = <&pericfg CLK_PERI_I2C1>, 361 <&pericfg CLK_PERI_AP_DMA>; 362 clock-names = "main", "dma"; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&i2c1_pins_a>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 status = "disabled"; 368 }; 369 370 i2c2: i2c@11009000 { 371 compatible = "mediatek,mt8173-i2c"; 372 reg = <0 0x11009000 0 0x70>, 373 <0 0x11000200 0 0x80>; 374 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 375 clock-div = <16>; 376 clocks = <&pericfg CLK_PERI_I2C2>, 377 <&pericfg CLK_PERI_AP_DMA>; 378 clock-names = "main", "dma"; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c2_pins_a>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 status = "disabled"; 384 }; 385 386 spi: spi@1100a000 { 387 compatible = "mediatek,mt8173-spi"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0 0x1100a000 0 0x1000>; 391 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 392 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 393 <&topckgen CLK_TOP_SPI_SEL>, 394 <&pericfg CLK_PERI_SPI0>; 395 clock-names = "parent-clk", "sel-clk", "spi-clk"; 396 status = "disabled"; 397 }; 398 399 i2c3: i2c@11010000 { 400 compatible = "mediatek,mt8173-i2c"; 401 reg = <0 0x11010000 0 0x70>, 402 <0 0x11000280 0 0x80>; 403 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 404 clock-div = <16>; 405 clocks = <&pericfg CLK_PERI_I2C3>, 406 <&pericfg CLK_PERI_AP_DMA>; 407 clock-names = "main", "dma"; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c3_pins_a>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i2c4: i2c@11011000 { 416 compatible = "mediatek,mt8173-i2c"; 417 reg = <0 0x11011000 0 0x70>, 418 <0 0x11000300 0 0x80>; 419 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 420 clock-div = <16>; 421 clocks = <&pericfg CLK_PERI_I2C4>, 422 <&pericfg CLK_PERI_AP_DMA>; 423 clock-names = "main", "dma"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&i2c4_pins_a>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c6: i2c@11013000 { 432 compatible = "mediatek,mt8173-i2c"; 433 reg = <0 0x11013000 0 0x70>, 434 <0 0x11000080 0 0x80>; 435 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 436 clock-div = <16>; 437 clocks = <&pericfg CLK_PERI_I2C6>, 438 <&pericfg CLK_PERI_AP_DMA>; 439 clock-names = "main", "dma"; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2c6_pins_a>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 afe: audio-controller@11220000 { 448 compatible = "mediatek,mt8173-afe-pcm"; 449 reg = <0 0x11220000 0 0x1000>; 450 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 451 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 452 clocks = <&infracfg CLK_INFRA_AUDIO>, 453 <&topckgen CLK_TOP_AUDIO_SEL>, 454 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 455 <&topckgen CLK_TOP_APLL1_DIV0>, 456 <&topckgen CLK_TOP_APLL2_DIV0>, 457 <&topckgen CLK_TOP_I2S0_M_SEL>, 458 <&topckgen CLK_TOP_I2S1_M_SEL>, 459 <&topckgen CLK_TOP_I2S2_M_SEL>, 460 <&topckgen CLK_TOP_I2S3_M_SEL>, 461 <&topckgen CLK_TOP_I2S3_B_SEL>; 462 clock-names = "infra_sys_audio_clk", 463 "top_pdn_audio", 464 "top_pdn_aud_intbus", 465 "bck0", 466 "bck1", 467 "i2s0_m", 468 "i2s1_m", 469 "i2s2_m", 470 "i2s3_m", 471 "i2s3_b"; 472 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 473 <&topckgen CLK_TOP_AUD_2_SEL>; 474 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 475 <&topckgen CLK_TOP_APLL2>; 476 }; 477 478 mmc0: mmc@11230000 { 479 compatible = "mediatek,mt8173-mmc", 480 "mediatek,mt8135-mmc"; 481 reg = <0 0x11230000 0 0x1000>; 482 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 483 clocks = <&pericfg CLK_PERI_MSDC30_0>, 484 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 485 clock-names = "source", "hclk"; 486 status = "disabled"; 487 }; 488 489 mmc1: mmc@11240000 { 490 compatible = "mediatek,mt8173-mmc", 491 "mediatek,mt8135-mmc"; 492 reg = <0 0x11240000 0 0x1000>; 493 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 494 clocks = <&pericfg CLK_PERI_MSDC30_1>, 495 <&topckgen CLK_TOP_AXI_SEL>; 496 clock-names = "source", "hclk"; 497 status = "disabled"; 498 }; 499 500 mmc2: mmc@11250000 { 501 compatible = "mediatek,mt8173-mmc", 502 "mediatek,mt8135-mmc"; 503 reg = <0 0x11250000 0 0x1000>; 504 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 505 clocks = <&pericfg CLK_PERI_MSDC30_2>, 506 <&topckgen CLK_TOP_AXI_SEL>; 507 clock-names = "source", "hclk"; 508 status = "disabled"; 509 }; 510 511 mmc3: mmc@11260000 { 512 compatible = "mediatek,mt8173-mmc", 513 "mediatek,mt8135-mmc"; 514 reg = <0 0x11260000 0 0x1000>; 515 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 516 clocks = <&pericfg CLK_PERI_MSDC30_3>, 517 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 518 clock-names = "source", "hclk"; 519 status = "disabled"; 520 }; 521 522 mmsys: clock-controller@14000000 { 523 compatible = "mediatek,mt8173-mmsys", "syscon"; 524 reg = <0 0x14000000 0 0x1000>; 525 #clock-cells = <1>; 526 }; 527 528 imgsys: clock-controller@15000000 { 529 compatible = "mediatek,mt8173-imgsys", "syscon"; 530 reg = <0 0x15000000 0 0x1000>; 531 #clock-cells = <1>; 532 }; 533 534 vdecsys: clock-controller@16000000 { 535 compatible = "mediatek,mt8173-vdecsys", "syscon"; 536 reg = <0 0x16000000 0 0x1000>; 537 #clock-cells = <1>; 538 }; 539 540 vencsys: clock-controller@18000000 { 541 compatible = "mediatek,mt8173-vencsys", "syscon"; 542 reg = <0 0x18000000 0 0x1000>; 543 #clock-cells = <1>; 544 }; 545 546 vencltsys: clock-controller@19000000 { 547 compatible = "mediatek,mt8173-vencltsys", "syscon"; 548 reg = <0 0x19000000 0 0x1000>; 549 #clock-cells = <1>; 550 }; 551 }; 552}; 553 554