1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt8173-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/power/mt8173-power.h>
18#include <dt-bindings/reset-controller/mt8173-resets.h>
19#include "mt8173-pinfunc.h"
20
21/ {
22	compatible = "mediatek,mt8173";
23	interrupt-parent = <&sysirq>;
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu-map {
32			cluster0 {
33				core0 {
34					cpu = <&cpu0>;
35				};
36				core1 {
37					cpu = <&cpu1>;
38				};
39			};
40
41			cluster1 {
42				core0 {
43					cpu = <&cpu2>;
44				};
45				core1 {
46					cpu = <&cpu3>;
47				};
48			};
49		};
50
51		cpu0: cpu@0 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53";
54			reg = <0x000>;
55			enable-method = "psci";
56			cpu-idle-states = <&CPU_SLEEP_0>;
57		};
58
59		cpu1: cpu@1 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a53";
62			reg = <0x001>;
63			enable-method = "psci";
64			cpu-idle-states = <&CPU_SLEEP_0>;
65		};
66
67		cpu2: cpu@100 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a57";
70			reg = <0x100>;
71			enable-method = "psci";
72			cpu-idle-states = <&CPU_SLEEP_0>;
73		};
74
75		cpu3: cpu@101 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a57";
78			reg = <0x101>;
79			enable-method = "psci";
80			cpu-idle-states = <&CPU_SLEEP_0>;
81		};
82
83		idle-states {
84			entry-method = "arm,psci";
85
86			CPU_SLEEP_0: cpu-sleep-0 {
87				compatible = "arm,idle-state";
88				local-timer-stop;
89				entry-latency-us = <639>;
90				exit-latency-us = <680>;
91				min-residency-us = <1088>;
92				arm,psci-suspend-param = <0x0010000>;
93			};
94		};
95	};
96
97	psci {
98		compatible = "arm,psci";
99		method = "smc";
100		cpu_suspend   = <0x84000001>;
101		cpu_off	      = <0x84000002>;
102		cpu_on	      = <0x84000003>;
103	};
104
105	clk26m: oscillator@0 {
106		compatible = "fixed-clock";
107		#clock-cells = <0>;
108		clock-frequency = <26000000>;
109		clock-output-names = "clk26m";
110	};
111
112	clk32k: oscillator@1 {
113		compatible = "fixed-clock";
114		#clock-cells = <0>;
115		clock-frequency = <32000>;
116		clock-output-names = "clk32k";
117	};
118
119	timer {
120		compatible = "arm,armv8-timer";
121		interrupt-parent = <&gic>;
122		interrupts = <GIC_PPI 13
123			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
124			     <GIC_PPI 14
125			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
126			     <GIC_PPI 11
127			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128			     <GIC_PPI 10
129			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
130	};
131
132	soc {
133		#address-cells = <2>;
134		#size-cells = <2>;
135		compatible = "simple-bus";
136		ranges;
137
138		topckgen: clock-controller@10000000 {
139			compatible = "mediatek,mt8173-topckgen";
140			reg = <0 0x10000000 0 0x1000>;
141			#clock-cells = <1>;
142		};
143
144		infracfg: power-controller@10001000 {
145			compatible = "mediatek,mt8173-infracfg", "syscon";
146			reg = <0 0x10001000 0 0x1000>;
147			#clock-cells = <1>;
148			#reset-cells = <1>;
149		};
150
151		pericfg: power-controller@10003000 {
152			compatible = "mediatek,mt8173-pericfg", "syscon";
153			reg = <0 0x10003000 0 0x1000>;
154			#clock-cells = <1>;
155			#reset-cells = <1>;
156		};
157
158		syscfg_pctl_a: syscfg_pctl_a@10005000 {
159			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
160			reg = <0 0x10005000 0 0x1000>;
161		};
162
163		pio: pinctrl@0x10005000 {
164			compatible = "mediatek,mt8173-pinctrl";
165			reg = <0 0x1000b000 0 0x1000>;
166			mediatek,pctl-regmap = <&syscfg_pctl_a>;
167			pins-are-numbered;
168			gpio-controller;
169			#gpio-cells = <2>;
170			interrupt-controller;
171			#interrupt-cells = <2>;
172			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
173				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
174				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
175
176			i2c0_pins_a: i2c0 {
177				pins1 {
178					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
179						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
180					bias-disable;
181				};
182			};
183
184			i2c1_pins_a: i2c1 {
185				pins1 {
186					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
187						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
188					bias-disable;
189				};
190			};
191
192			i2c2_pins_a: i2c2 {
193				pins1 {
194					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
195						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
196					bias-disable;
197				};
198			};
199
200			i2c3_pins_a: i2c3 {
201				pins1 {
202					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
203						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
204					bias-disable;
205				};
206			};
207
208			i2c4_pins_a: i2c4 {
209				pins1 {
210					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
211						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
212					bias-disable;
213				};
214			};
215
216			i2c6_pins_a: i2c6 {
217				pins1 {
218					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
219						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
220					bias-disable;
221				};
222			};
223		};
224
225		scpsys: scpsys@10006000 {
226			compatible = "mediatek,mt8173-scpsys";
227			#power-domain-cells = <1>;
228			reg = <0 0x10006000 0 0x1000>;
229			clocks = <&clk26m>,
230				 <&topckgen CLK_TOP_MM_SEL>;
231			clock-names = "mfg", "mm";
232			infracfg = <&infracfg>;
233		};
234
235		watchdog: watchdog@10007000 {
236			compatible = "mediatek,mt8173-wdt",
237				     "mediatek,mt6589-wdt";
238			reg = <0 0x10007000 0 0x100>;
239		};
240
241		pwrap: pwrap@1000d000 {
242			compatible = "mediatek,mt8173-pwrap";
243			reg = <0 0x1000d000 0 0x1000>;
244			reg-names = "pwrap";
245			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
246			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
247			reset-names = "pwrap";
248			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
249			clock-names = "spi", "wrap";
250		};
251
252		sysirq: intpol-controller@10200620 {
253			compatible = "mediatek,mt8173-sysirq",
254				     "mediatek,mt6577-sysirq";
255			interrupt-controller;
256			#interrupt-cells = <3>;
257			interrupt-parent = <&gic>;
258			reg = <0 0x10200620 0 0x20>;
259		};
260
261		apmixedsys: clock-controller@10209000 {
262			compatible = "mediatek,mt8173-apmixedsys";
263			reg = <0 0x10209000 0 0x1000>;
264			#clock-cells = <1>;
265		};
266
267		gic: interrupt-controller@10220000 {
268			compatible = "arm,gic-400";
269			#interrupt-cells = <3>;
270			interrupt-parent = <&gic>;
271			interrupt-controller;
272			reg = <0 0x10221000 0 0x1000>,
273			      <0 0x10222000 0 0x2000>,
274			      <0 0x10224000 0 0x2000>,
275			      <0 0x10226000 0 0x2000>;
276			interrupts = <GIC_PPI 9
277				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
278		};
279
280		uart0: serial@11002000 {
281			compatible = "mediatek,mt8173-uart",
282				     "mediatek,mt6577-uart";
283			reg = <0 0x11002000 0 0x400>;
284			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
285			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
286			clock-names = "baud", "bus";
287			status = "disabled";
288		};
289
290		uart1: serial@11003000 {
291			compatible = "mediatek,mt8173-uart",
292				     "mediatek,mt6577-uart";
293			reg = <0 0x11003000 0 0x400>;
294			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
295			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
296			clock-names = "baud", "bus";
297			status = "disabled";
298		};
299
300		uart2: serial@11004000 {
301			compatible = "mediatek,mt8173-uart",
302				     "mediatek,mt6577-uart";
303			reg = <0 0x11004000 0 0x400>;
304			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
305			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
306			clock-names = "baud", "bus";
307			status = "disabled";
308		};
309
310		uart3: serial@11005000 {
311			compatible = "mediatek,mt8173-uart",
312				     "mediatek,mt6577-uart";
313			reg = <0 0x11005000 0 0x400>;
314			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
315			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
316			clock-names = "baud", "bus";
317			status = "disabled";
318		};
319
320		i2c0: i2c@11007000 {
321			compatible = "mediatek,mt8173-i2c";
322			reg = <0 0x11007000 0 0x70>,
323			      <0 0x11000100 0 0x80>;
324			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
325			clock-div = <16>;
326			clocks = <&pericfg CLK_PERI_I2C0>,
327				 <&pericfg CLK_PERI_AP_DMA>;
328			clock-names = "main", "dma";
329			pinctrl-names = "default";
330			pinctrl-0 = <&i2c0_pins_a>;
331			#address-cells = <1>;
332			#size-cells = <0>;
333			status = "disabled";
334		};
335
336		i2c1: i2c@11008000 {
337			compatible = "mediatek,mt8173-i2c";
338			reg = <0 0x11008000 0 0x70>,
339			      <0 0x11000180 0 0x80>;
340			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
341			clock-div = <16>;
342			clocks = <&pericfg CLK_PERI_I2C1>,
343				 <&pericfg CLK_PERI_AP_DMA>;
344			clock-names = "main", "dma";
345			pinctrl-names = "default";
346			pinctrl-0 = <&i2c1_pins_a>;
347			#address-cells = <1>;
348			#size-cells = <0>;
349			status = "disabled";
350		};
351
352		i2c2: i2c@11009000 {
353			compatible = "mediatek,mt8173-i2c";
354			reg = <0 0x11009000 0 0x70>,
355			      <0 0x11000200 0 0x80>;
356			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
357			clock-div = <16>;
358			clocks = <&pericfg CLK_PERI_I2C2>,
359				 <&pericfg CLK_PERI_AP_DMA>;
360			clock-names = "main", "dma";
361			pinctrl-names = "default";
362			pinctrl-0 = <&i2c2_pins_a>;
363			#address-cells = <1>;
364			#size-cells = <0>;
365			status = "disabled";
366		};
367
368		spi: spi@1100a000 {
369			compatible = "mediatek,mt8173-spi";
370			#address-cells = <1>;
371			#size-cells = <0>;
372			reg = <0 0x1100a000 0 0x1000>;
373			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
374			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
375				 <&topckgen CLK_TOP_SPI_SEL>,
376				 <&pericfg CLK_PERI_SPI0>;
377			clock-names = "parent-clk", "sel-clk", "spi-clk";
378			status = "disabled";
379		};
380
381		i2c3: i2c@11010000 {
382			compatible = "mediatek,mt8173-i2c";
383			reg = <0 0x11010000 0 0x70>,
384			      <0 0x11000280 0 0x80>;
385			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
386			clock-div = <16>;
387			clocks = <&pericfg CLK_PERI_I2C3>,
388				 <&pericfg CLK_PERI_AP_DMA>;
389			clock-names = "main", "dma";
390			pinctrl-names = "default";
391			pinctrl-0 = <&i2c3_pins_a>;
392			#address-cells = <1>;
393			#size-cells = <0>;
394			status = "disabled";
395		};
396
397		i2c4: i2c@11011000 {
398			compatible = "mediatek,mt8173-i2c";
399			reg = <0 0x11011000 0 0x70>,
400			      <0 0x11000300 0 0x80>;
401			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
402			clock-div = <16>;
403			clocks = <&pericfg CLK_PERI_I2C4>,
404				 <&pericfg CLK_PERI_AP_DMA>;
405			clock-names = "main", "dma";
406			pinctrl-names = "default";
407			pinctrl-0 = <&i2c4_pins_a>;
408			#address-cells = <1>;
409			#size-cells = <0>;
410			status = "disabled";
411		};
412
413		i2c6: i2c@11013000 {
414			compatible = "mediatek,mt8173-i2c";
415			reg = <0 0x11013000 0 0x70>,
416			      <0 0x11000080 0 0x80>;
417			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
418			clock-div = <16>;
419			clocks = <&pericfg CLK_PERI_I2C6>,
420				 <&pericfg CLK_PERI_AP_DMA>;
421			clock-names = "main", "dma";
422			pinctrl-names = "default";
423			pinctrl-0 = <&i2c6_pins_a>;
424			#address-cells = <1>;
425			#size-cells = <0>;
426			status = "disabled";
427		};
428
429		afe: audio-controller@11220000  {
430			compatible = "mediatek,mt8173-afe-pcm";
431			reg = <0 0x11220000 0 0x1000>;
432			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
433			power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
434			clocks = <&infracfg CLK_INFRA_AUDIO>,
435				 <&topckgen CLK_TOP_AUDIO_SEL>,
436				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
437				 <&topckgen CLK_TOP_APLL1_DIV0>,
438				 <&topckgen CLK_TOP_APLL2_DIV0>,
439				 <&topckgen CLK_TOP_I2S0_M_SEL>,
440				 <&topckgen CLK_TOP_I2S1_M_SEL>,
441				 <&topckgen CLK_TOP_I2S2_M_SEL>,
442				 <&topckgen CLK_TOP_I2S3_M_SEL>,
443				 <&topckgen CLK_TOP_I2S3_B_SEL>;
444			clock-names = "infra_sys_audio_clk",
445				      "top_pdn_audio",
446				      "top_pdn_aud_intbus",
447				      "bck0",
448				      "bck1",
449				      "i2s0_m",
450				      "i2s1_m",
451				      "i2s2_m",
452				      "i2s3_m",
453				      "i2s3_b";
454			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
455					  <&topckgen CLK_TOP_AUD_2_SEL>;
456			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
457						 <&topckgen CLK_TOP_APLL2>;
458		};
459
460		mmc0: mmc@11230000 {
461			compatible = "mediatek,mt8173-mmc",
462				     "mediatek,mt8135-mmc";
463			reg = <0 0x11230000 0 0x1000>;
464			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
465			clocks = <&pericfg CLK_PERI_MSDC30_0>,
466				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
467			clock-names = "source", "hclk";
468			status = "disabled";
469		};
470
471		mmc1: mmc@11240000 {
472			compatible = "mediatek,mt8173-mmc",
473				     "mediatek,mt8135-mmc";
474			reg = <0 0x11240000 0 0x1000>;
475			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
476			clocks = <&pericfg CLK_PERI_MSDC30_1>,
477				 <&topckgen CLK_TOP_AXI_SEL>;
478			clock-names = "source", "hclk";
479			status = "disabled";
480		};
481
482		mmc2: mmc@11250000 {
483			compatible = "mediatek,mt8173-mmc",
484				     "mediatek,mt8135-mmc";
485			reg = <0 0x11250000 0 0x1000>;
486			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
487			clocks = <&pericfg CLK_PERI_MSDC30_2>,
488				 <&topckgen CLK_TOP_AXI_SEL>;
489			clock-names = "source", "hclk";
490			status = "disabled";
491		};
492
493		mmc3: mmc@11260000 {
494			compatible = "mediatek,mt8173-mmc",
495				     "mediatek,mt8135-mmc";
496			reg = <0 0x11260000 0 0x1000>;
497			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
498			clocks = <&pericfg CLK_PERI_MSDC30_3>,
499				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
500			clock-names = "source", "hclk";
501			status = "disabled";
502		};
503	};
504};
505
506