1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt8173-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/reset-controller/mt8173-resets.h>
18#include "mt8173-pinfunc.h"
19
20/ {
21	compatible = "mediatek,mt8173";
22	interrupt-parent = <&sysirq>;
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu-map {
31			cluster0 {
32				core0 {
33					cpu = <&cpu0>;
34				};
35				core1 {
36					cpu = <&cpu1>;
37				};
38			};
39
40			cluster1 {
41				core0 {
42					cpu = <&cpu2>;
43				};
44				core1 {
45					cpu = <&cpu3>;
46				};
47			};
48		};
49
50		cpu0: cpu@0 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53";
53			reg = <0x000>;
54			enable-method = "psci";
55			cpu-idle-states = <&CPU_SLEEP_0>;
56		};
57
58		cpu1: cpu@1 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a53";
61			reg = <0x001>;
62			enable-method = "psci";
63			cpu-idle-states = <&CPU_SLEEP_0>;
64		};
65
66		cpu2: cpu@100 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a57";
69			reg = <0x100>;
70			enable-method = "psci";
71			cpu-idle-states = <&CPU_SLEEP_0>;
72		};
73
74		cpu3: cpu@101 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a57";
77			reg = <0x101>;
78			enable-method = "psci";
79			cpu-idle-states = <&CPU_SLEEP_0>;
80		};
81
82		idle-states {
83			entry-method = "arm,psci";
84
85			CPU_SLEEP_0: cpu-sleep-0 {
86				compatible = "arm,idle-state";
87				local-timer-stop;
88				entry-latency-us = <639>;
89				exit-latency-us = <680>;
90				min-residency-us = <1088>;
91				arm,psci-suspend-param = <0x0010000>;
92			};
93		};
94	};
95
96	psci {
97		compatible = "arm,psci";
98		method = "smc";
99		cpu_suspend   = <0x84000001>;
100		cpu_off	      = <0x84000002>;
101		cpu_on	      = <0x84000003>;
102	};
103
104	clk26m: oscillator@0 {
105		compatible = "fixed-clock";
106		#clock-cells = <0>;
107		clock-frequency = <26000000>;
108		clock-output-names = "clk26m";
109	};
110
111	clk32k: oscillator@1 {
112		compatible = "fixed-clock";
113		#clock-cells = <0>;
114		clock-frequency = <32000>;
115		clock-output-names = "clk32k";
116	};
117
118	timer {
119		compatible = "arm,armv8-timer";
120		interrupt-parent = <&gic>;
121		interrupts = <GIC_PPI 13
122			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
123			     <GIC_PPI 14
124			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125			     <GIC_PPI 11
126			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127			     <GIC_PPI 10
128			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
129	};
130
131	soc {
132		#address-cells = <2>;
133		#size-cells = <2>;
134		compatible = "simple-bus";
135		ranges;
136
137		topckgen: clock-controller@10000000 {
138			compatible = "mediatek,mt8173-topckgen";
139			reg = <0 0x10000000 0 0x1000>;
140			#clock-cells = <1>;
141		};
142
143		infracfg: power-controller@10001000 {
144			compatible = "mediatek,mt8173-infracfg", "syscon";
145			reg = <0 0x10001000 0 0x1000>;
146			#clock-cells = <1>;
147			#reset-cells = <1>;
148		};
149
150		pericfg: power-controller@10003000 {
151			compatible = "mediatek,mt8173-pericfg", "syscon";
152			reg = <0 0x10003000 0 0x1000>;
153			#clock-cells = <1>;
154			#reset-cells = <1>;
155		};
156
157		syscfg_pctl_a: syscfg_pctl_a@10005000 {
158			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
159			reg = <0 0x10005000 0 0x1000>;
160		};
161
162		pio: pinctrl@0x10005000 {
163			compatible = "mediatek,mt8173-pinctrl";
164			reg = <0 0x1000b000 0 0x1000>;
165			mediatek,pctl-regmap = <&syscfg_pctl_a>;
166			pins-are-numbered;
167			gpio-controller;
168			#gpio-cells = <2>;
169			interrupt-controller;
170			#interrupt-cells = <2>;
171			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
172				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
173				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
174
175			i2c0_pins_a: i2c0 {
176				pins1 {
177					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
178						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
179					bias-disable;
180				};
181			};
182
183			i2c1_pins_a: i2c1 {
184				pins1 {
185					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
186						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
187					bias-disable;
188				};
189			};
190
191			i2c2_pins_a: i2c2 {
192				pins1 {
193					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
194						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
195					bias-disable;
196				};
197			};
198
199			i2c3_pins_a: i2c3 {
200				pins1 {
201					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
202						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
203					bias-disable;
204				};
205			};
206
207			i2c4_pins_a: i2c4 {
208				pins1 {
209					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
210						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
211					bias-disable;
212				};
213			};
214
215			i2c6_pins_a: i2c6 {
216				pins1 {
217					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
218						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
219					bias-disable;
220				};
221			};
222		};
223
224		scpsys: scpsys@10006000 {
225			compatible = "mediatek,mt8173-scpsys";
226			#power-domain-cells = <1>;
227			reg = <0 0x10006000 0 0x1000>;
228			clocks = <&clk26m>,
229				 <&topckgen CLK_TOP_MM_SEL>;
230			clock-names = "mfg", "mm";
231			infracfg = <&infracfg>;
232		};
233
234		watchdog: watchdog@10007000 {
235			compatible = "mediatek,mt8173-wdt",
236				     "mediatek,mt6589-wdt";
237			reg = <0 0x10007000 0 0x100>;
238		};
239
240		pwrap: pwrap@1000d000 {
241			compatible = "mediatek,mt8173-pwrap";
242			reg = <0 0x1000d000 0 0x1000>;
243			reg-names = "pwrap";
244			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
245			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
246			reset-names = "pwrap";
247			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
248			clock-names = "spi", "wrap";
249		};
250
251		sysirq: intpol-controller@10200620 {
252			compatible = "mediatek,mt8173-sysirq",
253				     "mediatek,mt6577-sysirq";
254			interrupt-controller;
255			#interrupt-cells = <3>;
256			interrupt-parent = <&gic>;
257			reg = <0 0x10200620 0 0x20>;
258		};
259
260		apmixedsys: clock-controller@10209000 {
261			compatible = "mediatek,mt8173-apmixedsys";
262			reg = <0 0x10209000 0 0x1000>;
263			#clock-cells = <1>;
264		};
265
266		gic: interrupt-controller@10220000 {
267			compatible = "arm,gic-400";
268			#interrupt-cells = <3>;
269			interrupt-parent = <&gic>;
270			interrupt-controller;
271			reg = <0 0x10221000 0 0x1000>,
272			      <0 0x10222000 0 0x2000>,
273			      <0 0x10224000 0 0x2000>,
274			      <0 0x10226000 0 0x2000>;
275			interrupts = <GIC_PPI 9
276				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
277		};
278
279		uart0: serial@11002000 {
280			compatible = "mediatek,mt8173-uart",
281				     "mediatek,mt6577-uart";
282			reg = <0 0x11002000 0 0x400>;
283			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
284			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
285			clock-names = "baud", "bus";
286			status = "disabled";
287		};
288
289		uart1: serial@11003000 {
290			compatible = "mediatek,mt8173-uart",
291				     "mediatek,mt6577-uart";
292			reg = <0 0x11003000 0 0x400>;
293			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
294			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
295			clock-names = "baud", "bus";
296			status = "disabled";
297		};
298
299		uart2: serial@11004000 {
300			compatible = "mediatek,mt8173-uart",
301				     "mediatek,mt6577-uart";
302			reg = <0 0x11004000 0 0x400>;
303			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
304			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
305			clock-names = "baud", "bus";
306			status = "disabled";
307		};
308
309		uart3: serial@11005000 {
310			compatible = "mediatek,mt8173-uart",
311				     "mediatek,mt6577-uart";
312			reg = <0 0x11005000 0 0x400>;
313			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
314			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
315			clock-names = "baud", "bus";
316			status = "disabled";
317		};
318
319		i2c0: i2c@11007000 {
320			compatible = "mediatek,mt8173-i2c";
321			reg = <0 0x11007000 0 0x70>,
322			      <0 0x11000100 0 0x80>;
323			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
324			clock-div = <16>;
325			clocks = <&pericfg CLK_PERI_I2C0>,
326				 <&pericfg CLK_PERI_AP_DMA>;
327			clock-names = "main", "dma";
328			pinctrl-names = "default";
329			pinctrl-0 = <&i2c0_pins_a>;
330			#address-cells = <1>;
331			#size-cells = <0>;
332			status = "disabled";
333		};
334
335		i2c1: i2c@11008000 {
336			compatible = "mediatek,mt8173-i2c";
337			reg = <0 0x11008000 0 0x70>,
338			      <0 0x11000180 0 0x80>;
339			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
340			clock-div = <16>;
341			clocks = <&pericfg CLK_PERI_I2C1>,
342				 <&pericfg CLK_PERI_AP_DMA>;
343			clock-names = "main", "dma";
344			pinctrl-names = "default";
345			pinctrl-0 = <&i2c1_pins_a>;
346			#address-cells = <1>;
347			#size-cells = <0>;
348			status = "disabled";
349		};
350
351		i2c2: i2c@11009000 {
352			compatible = "mediatek,mt8173-i2c";
353			reg = <0 0x11009000 0 0x70>,
354			      <0 0x11000200 0 0x80>;
355			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
356			clock-div = <16>;
357			clocks = <&pericfg CLK_PERI_I2C2>,
358				 <&pericfg CLK_PERI_AP_DMA>;
359			clock-names = "main", "dma";
360			pinctrl-names = "default";
361			pinctrl-0 = <&i2c2_pins_a>;
362			#address-cells = <1>;
363			#size-cells = <0>;
364			status = "disabled";
365		};
366
367		i2c3: i2c3@11010000 {
368			compatible = "mediatek,mt8173-i2c";
369			reg = <0 0x11010000 0 0x70>,
370			      <0 0x11000280 0 0x80>;
371			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
372			clock-div = <16>;
373			clocks = <&pericfg CLK_PERI_I2C3>,
374				 <&pericfg CLK_PERI_AP_DMA>;
375			clock-names = "main", "dma";
376			pinctrl-names = "default";
377			pinctrl-0 = <&i2c3_pins_a>;
378			#address-cells = <1>;
379			#size-cells = <0>;
380			status = "disabled";
381		};
382
383		i2c4: i2c4@11011000 {
384			compatible = "mediatek,mt8173-i2c";
385			reg = <0 0x11011000 0 0x70>,
386			      <0 0x11000300 0 0x80>;
387			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
388			clock-div = <16>;
389			clocks = <&pericfg CLK_PERI_I2C4>,
390				 <&pericfg CLK_PERI_AP_DMA>;
391			clock-names = "main", "dma";
392			pinctrl-names = "default";
393			pinctrl-0 = <&i2c4_pins_a>;
394			#address-cells = <1>;
395			#size-cells = <0>;
396			status = "disabled";
397		};
398
399		i2c6: i2c6@11013000 {
400			compatible = "mediatek,mt8173-i2c";
401			reg = <0 0x11013000 0 0x70>,
402			      <0 0x11000080 0 0x80>;
403			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
404			clock-div = <16>;
405			clocks = <&pericfg CLK_PERI_I2C6>,
406				 <&pericfg CLK_PERI_AP_DMA>;
407			clock-names = "main", "dma";
408			pinctrl-names = "default";
409			pinctrl-0 = <&i2c6_pins_a>;
410			#address-cells = <1>;
411			#size-cells = <0>;
412			status = "disabled";
413		};
414	};
415};
416
417